* [PATCH 0/2] RISC-V: Preparation for more generic linker relaxation
@ 2023-10-14 5:03 Tsukasa OI
2023-10-14 5:03 ` [PATCH 1/2] RISC-V: Group relaxation features Tsukasa OI
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Tsukasa OI @ 2023-10-14 5:03 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson,
Nelson Chu, Kito Cheng
Cc: binutils
Hi,
It *seems* a generic tidying patch set which does nothing useful. However,
this is a part of my attempt to implement Qualcomm's proposal of Code Size
Reduction Instructions (tentatively called 'Zics') but without any 'Zics'-
specific code.
Qualcomm's proposal of Code Size Reduction Instructions:
<https://lists.riscv.org/g/tech-profiles/topic/101784675#332>
My test branch implementing most of them (except assembler/linker support of
PC-relative load instructions):
<https://github.com/a4lg/binutils-gdb/tree/qualcomm_zics>
This patch set intends to improve clarity and maintainability of the linker
relaxation so that 'Zics'-related linker relaxation can be implemented
easily. I believe that it will be helpful even if 'Zics' is not approved.
'Zics' attempts to reduce the code size by providing PC-relative load
instructions (as well as other many additional addressing modes). However,
Qualcomm's proposal of the PC-relative load instructions is exactly the same
as GNU Binutils' macro load instructions (except "lb" and "lbu", that
Qualcomm's proposal does not have a counterpart).
GNU Binutils' macro load instruction:
label:
lw a0, symbol
will generate instruction sequence like this:
0: 00000517 auipc a0,0x0
0: R_RISCV_PCREL_HI20 symbol
0: R_RISCV_RELAX *ABS*
4: 00052503 lw a0,0(a0) # 0 <_start>
4: R_RISCV_PCREL_LO12_I label
4: R_RISCV_RELAX *ABS*
If "symbol" is near enough (relative to the second "lw"), the linker may
relax the instruction sequence like this (pseudo objdump output):
0: d0807503 lw a0,400 <symbol>
# This "lw" encoding is a proposed variant by Qualcomm.
It will require a few changes (riscv_pc_relax_hi_reloc must store additional
information such like reference count to keep track of whether HI20
instruction can be removed; this is because we may not be able to remove
instruction with HI20 relocation if (a) multiple LO12 relocations are
corresponding (b) there are multiple types of linker relaxations utilizing
this type and (c) at least one of them, relaxation possibility is determined
based on the instruction address with LO12 relocation, not HI20 one).
That got a quite long but even if Qualcomm's proposal didn't progress any
further, this patch alone set will be helpful to implement such like
**proper** Zero-page relaxation (current zero-page relaxation reusing the
code from PCREL->GPREL is too restrictive).
Thanks,
Tsukasa
Tsukasa OI (2):
RISC-V: Group relaxation features
RISC-V: Prepare for more generic PCREL relaxations
bfd/elfnn-riscv.c | 176 ++++++++++++++++++++++++++--------------------
1 file changed, 100 insertions(+), 76 deletions(-)
base-commit: 5e2c9ce9c0bf4763a6d17a3a5bee9011ec710f10
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 1/2] RISC-V: Group relaxation features
2023-10-14 5:03 [PATCH 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
@ 2023-10-14 5:03 ` Tsukasa OI
2023-10-14 5:03 ` [PATCH 2/2] RISC-V: Prepare for more generic PCREL relaxations Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2023-10-14 5:03 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson,
Nelson Chu, Kito Cheng
Cc: binutils
From: Tsukasa OI <research_trasio@irq.a4lg.com>
It does not only deduplicate multiple relaxation feature detection,
but enable more complex features so that querying the feature availability
will get too slow if we perform it per-relocation (not per-section).
Even if that wouldn't happen any time soon, it will improve the
maintainability around the linker relaxation code.
bfd/ChangeLog:
* elfnn-riscv.c (RISCV_RELAX_RVC, RISCV_RELAX_GP): New.
(relax_func_t): Add new relax_features argument.
(_bfd_riscv_relax_call): Likewise. Move feature detection to
_bfd_riscv_relax_section. Use bool for simplicity.
(_bfd_riscv_relax_lui): Likewise. Move feature detection to
_bfd_riscv_relax_section.
(_bfd_riscv_relax_tls_le): Likewise but features are not used.
(_bfd_riscv_relax_align): Likewise but features are not used.
(_bfd_riscv_relax_pc): Likewise. Move feature detection to
_bfd_riscv_relax_section.
(_bfd_riscv_relax_section): Detect relaxation-related features
and pass the flags to each relaxation function.
---
bfd/elfnn-riscv.c | 40 +++++++++++++++++++++++++++++-----------
1 file changed, 29 insertions(+), 11 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 09aa7be225ef..15652a08296d 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4085,6 +4085,10 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
return false;
}
+/* Enabled relaxation features to use. */
+#define RISCV_RELAX_RVC 0x01U
+#define RISCV_RELAX_GP 0x02U
+
/* A second format for recording PC-relative hi relocations. This stores the
information required to relax them to GP-relative addresses. */
@@ -4471,7 +4475,8 @@ typedef bool (*relax_func_t) (bfd *, asection *, asection *,
Elf_Internal_Rela *,
bfd_vma, bfd_vma, bfd_vma, bool *,
riscv_pcgp_relocs *,
- bool undefined_weak);
+ bool undefined_weak,
+ unsigned relax_features);
/* Relax AUIPC + JALR into JAL. */
@@ -4484,13 +4489,15 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak ATTRIBUTE_UNUSED)
+ bool undefined_weak ATTRIBUTE_UNUSED,
+ unsigned relax_features)
{
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
bfd_vma foff = symval - (sec_addr (sec) + rel->r_offset);
bool near_zero = (symval + RISCV_IMM_REACH / 2) < RISCV_IMM_REACH;
+ bool rvc = (relax_features & RISCV_RELAX_RVC) != 0;
bfd_vma auipc, jalr;
- int rd, r_type, len = 4, rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+ int rd, r_type, len = 4;
/* If the call crosses section boundaries, an alignment directive could
cause the PC-relative offset to later increase, so we need to add in the
@@ -4590,15 +4597,16 @@ _bfd_riscv_relax_lui (bfd *abfd,
bfd_vma reserve_size,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak)
+ bool undefined_weak,
+ unsigned relax_features)
{
struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (link_info);
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
/* Can relax to x0 even when gp relaxation is disabled. */
- bfd_vma gp = htab->params->relax_gp
+ bfd_vma gp = (relax_features & RISCV_RELAX_GP) != 0
? riscv_global_pointer_value (link_info)
: 0;
- int use_rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+ bool use_rvc = (relax_features & RISCV_RELAX_RVC) != 0;
BFD_ASSERT (rel->r_offset + 4 <= sec->size);
@@ -4703,7 +4711,8 @@ _bfd_riscv_relax_tls_le (bfd *abfd,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak ATTRIBUTE_UNUSED)
+ bool undefined_weak ATTRIBUTE_UNUSED,
+ unsigned relax_features ATTRIBUTE_UNUSED)
{
/* See if this symbol is in range of tp. */
if (RISCV_CONST_HIGH_PART (tpoff (link_info, symval)) != 0)
@@ -4745,7 +4754,8 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again ATTRIBUTE_UNUSED,
riscv_pcgp_relocs *pcgp_relocs ATTRIBUTE_UNUSED,
- bool undefined_weak ATTRIBUTE_UNUSED)
+ bool undefined_weak ATTRIBUTE_UNUSED,
+ unsigned relax_features ATTRIBUTE_UNUSED)
{
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
bfd_vma alignment = 1, pos;
@@ -4805,11 +4815,12 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
bfd_vma reserve_size,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak)
+ bool undefined_weak,
+ unsigned relax_features)
{
struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (link_info);
/* Can relax to x0 even when gp relaxation is disabled. */
- bfd_vma gp = htab->params->relax_gp
+ bfd_vma gp = (relax_features & RISCV_RELAX_GP) != 0
? riscv_global_pointer_value (link_info)
: 0;
@@ -4965,6 +4976,13 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
bfd_vma max_alignment, reserve_size = 0;
riscv_pcgp_relocs pcgp_relocs;
static asection *first_section = NULL;
+ unsigned relax_features = 0;
+
+ /* Detect available/enabled relaxation features. */
+ if (elf_elfheader (abfd)->e_flags & EF_RISCV_RVC)
+ relax_features |= RISCV_RELAX_RVC;
+ if (htab->params->relax_gp)
+ relax_features |= RISCV_RELAX_GP;
*again = false;
@@ -5208,7 +5226,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
if (!relax_func (abfd, sec, sym_sec, info, rel, symval,
max_alignment, reserve_size, again,
- &pcgp_relocs, undefined_weak))
+ &pcgp_relocs, undefined_weak, relax_features))
goto fail;
}
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/2] RISC-V: Prepare for more generic PCREL relaxations
2023-10-14 5:03 [PATCH 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2023-10-14 5:03 ` [PATCH 1/2] RISC-V: Group relaxation features Tsukasa OI
@ 2023-10-14 5:03 ` Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2023-10-14 5:03 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson,
Nelson Chu, Kito Cheng
Cc: binutils
From: Tsukasa OI <research_trasio@irq.a4lg.com>
There's not only Global-pointer Relaxation defined by the RISC-V psABI
Specification. There is also the Zero-page relaxation, making the name
"pcgp" not suitable for storage to PC-relative relocations used in the
linker relaxation passes.
This commit prepares for future changes including proper zero-page
relaxation.
bfd/ChangeLog:
* elfnn-riscv.c
(struct riscv_pcgp_hi_reloc): Rename to...
(struct riscv_pc_relax_hi_reloc): ...here.
(struct riscv_pcgp_lo_reloc): Rename to...
(struct riscv_pc_relax_lo_reloc): ...here.
(riscv_init_pcgp_relocs): Rename to...
(riscv_init_pc_relax_relocs): ...here.
(riscv_free_pcgp_relocs): Rename to...
(riscv_free_pc_relax_relocs): ...here.
(riscv_record_pcgp_hi_reloc): Rename to...
(riscv_record_pc_relax_hi_reloc): ...here.
(riscv_find_pcgp_hi_reloc): Rename to...
(riscv_find_pc_relax_hi_reloc): ...here.
(riscv_record_pcgp_lo_reloc): Rename to...
(riscv_record_pc_relax_lo_reloc): ...here.
(riscv_find_pcgp_lo_reloc): Rename to...
(riscv_find_pc_relax_lo_reloc): ...here.
(riscv_update_pcgp_relocs): Rename to...
(riscv_update_pc_relax_relocs): ...here.
(_riscv_relax_delete_bytes, _riscv_relax_delete_piecewise,
_riscv_relax_delete_immediate, _bfd_riscv_relax_call,
_bfd_riscv_relax_lui, _bfd_riscv_relax_tls_le,
_bfd_riscv_relax_align, _bfd_riscv_relax_pc,
_bfd_riscv_relax_section): Reflect name changes.
---
bfd/elfnn-riscv.c | 138 ++++++++++++++++++++++++----------------------
1 file changed, 72 insertions(+), 66 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 15652a08296d..10ecfe35d170 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4090,10 +4090,10 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
#define RISCV_RELAX_GP 0x02U
/* A second format for recording PC-relative hi relocations. This stores the
- information required to relax them to GP-relative addresses. */
+ information required to relax them to other kinds of relative addresses. */
-typedef struct riscv_pcgp_hi_reloc riscv_pcgp_hi_reloc;
-struct riscv_pcgp_hi_reloc
+typedef struct riscv_pc_relax_hi_reloc riscv_pc_relax_hi_reloc;
+struct riscv_pc_relax_hi_reloc
{
bfd_vma hi_sec_off;
bfd_vma hi_addend;
@@ -4101,68 +4101,69 @@ struct riscv_pcgp_hi_reloc
unsigned hi_sym;
asection *sym_sec;
bool undefined_weak;
- riscv_pcgp_hi_reloc *next;
+ riscv_pc_relax_hi_reloc *next;
};
-typedef struct riscv_pcgp_lo_reloc riscv_pcgp_lo_reloc;
-struct riscv_pcgp_lo_reloc
+typedef struct riscv_pc_relax_lo_reloc riscv_pc_relax_lo_reloc;
+struct riscv_pc_relax_lo_reloc
{
bfd_vma hi_sec_off;
- riscv_pcgp_lo_reloc *next;
+ riscv_pc_relax_lo_reloc *next;
};
typedef struct
{
- riscv_pcgp_hi_reloc *hi;
- riscv_pcgp_lo_reloc *lo;
-} riscv_pcgp_relocs;
+ riscv_pc_relax_hi_reloc *hi;
+ riscv_pc_relax_lo_reloc *lo;
+} riscv_pc_relax_relocs;
-/* Initialize the pcgp reloc info in P. */
+/* Initialize the pc relaxation reloc info in P. */
static bool
-riscv_init_pcgp_relocs (riscv_pcgp_relocs *p)
+riscv_init_pc_relax_relocs (riscv_pc_relax_relocs *p)
{
p->hi = NULL;
p->lo = NULL;
return true;
}
-/* Free the pcgp reloc info in P. */
+/* Free the pc relaxation reloc info in P. */
static void
-riscv_free_pcgp_relocs (riscv_pcgp_relocs *p,
- bfd *abfd ATTRIBUTE_UNUSED,
- asection *sec ATTRIBUTE_UNUSED)
+riscv_free_pc_relax_relocs (riscv_pc_relax_relocs *p,
+ bfd *abfd ATTRIBUTE_UNUSED,
+ asection *sec ATTRIBUTE_UNUSED)
{
- riscv_pcgp_hi_reloc *c;
- riscv_pcgp_lo_reloc *l;
+ riscv_pc_relax_hi_reloc *c;
+ riscv_pc_relax_lo_reloc *l;
for (c = p->hi; c != NULL; )
{
- riscv_pcgp_hi_reloc *next = c->next;
+ riscv_pc_relax_hi_reloc *next = c->next;
free (c);
c = next;
}
for (l = p->lo; l != NULL; )
{
- riscv_pcgp_lo_reloc *next = l->next;
+ riscv_pc_relax_lo_reloc *next = l->next;
free (l);
l = next;
}
}
-/* Record pcgp hi part reloc info in P, using HI_SEC_OFF as the lookup index.
- The HI_ADDEND, HI_ADDR, HI_SYM, and SYM_SEC args contain info required to
- relax the corresponding lo part reloc. */
+/* Record pc relaxation hi part reloc info in P, using HI_SEC_OFF as
+ the lookup index. The HI_ADDEND, HI_ADDR, HI_SYM, and SYM_SEC args
+ contain info required to relax the corresponding lo part reloc. */
static bool
-riscv_record_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off,
- bfd_vma hi_addend, bfd_vma hi_addr,
- unsigned hi_sym, asection *sym_sec,
- bool undefined_weak)
+riscv_record_pc_relax_hi_reloc (riscv_pc_relax_relocs *p,
+ bfd_vma hi_sec_off,
+ bfd_vma hi_addend, bfd_vma hi_addr,
+ unsigned hi_sym, asection *sym_sec,
+ bool undefined_weak)
{
- riscv_pcgp_hi_reloc *new = bfd_malloc (sizeof (*new));
+ riscv_pc_relax_hi_reloc *new = bfd_malloc (sizeof (*new));
if (!new)
return false;
new->hi_sec_off = hi_sec_off;
@@ -4179,10 +4180,10 @@ riscv_record_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off,
/* Look up hi part pcgp reloc info in P, using HI_SEC_OFF as the lookup index.
This is used by a lo part reloc to find the corresponding hi part reloc. */
-static riscv_pcgp_hi_reloc *
-riscv_find_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
+static riscv_pc_relax_hi_reloc *
+riscv_find_pc_relax_hi_reloc (riscv_pc_relax_relocs *p, bfd_vma hi_sec_off)
{
- riscv_pcgp_hi_reloc *c;
+ riscv_pc_relax_hi_reloc *c;
for (c = p->hi; c != NULL; c = c->next)
if (c->hi_sec_off == hi_sec_off)
@@ -4194,9 +4195,10 @@ riscv_find_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
This is used to record relocs that can't be relaxed. */
static bool
-riscv_record_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
+riscv_record_pc_relax_lo_reloc (riscv_pc_relax_relocs *p,
+ bfd_vma hi_sec_off)
{
- riscv_pcgp_lo_reloc *new = bfd_malloc (sizeof (*new));
+ riscv_pc_relax_lo_reloc *new = bfd_malloc (sizeof (*new));
if (!new)
return false;
new->hi_sec_off = hi_sec_off;
@@ -4209,9 +4211,9 @@ riscv_record_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
This is used by a hi part reloc to find the corresponding lo part reloc. */
static bool
-riscv_find_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
+riscv_find_pc_relax_lo_reloc (riscv_pc_relax_relocs *p, bfd_vma hi_sec_off)
{
- riscv_pcgp_lo_reloc *c;
+ riscv_pc_relax_lo_reloc *c;
for (c = p->lo; c != NULL; c = c->next)
if (c->hi_sec_off == hi_sec_off)
@@ -4220,14 +4222,16 @@ riscv_find_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
}
static void
-riscv_update_pcgp_relocs (riscv_pcgp_relocs *p, asection *deleted_sec,
- bfd_vma deleted_addr, size_t deleted_count)
+riscv_update_pc_relax_relocs (riscv_pc_relax_relocs *p,
+ asection *deleted_sec,
+ bfd_vma deleted_addr,
+ size_t deleted_count)
{
/* Bytes have already been deleted and toaddr should match the old section
size for our checks, so adjust it here. */
bfd_vma toaddr = deleted_sec->size + deleted_count;
- riscv_pcgp_lo_reloc *l;
- riscv_pcgp_hi_reloc *h;
+ riscv_pc_relax_lo_reloc *l;
+ riscv_pc_relax_hi_reloc *h;
/* Update section offsets of corresponding pcrel_hi relocs for the pcrel_lo
entries where they occur after the deleted bytes. */
@@ -4258,7 +4262,7 @@ _riscv_relax_delete_bytes (bfd *abfd,
bfd_vma addr,
size_t count,
struct bfd_link_info *link_info,
- riscv_pcgp_relocs *p,
+ riscv_pc_relax_relocs *p,
bfd_vma delete_total,
bfd_vma toaddr)
{
@@ -4287,7 +4291,7 @@ _riscv_relax_delete_bytes (bfd *abfd,
/* Adjust the hi_sec_off, and the hi_addr of any entries in the pcgp relocs
table for which these values occur after the deleted bytes. */
if (p)
- riscv_update_pcgp_relocs (p, sec, addr, count);
+ riscv_update_pc_relax_relocs (p, sec, addr, count);
/* Adjust the local symbols defined in this section. */
for (i = 0; i < symtab_hdr->sh_info; i++)
@@ -4376,7 +4380,7 @@ _riscv_relax_delete_bytes (bfd *abfd,
typedef bool (*relax_delete_t) (bfd *, asection *,
bfd_vma, size_t,
struct bfd_link_info *,
- riscv_pcgp_relocs *,
+ riscv_pc_relax_relocs *,
Elf_Internal_Rela *);
static relax_delete_t riscv_relax_delete_bytes;
@@ -4390,7 +4394,7 @@ _riscv_relax_delete_piecewise (bfd *abfd ATTRIBUTE_UNUSED,
bfd_vma addr,
size_t count,
struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
- riscv_pcgp_relocs *p ATTRIBUTE_UNUSED,
+ riscv_pc_relax_relocs *p ATTRIBUTE_UNUSED,
Elf_Internal_Rela *rel)
{
if (rel == NULL)
@@ -4409,7 +4413,7 @@ _riscv_relax_delete_immediate (bfd *abfd,
bfd_vma addr,
size_t count,
struct bfd_link_info *link_info,
- riscv_pcgp_relocs *p,
+ riscv_pc_relax_relocs *p,
Elf_Internal_Rela *rel)
{
if (rel != NULL)
@@ -4474,7 +4478,7 @@ typedef bool (*relax_func_t) (bfd *, asection *, asection *,
struct bfd_link_info *,
Elf_Internal_Rela *,
bfd_vma, bfd_vma, bfd_vma, bool *,
- riscv_pcgp_relocs *,
+ riscv_pc_relax_relocs *,
bool undefined_weak,
unsigned relax_features);
@@ -4488,7 +4492,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
bfd_vma max_alignment,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak ATTRIBUTE_UNUSED,
unsigned relax_features)
{
@@ -4554,7 +4558,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
/* Delete unnecessary JALR and reuse the R_RISCV_RELAX reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + len, 8 - len,
- link_info, pcgp_relocs, rel + 1);
+ link_info, pc_relax_relocs, rel + 1);
}
/* Traverse all output sections and return the max alignment.
@@ -4596,7 +4600,7 @@ _bfd_riscv_relax_lui (bfd *abfd,
bfd_vma max_alignment,
bfd_vma reserve_size,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak,
unsigned relax_features)
{
@@ -4658,7 +4662,8 @@ _bfd_riscv_relax_lui (bfd *abfd,
/* Delete unnecessary LUI and reuse the reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4,
- link_info, pcgp_relocs, rel);
+ link_info, pc_relax_relocs,
+ rel);
default:
abort ();
@@ -4692,7 +4697,8 @@ _bfd_riscv_relax_lui (bfd *abfd,
/* Delete extra bytes and reuse the R_RISCV_RELAX reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 2, 2,
- link_info, pcgp_relocs, rel + 1);
+ link_info, pc_relax_relocs,
+ rel + 1);
}
return true;
@@ -4710,7 +4716,7 @@ _bfd_riscv_relax_tls_le (bfd *abfd,
bfd_vma max_alignment ATTRIBUTE_UNUSED,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak ATTRIBUTE_UNUSED,
unsigned relax_features ATTRIBUTE_UNUSED)
{
@@ -4734,7 +4740,7 @@ _bfd_riscv_relax_tls_le (bfd *abfd,
/* Delete unnecessary instruction and reuse the reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info,
- pcgp_relocs, rel);
+ pc_relax_relocs, rel);
default:
abort ();
@@ -4753,7 +4759,7 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
bfd_vma max_alignment ATTRIBUTE_UNUSED,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again ATTRIBUTE_UNUSED,
- riscv_pcgp_relocs *pcgp_relocs ATTRIBUTE_UNUSED,
+ riscv_pc_relax_relocs *pc_relax_relocs ATTRIBUTE_UNUSED,
bool undefined_weak ATTRIBUTE_UNUSED,
unsigned relax_features ATTRIBUTE_UNUSED)
{
@@ -4814,7 +4820,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
bfd_vma max_alignment,
bfd_vma reserve_size,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak,
unsigned relax_features)
{
@@ -4828,7 +4834,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* Chain the _LO relocs to their cooresponding _HI reloc to compute the
actual target address. */
- riscv_pcgp_hi_reloc hi_reloc;
+ riscv_pc_relax_hi_reloc hi_reloc;
memset (&hi_reloc, 0, sizeof (hi_reloc));
switch (ELFNN_R_TYPE (rel->r_info))
{
@@ -4840,11 +4846,11 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
hi part instruction. So we must subtract it here for the lookup.
It is still used below in the final symbol address. */
bfd_vma hi_sec_off = symval - sec_addr (sym_sec) - rel->r_addend;
- riscv_pcgp_hi_reloc *hi = riscv_find_pcgp_hi_reloc (pcgp_relocs,
- hi_sec_off);
+ riscv_pc_relax_hi_reloc *hi =
+ riscv_find_pc_relax_hi_reloc (pc_relax_relocs, hi_sec_off);
if (hi == NULL)
{
- riscv_record_pcgp_lo_reloc (pcgp_relocs, hi_sec_off);
+ riscv_record_pc_relax_lo_reloc (pc_relax_relocs, hi_sec_off);
return true;
}
@@ -4855,7 +4861,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* We can not know whether the undefined weak symbol is referenced
according to the information of R_RISCV_PCREL_LO12_I/S. Therefore,
we have to record the 'undefined_weak' flag when handling the
- corresponding R_RISCV_HI20 reloc in riscv_record_pcgp_hi_reloc. */
+ corresponding R_RISCV_HI20 reloc in riscv_record_pc_relax_hi_reloc. */
undefined_weak = hi_reloc.undefined_weak;
}
break;
@@ -4868,7 +4874,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* If the cooresponding lo relocation has already been seen then it's not
safe to relax this relocation. */
- if (riscv_find_pcgp_lo_reloc (pcgp_relocs, rel->r_offset))
+ if (riscv_find_pc_relax_lo_reloc (pc_relax_relocs, rel->r_offset))
return true;
break;
@@ -4924,7 +4930,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
return true;
case R_RISCV_PCREL_HI20:
- riscv_record_pcgp_hi_reloc (pcgp_relocs,
+ riscv_record_pc_relax_hi_reloc (pc_relax_relocs,
rel->r_offset,
rel->r_addend,
symval,
@@ -4934,7 +4940,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* Delete unnecessary AUIPC and reuse the reloc. */
*again = true;
riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info,
- pcgp_relocs, rel);
+ pc_relax_relocs, rel);
return true;
default:
@@ -4974,7 +4980,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
bool ret = false;
unsigned int i;
bfd_vma max_alignment, reserve_size = 0;
- riscv_pcgp_relocs pcgp_relocs;
+ riscv_pc_relax_relocs pc_relax_relocs;
static asection *first_section = NULL;
unsigned relax_features = 0;
@@ -5005,7 +5011,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
else if (first_section == sec)
htab->max_alignment_for_gp = -1;
- riscv_init_pcgp_relocs (&pcgp_relocs);
+ riscv_init_pc_relax_relocs (&pc_relax_relocs);
/* Read this BFD's relocs if we haven't done so already. */
if (data->relocs)
@@ -5226,7 +5232,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
if (!relax_func (abfd, sec, sym_sec, info, rel, symval,
max_alignment, reserve_size, again,
- &pcgp_relocs, undefined_weak, relax_features))
+ &pc_relax_relocs, undefined_weak, relax_features))
goto fail;
}
@@ -5239,7 +5245,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
fail:
if (relocs != data->relocs)
free (relocs);
- riscv_free_pcgp_relocs (&pcgp_relocs, abfd, sec);
+ riscv_free_pc_relax_relocs (&pc_relax_relocs, abfd, sec);
return ret;
}
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation
2023-10-14 5:03 [PATCH 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2023-10-14 5:03 ` [PATCH 1/2] RISC-V: Group relaxation features Tsukasa OI
2023-10-14 5:03 ` [PATCH 2/2] RISC-V: Prepare for more generic PCREL relaxations Tsukasa OI
@ 2023-10-15 0:44 ` Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 1/2] RISC-V: Group linker relaxation features Tsukasa OI
` (2 more replies)
2 siblings, 3 replies; 10+ messages in thread
From: Tsukasa OI @ 2023-10-15 0:44 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson,
Nelson Chu, Kito Cheng
Cc: binutils
Hi,
For details, see the cover letter of PATCH v1.
PATCH v1:
<https://sourceware.org/pipermail/binutils/2023-October/129952.html>
Changes: v1->v2
1. [1/2] Minor fix to the commit message
2. [1/2] Deduplicate bfd_link_pic(info)
as RISCV_RELAX_PIC feature flag
3. [2/2] Change some function description comment
from "GP-relative" to "GP/zero-relative".
Thanks,
Tsukasa
Tsukasa OI (2):
RISC-V: Group linker relaxation features
RISC-V: Prepare for more generic PCREL relaxations
bfd/elfnn-riscv.c | 191 ++++++++++++++++++++++++++--------------------
1 file changed, 110 insertions(+), 81 deletions(-)
base-commit: cd09b5ddefe662dcaa793cfa348730cbdee1e01b
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 1/2] RISC-V: Group linker relaxation features
2023-10-15 0:44 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
@ 2023-10-15 0:44 ` Tsukasa OI
2023-10-15 2:33 ` Nelson Chu
2023-10-15 0:44 ` [PATCH v2 2/2] RISC-V: Prepare for more generic PCREL relaxations Tsukasa OI
2023-10-15 2:29 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Nelson Chu
2 siblings, 1 reply; 10+ messages in thread
From: Tsukasa OI @ 2023-10-15 0:44 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson,
Nelson Chu, Kito Cheng
Cc: binutils
From: Tsukasa OI <research_trasio@irq.a4lg.com>
It does not only deduplicate multiple relaxation feature detection,
but enable more complex features so that querying the feature availability
will get too slow if we perform it per-relocation (not per-section).
Even if that wouldn't happen any time soon, it will improve the
maintainability around the linker relaxation code.
bfd/ChangeLog:
* elfnn-riscv.c (RISCV_RELAX_RVC, RISCV_RELAX_GP): New.
(relax_func_t): Add new relax_features argument.
(_bfd_riscv_relax_call): Likewise. Move feature detection to
_bfd_riscv_relax_section. Use bool for simplicity.
(_bfd_riscv_relax_lui): Likewise. Move feature detection to
_bfd_riscv_relax_section.
(_bfd_riscv_relax_tls_le): Likewise but features are not used.
(_bfd_riscv_relax_align): Likewise but features are not used.
(_bfd_riscv_relax_pc): Likewise. Move feature detection to
_bfd_riscv_relax_section.
(_bfd_riscv_relax_section): Detect relaxation-related features
and pass the flags to each relaxation function. Use the PIC
feature flag generated by itself.
---
bfd/elfnn-riscv.c | 50 ++++++++++++++++++++++++++++++++++-------------
1 file changed, 36 insertions(+), 14 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 09aa7be225ef..947a02d44478 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4085,6 +4085,11 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
return false;
}
+/* Enabled relaxation features to use. */
+#define RISCV_RELAX_RVC 0x01U
+#define RISCV_RELAX_GP 0x02U
+#define RISCV_RELAX_PIC 0x04U
+
/* A second format for recording PC-relative hi relocations. This stores the
information required to relax them to GP-relative addresses. */
@@ -4471,7 +4476,8 @@ typedef bool (*relax_func_t) (bfd *, asection *, asection *,
Elf_Internal_Rela *,
bfd_vma, bfd_vma, bfd_vma, bool *,
riscv_pcgp_relocs *,
- bool undefined_weak);
+ bool undefined_weak,
+ unsigned relax_features);
/* Relax AUIPC + JALR into JAL. */
@@ -4484,13 +4490,15 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak ATTRIBUTE_UNUSED)
+ bool undefined_weak ATTRIBUTE_UNUSED,
+ unsigned relax_features)
{
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
bfd_vma foff = symval - (sec_addr (sec) + rel->r_offset);
bool near_zero = (symval + RISCV_IMM_REACH / 2) < RISCV_IMM_REACH;
+ bool rvc = (relax_features & RISCV_RELAX_RVC) != 0;
bfd_vma auipc, jalr;
- int rd, r_type, len = 4, rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+ int rd, r_type, len = 4;
/* If the call crosses section boundaries, an alignment directive could
cause the PC-relative offset to later increase, so we need to add in the
@@ -4505,7 +4513,8 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
}
/* See if this function call can be shortened. */
- if (!VALID_JTYPE_IMM (foff) && !(!bfd_link_pic (link_info) && near_zero))
+ if (!VALID_JTYPE_IMM (foff)
+ && !(!(relax_features & RISCV_RELAX_PIC) && near_zero))
return true;
/* Shorten the function call. */
@@ -4590,15 +4599,16 @@ _bfd_riscv_relax_lui (bfd *abfd,
bfd_vma reserve_size,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak)
+ bool undefined_weak,
+ unsigned relax_features)
{
struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (link_info);
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
/* Can relax to x0 even when gp relaxation is disabled. */
- bfd_vma gp = htab->params->relax_gp
+ bfd_vma gp = (relax_features & RISCV_RELAX_GP) != 0
? riscv_global_pointer_value (link_info)
: 0;
- int use_rvc = elf_elfheader (abfd)->e_flags & EF_RISCV_RVC;
+ bool use_rvc = (relax_features & RISCV_RELAX_RVC) != 0;
BFD_ASSERT (rel->r_offset + 4 <= sec->size);
@@ -4703,7 +4713,8 @@ _bfd_riscv_relax_tls_le (bfd *abfd,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak ATTRIBUTE_UNUSED)
+ bool undefined_weak ATTRIBUTE_UNUSED,
+ unsigned relax_features ATTRIBUTE_UNUSED)
{
/* See if this symbol is in range of tp. */
if (RISCV_CONST_HIGH_PART (tpoff (link_info, symval)) != 0)
@@ -4745,7 +4756,8 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again ATTRIBUTE_UNUSED,
riscv_pcgp_relocs *pcgp_relocs ATTRIBUTE_UNUSED,
- bool undefined_weak ATTRIBUTE_UNUSED)
+ bool undefined_weak ATTRIBUTE_UNUSED,
+ unsigned relax_features ATTRIBUTE_UNUSED)
{
bfd_byte *contents = elf_section_data (sec)->this_hdr.contents;
bfd_vma alignment = 1, pos;
@@ -4805,11 +4817,12 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
bfd_vma reserve_size,
bool *again,
riscv_pcgp_relocs *pcgp_relocs,
- bool undefined_weak)
+ bool undefined_weak,
+ unsigned relax_features)
{
struct riscv_elf_link_hash_table *htab = riscv_elf_hash_table (link_info);
/* Can relax to x0 even when gp relaxation is disabled. */
- bfd_vma gp = htab->params->relax_gp
+ bfd_vma gp = (relax_features & RISCV_RELAX_GP) != 0
? riscv_global_pointer_value (link_info)
: 0;
@@ -4965,6 +4978,15 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
bfd_vma max_alignment, reserve_size = 0;
riscv_pcgp_relocs pcgp_relocs;
static asection *first_section = NULL;
+ unsigned relax_features = 0;
+
+ /* Detect available/enabled relaxation features. */
+ if (elf_elfheader (abfd)->e_flags & EF_RISCV_RVC)
+ relax_features |= RISCV_RELAX_RVC;
+ if (htab->params->relax_gp)
+ relax_features |= RISCV_RELAX_GP;
+ if (bfd_link_pic (info))
+ relax_features |= RISCV_RELAX_PIC;
*again = false;
@@ -5032,7 +5054,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
|| type == R_RISCV_TPREL_LO12_I
|| type == R_RISCV_TPREL_LO12_S)
relax_func = _bfd_riscv_relax_tls_le;
- else if (!bfd_link_pic (info)
+ else if (!(relax_features & RISCV_RELAX_PIC)
&& (type == R_RISCV_PCREL_HI20
|| type == R_RISCV_PCREL_LO12_I
|| type == R_RISCV_PCREL_LO12_S))
@@ -5145,7 +5167,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
/* This line has to match the check in riscv_elf_relocate_section
in the R_RISCV_CALL[_PLT] case. */
- if (bfd_link_pic (info) && h->plt.offset != MINUS_ONE)
+ if ((relax_features & RISCV_RELAX_PIC) && h->plt.offset != MINUS_ONE)
{
sym_sec = htab->elf.splt;
symval = h->plt.offset;
@@ -5208,7 +5230,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
if (!relax_func (abfd, sec, sym_sec, info, rel, symval,
max_alignment, reserve_size, again,
- &pcgp_relocs, undefined_weak))
+ &pcgp_relocs, undefined_weak, relax_features))
goto fail;
}
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v2 2/2] RISC-V: Prepare for more generic PCREL relaxations
2023-10-15 0:44 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 1/2] RISC-V: Group linker relaxation features Tsukasa OI
@ 2023-10-15 0:44 ` Tsukasa OI
2023-10-15 2:29 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Nelson Chu
2 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2023-10-15 0:44 UTC (permalink / raw)
To: Tsukasa OI, Palmer Dabbelt, Andrew Waterman, Jim Wilson,
Nelson Chu, Kito Cheng
Cc: binutils
From: Tsukasa OI <research_trasio@irq.a4lg.com>
There's not only Global-pointer Relaxation defined by the RISC-V psABI
Specification. There is also the Zero-page relaxation, making the name
"pcgp" not suitable for storage to PC-relative relocations used in the
linker relaxation passes.
This commit prepares for future changes including proper zero-page
relaxation.
bfd/ChangeLog:
* elfnn-riscv.c
(struct riscv_pcgp_hi_reloc): Rename to...
(struct riscv_pc_relax_hi_reloc): ...here.
(struct riscv_pcgp_lo_reloc): Rename to...
(struct riscv_pc_relax_lo_reloc): ...here.
(riscv_init_pcgp_relocs): Rename to...
(riscv_init_pc_relax_relocs): ...here.
(riscv_free_pcgp_relocs): Rename to...
(riscv_free_pc_relax_relocs): ...here.
(riscv_record_pcgp_hi_reloc): Rename to...
(riscv_record_pc_relax_hi_reloc): ...here.
(riscv_find_pcgp_hi_reloc): Rename to...
(riscv_find_pc_relax_hi_reloc): ...here.
(riscv_record_pcgp_lo_reloc): Rename to...
(riscv_record_pc_relax_lo_reloc): ...here.
(riscv_find_pcgp_lo_reloc): Rename to...
(riscv_find_pc_relax_lo_reloc): ...here.
(riscv_update_pcgp_relocs): Rename to...
(riscv_update_pc_relax_relocs): ...here.
(_riscv_relax_delete_bytes, _riscv_relax_delete_piecewise,
_riscv_relax_delete_immediate, _bfd_riscv_relax_call,
_bfd_riscv_relax_tls_le, _bfd_riscv_relax_align,
_bfd_riscv_relax_section): Reflect name changes.
(_bfd_riscv_relax_lui, _bfd_riscv_relax_pc):
Likewise. Also change "GP-relative" to "GP/zero-relative"
in the function description comment.
---
bfd/elfnn-riscv.c | 143 ++++++++++++++++++++++++----------------------
1 file changed, 75 insertions(+), 68 deletions(-)
diff --git a/bfd/elfnn-riscv.c b/bfd/elfnn-riscv.c
index 947a02d44478..97ed74ffa91e 100644
--- a/bfd/elfnn-riscv.c
+++ b/bfd/elfnn-riscv.c
@@ -4091,10 +4091,10 @@ _bfd_riscv_elf_merge_private_bfd_data (bfd *ibfd, struct bfd_link_info *info)
#define RISCV_RELAX_PIC 0x04U
/* A second format for recording PC-relative hi relocations. This stores the
- information required to relax them to GP-relative addresses. */
+ information required to relax them to other kinds of relative addresses. */
-typedef struct riscv_pcgp_hi_reloc riscv_pcgp_hi_reloc;
-struct riscv_pcgp_hi_reloc
+typedef struct riscv_pc_relax_hi_reloc riscv_pc_relax_hi_reloc;
+struct riscv_pc_relax_hi_reloc
{
bfd_vma hi_sec_off;
bfd_vma hi_addend;
@@ -4102,68 +4102,69 @@ struct riscv_pcgp_hi_reloc
unsigned hi_sym;
asection *sym_sec;
bool undefined_weak;
- riscv_pcgp_hi_reloc *next;
+ riscv_pc_relax_hi_reloc *next;
};
-typedef struct riscv_pcgp_lo_reloc riscv_pcgp_lo_reloc;
-struct riscv_pcgp_lo_reloc
+typedef struct riscv_pc_relax_lo_reloc riscv_pc_relax_lo_reloc;
+struct riscv_pc_relax_lo_reloc
{
bfd_vma hi_sec_off;
- riscv_pcgp_lo_reloc *next;
+ riscv_pc_relax_lo_reloc *next;
};
typedef struct
{
- riscv_pcgp_hi_reloc *hi;
- riscv_pcgp_lo_reloc *lo;
-} riscv_pcgp_relocs;
+ riscv_pc_relax_hi_reloc *hi;
+ riscv_pc_relax_lo_reloc *lo;
+} riscv_pc_relax_relocs;
-/* Initialize the pcgp reloc info in P. */
+/* Initialize the pc relaxation reloc info in P. */
static bool
-riscv_init_pcgp_relocs (riscv_pcgp_relocs *p)
+riscv_init_pc_relax_relocs (riscv_pc_relax_relocs *p)
{
p->hi = NULL;
p->lo = NULL;
return true;
}
-/* Free the pcgp reloc info in P. */
+/* Free the pc relaxation reloc info in P. */
static void
-riscv_free_pcgp_relocs (riscv_pcgp_relocs *p,
- bfd *abfd ATTRIBUTE_UNUSED,
- asection *sec ATTRIBUTE_UNUSED)
+riscv_free_pc_relax_relocs (riscv_pc_relax_relocs *p,
+ bfd *abfd ATTRIBUTE_UNUSED,
+ asection *sec ATTRIBUTE_UNUSED)
{
- riscv_pcgp_hi_reloc *c;
- riscv_pcgp_lo_reloc *l;
+ riscv_pc_relax_hi_reloc *c;
+ riscv_pc_relax_lo_reloc *l;
for (c = p->hi; c != NULL; )
{
- riscv_pcgp_hi_reloc *next = c->next;
+ riscv_pc_relax_hi_reloc *next = c->next;
free (c);
c = next;
}
for (l = p->lo; l != NULL; )
{
- riscv_pcgp_lo_reloc *next = l->next;
+ riscv_pc_relax_lo_reloc *next = l->next;
free (l);
l = next;
}
}
-/* Record pcgp hi part reloc info in P, using HI_SEC_OFF as the lookup index.
- The HI_ADDEND, HI_ADDR, HI_SYM, and SYM_SEC args contain info required to
- relax the corresponding lo part reloc. */
+/* Record pc relaxation hi part reloc info in P, using HI_SEC_OFF as
+ the lookup index. The HI_ADDEND, HI_ADDR, HI_SYM, and SYM_SEC args
+ contain info required to relax the corresponding lo part reloc. */
static bool
-riscv_record_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off,
- bfd_vma hi_addend, bfd_vma hi_addr,
- unsigned hi_sym, asection *sym_sec,
- bool undefined_weak)
+riscv_record_pc_relax_hi_reloc (riscv_pc_relax_relocs *p,
+ bfd_vma hi_sec_off,
+ bfd_vma hi_addend, bfd_vma hi_addr,
+ unsigned hi_sym, asection *sym_sec,
+ bool undefined_weak)
{
- riscv_pcgp_hi_reloc *new = bfd_malloc (sizeof (*new));
+ riscv_pc_relax_hi_reloc *new = bfd_malloc (sizeof (*new));
if (!new)
return false;
new->hi_sec_off = hi_sec_off;
@@ -4180,10 +4181,10 @@ riscv_record_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off,
/* Look up hi part pcgp reloc info in P, using HI_SEC_OFF as the lookup index.
This is used by a lo part reloc to find the corresponding hi part reloc. */
-static riscv_pcgp_hi_reloc *
-riscv_find_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
+static riscv_pc_relax_hi_reloc *
+riscv_find_pc_relax_hi_reloc (riscv_pc_relax_relocs *p, bfd_vma hi_sec_off)
{
- riscv_pcgp_hi_reloc *c;
+ riscv_pc_relax_hi_reloc *c;
for (c = p->hi; c != NULL; c = c->next)
if (c->hi_sec_off == hi_sec_off)
@@ -4195,9 +4196,10 @@ riscv_find_pcgp_hi_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
This is used to record relocs that can't be relaxed. */
static bool
-riscv_record_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
+riscv_record_pc_relax_lo_reloc (riscv_pc_relax_relocs *p,
+ bfd_vma hi_sec_off)
{
- riscv_pcgp_lo_reloc *new = bfd_malloc (sizeof (*new));
+ riscv_pc_relax_lo_reloc *new = bfd_malloc (sizeof (*new));
if (!new)
return false;
new->hi_sec_off = hi_sec_off;
@@ -4210,9 +4212,9 @@ riscv_record_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
This is used by a hi part reloc to find the corresponding lo part reloc. */
static bool
-riscv_find_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
+riscv_find_pc_relax_lo_reloc (riscv_pc_relax_relocs *p, bfd_vma hi_sec_off)
{
- riscv_pcgp_lo_reloc *c;
+ riscv_pc_relax_lo_reloc *c;
for (c = p->lo; c != NULL; c = c->next)
if (c->hi_sec_off == hi_sec_off)
@@ -4221,14 +4223,16 @@ riscv_find_pcgp_lo_reloc (riscv_pcgp_relocs *p, bfd_vma hi_sec_off)
}
static void
-riscv_update_pcgp_relocs (riscv_pcgp_relocs *p, asection *deleted_sec,
- bfd_vma deleted_addr, size_t deleted_count)
+riscv_update_pc_relax_relocs (riscv_pc_relax_relocs *p,
+ asection *deleted_sec,
+ bfd_vma deleted_addr,
+ size_t deleted_count)
{
/* Bytes have already been deleted and toaddr should match the old section
size for our checks, so adjust it here. */
bfd_vma toaddr = deleted_sec->size + deleted_count;
- riscv_pcgp_lo_reloc *l;
- riscv_pcgp_hi_reloc *h;
+ riscv_pc_relax_lo_reloc *l;
+ riscv_pc_relax_hi_reloc *h;
/* Update section offsets of corresponding pcrel_hi relocs for the pcrel_lo
entries where they occur after the deleted bytes. */
@@ -4259,7 +4263,7 @@ _riscv_relax_delete_bytes (bfd *abfd,
bfd_vma addr,
size_t count,
struct bfd_link_info *link_info,
- riscv_pcgp_relocs *p,
+ riscv_pc_relax_relocs *p,
bfd_vma delete_total,
bfd_vma toaddr)
{
@@ -4288,7 +4292,7 @@ _riscv_relax_delete_bytes (bfd *abfd,
/* Adjust the hi_sec_off, and the hi_addr of any entries in the pcgp relocs
table for which these values occur after the deleted bytes. */
if (p)
- riscv_update_pcgp_relocs (p, sec, addr, count);
+ riscv_update_pc_relax_relocs (p, sec, addr, count);
/* Adjust the local symbols defined in this section. */
for (i = 0; i < symtab_hdr->sh_info; i++)
@@ -4377,7 +4381,7 @@ _riscv_relax_delete_bytes (bfd *abfd,
typedef bool (*relax_delete_t) (bfd *, asection *,
bfd_vma, size_t,
struct bfd_link_info *,
- riscv_pcgp_relocs *,
+ riscv_pc_relax_relocs *,
Elf_Internal_Rela *);
static relax_delete_t riscv_relax_delete_bytes;
@@ -4391,7 +4395,7 @@ _riscv_relax_delete_piecewise (bfd *abfd ATTRIBUTE_UNUSED,
bfd_vma addr,
size_t count,
struct bfd_link_info *link_info ATTRIBUTE_UNUSED,
- riscv_pcgp_relocs *p ATTRIBUTE_UNUSED,
+ riscv_pc_relax_relocs *p ATTRIBUTE_UNUSED,
Elf_Internal_Rela *rel)
{
if (rel == NULL)
@@ -4410,7 +4414,7 @@ _riscv_relax_delete_immediate (bfd *abfd,
bfd_vma addr,
size_t count,
struct bfd_link_info *link_info,
- riscv_pcgp_relocs *p,
+ riscv_pc_relax_relocs *p,
Elf_Internal_Rela *rel)
{
if (rel != NULL)
@@ -4475,7 +4479,7 @@ typedef bool (*relax_func_t) (bfd *, asection *, asection *,
struct bfd_link_info *,
Elf_Internal_Rela *,
bfd_vma, bfd_vma, bfd_vma, bool *,
- riscv_pcgp_relocs *,
+ riscv_pc_relax_relocs *,
bool undefined_weak,
unsigned relax_features);
@@ -4489,7 +4493,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
bfd_vma max_alignment,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak ATTRIBUTE_UNUSED,
unsigned relax_features)
{
@@ -4556,7 +4560,7 @@ _bfd_riscv_relax_call (bfd *abfd, asection *sec, asection *sym_sec,
/* Delete unnecessary JALR and reuse the R_RISCV_RELAX reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + len, 8 - len,
- link_info, pcgp_relocs, rel + 1);
+ link_info, pc_relax_relocs, rel + 1);
}
/* Traverse all output sections and return the max alignment.
@@ -4586,7 +4590,8 @@ _bfd_riscv_get_max_alignment (asection *sec, bfd_vma gp)
return (bfd_vma) 1 << max_alignment_power;
}
-/* Relax non-PIC global variable references to GP-relative references. */
+/* Relax non-PIC global variable references to
+ GP/zero-relative references. */
static bool
_bfd_riscv_relax_lui (bfd *abfd,
@@ -4598,7 +4603,7 @@ _bfd_riscv_relax_lui (bfd *abfd,
bfd_vma max_alignment,
bfd_vma reserve_size,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak,
unsigned relax_features)
{
@@ -4660,7 +4665,8 @@ _bfd_riscv_relax_lui (bfd *abfd,
/* Delete unnecessary LUI and reuse the reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4,
- link_info, pcgp_relocs, rel);
+ link_info, pc_relax_relocs,
+ rel);
default:
abort ();
@@ -4694,7 +4700,8 @@ _bfd_riscv_relax_lui (bfd *abfd,
/* Delete extra bytes and reuse the R_RISCV_RELAX reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset + 2, 2,
- link_info, pcgp_relocs, rel + 1);
+ link_info, pc_relax_relocs,
+ rel + 1);
}
return true;
@@ -4712,7 +4719,7 @@ _bfd_riscv_relax_tls_le (bfd *abfd,
bfd_vma max_alignment ATTRIBUTE_UNUSED,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak ATTRIBUTE_UNUSED,
unsigned relax_features ATTRIBUTE_UNUSED)
{
@@ -4736,7 +4743,7 @@ _bfd_riscv_relax_tls_le (bfd *abfd,
/* Delete unnecessary instruction and reuse the reloc. */
*again = true;
return riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info,
- pcgp_relocs, rel);
+ pc_relax_relocs, rel);
default:
abort ();
@@ -4755,7 +4762,7 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
bfd_vma max_alignment ATTRIBUTE_UNUSED,
bfd_vma reserve_size ATTRIBUTE_UNUSED,
bool *again ATTRIBUTE_UNUSED,
- riscv_pcgp_relocs *pcgp_relocs ATTRIBUTE_UNUSED,
+ riscv_pc_relax_relocs *pc_relax_relocs ATTRIBUTE_UNUSED,
bool undefined_weak ATTRIBUTE_UNUSED,
unsigned relax_features ATTRIBUTE_UNUSED)
{
@@ -4804,7 +4811,7 @@ _bfd_riscv_relax_align (bfd *abfd, asection *sec,
NULL, NULL);
}
-/* Relax PC-relative references to GP-relative references. */
+/* Relax PC-relative references to GP/zero-relative references. */
static bool
_bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
@@ -4816,7 +4823,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
bfd_vma max_alignment,
bfd_vma reserve_size,
bool *again,
- riscv_pcgp_relocs *pcgp_relocs,
+ riscv_pc_relax_relocs *pc_relax_relocs,
bool undefined_weak,
unsigned relax_features)
{
@@ -4830,7 +4837,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* Chain the _LO relocs to their cooresponding _HI reloc to compute the
actual target address. */
- riscv_pcgp_hi_reloc hi_reloc;
+ riscv_pc_relax_hi_reloc hi_reloc;
memset (&hi_reloc, 0, sizeof (hi_reloc));
switch (ELFNN_R_TYPE (rel->r_info))
{
@@ -4842,11 +4849,11 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
hi part instruction. So we must subtract it here for the lookup.
It is still used below in the final symbol address. */
bfd_vma hi_sec_off = symval - sec_addr (sym_sec) - rel->r_addend;
- riscv_pcgp_hi_reloc *hi = riscv_find_pcgp_hi_reloc (pcgp_relocs,
- hi_sec_off);
+ riscv_pc_relax_hi_reloc *hi =
+ riscv_find_pc_relax_hi_reloc (pc_relax_relocs, hi_sec_off);
if (hi == NULL)
{
- riscv_record_pcgp_lo_reloc (pcgp_relocs, hi_sec_off);
+ riscv_record_pc_relax_lo_reloc (pc_relax_relocs, hi_sec_off);
return true;
}
@@ -4857,7 +4864,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* We can not know whether the undefined weak symbol is referenced
according to the information of R_RISCV_PCREL_LO12_I/S. Therefore,
we have to record the 'undefined_weak' flag when handling the
- corresponding R_RISCV_HI20 reloc in riscv_record_pcgp_hi_reloc. */
+ corresponding R_RISCV_HI20 reloc in riscv_record_pc_relax_hi_reloc. */
undefined_weak = hi_reloc.undefined_weak;
}
break;
@@ -4870,7 +4877,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* If the cooresponding lo relocation has already been seen then it's not
safe to relax this relocation. */
- if (riscv_find_pcgp_lo_reloc (pcgp_relocs, rel->r_offset))
+ if (riscv_find_pc_relax_lo_reloc (pc_relax_relocs, rel->r_offset))
return true;
break;
@@ -4926,7 +4933,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
return true;
case R_RISCV_PCREL_HI20:
- riscv_record_pcgp_hi_reloc (pcgp_relocs,
+ riscv_record_pc_relax_hi_reloc (pc_relax_relocs,
rel->r_offset,
rel->r_addend,
symval,
@@ -4936,7 +4943,7 @@ _bfd_riscv_relax_pc (bfd *abfd ATTRIBUTE_UNUSED,
/* Delete unnecessary AUIPC and reuse the reloc. */
*again = true;
riscv_relax_delete_bytes (abfd, sec, rel->r_offset, 4, link_info,
- pcgp_relocs, rel);
+ pc_relax_relocs, rel);
return true;
default:
@@ -4976,7 +4983,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
bool ret = false;
unsigned int i;
bfd_vma max_alignment, reserve_size = 0;
- riscv_pcgp_relocs pcgp_relocs;
+ riscv_pc_relax_relocs pc_relax_relocs;
static asection *first_section = NULL;
unsigned relax_features = 0;
@@ -5009,7 +5016,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
else if (first_section == sec)
htab->max_alignment_for_gp = -1;
- riscv_init_pcgp_relocs (&pcgp_relocs);
+ riscv_init_pc_relax_relocs (&pc_relax_relocs);
/* Read this BFD's relocs if we haven't done so already. */
if (data->relocs)
@@ -5230,7 +5237,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
if (!relax_func (abfd, sec, sym_sec, info, rel, symval,
max_alignment, reserve_size, again,
- &pcgp_relocs, undefined_weak, relax_features))
+ &pc_relax_relocs, undefined_weak, relax_features))
goto fail;
}
@@ -5243,7 +5250,7 @@ _bfd_riscv_relax_section (bfd *abfd, asection *sec,
fail:
if (relocs != data->relocs)
free (relocs);
- riscv_free_pcgp_relocs (&pcgp_relocs, abfd, sec);
+ riscv_free_pc_relax_relocs (&pc_relax_relocs, abfd, sec);
return ret;
}
--
2.42.0
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation
2023-10-15 0:44 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 1/2] RISC-V: Group linker relaxation features Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 2/2] RISC-V: Prepare for more generic PCREL relaxations Tsukasa OI
@ 2023-10-15 2:29 ` Nelson Chu
2023-10-15 5:12 ` Tsukasa OI
2 siblings, 1 reply; 10+ messages in thread
From: Nelson Chu @ 2023-10-15 2:29 UTC (permalink / raw)
To: Tsukasa OI
Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Kito Cheng, binutils
[-- Attachment #1: Type: text/plain, Size: 667 bytes --]
On Sun, Oct 15, 2023 at 8:44 AM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:
> Hi,
>
> For details, see the cover letter of PATCH v1.
>
> PATCH v1:
> <https://sourceware.org/pipermail/binutils/2023-October/129952.html>
>
> Changes: v1->v2
> 1. [1/2] Minor fix to the commit message
> 2. [1/2] Deduplicate bfd_link_pic(info)
> as RISCV_RELAX_PIC feature flag
>
PIC isn't a relaxation feature, and we used to use bfd_link_pic everywhere,
so it seems no good to define it to another RISCV_RELAX_PIC.
Nelson
> 3. [2/2] Change some function description comment
> from "GP-relative" to "GP/zero-relative".
>
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] RISC-V: Group linker relaxation features
2023-10-15 0:44 ` [PATCH v2 1/2] RISC-V: Group linker relaxation features Tsukasa OI
@ 2023-10-15 2:33 ` Nelson Chu
2023-10-15 5:07 ` Tsukasa OI
0 siblings, 1 reply; 10+ messages in thread
From: Nelson Chu @ 2023-10-15 2:33 UTC (permalink / raw)
To: Tsukasa OI
Cc: Palmer Dabbelt, Andrew Waterman, Jim Wilson, Kito Cheng, binutils
[-- Attachment #1: Type: text/plain, Size: 574 bytes --]
On Sun, Oct 15, 2023 at 8:44 AM Tsukasa OI <research_trasio@irq.a4lg.com>
wrote:
> From: Tsukasa OI <research_trasio@irq.a4lg.com>
>
> It does not only deduplicate multiple relaxation feature detection,
> but enable more complex features so that querying the feature availability
> will get too slow if we perform it per-relocation (not per-section).
>
> Even if that wouldn't happen any time soon, it will improve the
> maintainability around the linker relaxation code.
>
>
I think the current implementation is good enough to maintain, thanks.
Nelson
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 1/2] RISC-V: Group linker relaxation features
2023-10-15 2:33 ` Nelson Chu
@ 2023-10-15 5:07 ` Tsukasa OI
0 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2023-10-15 5:07 UTC (permalink / raw)
To: Binutils
On 2023/10/15 11:33, Nelson Chu wrote:
>
>
> On Sun, Oct 15, 2023 at 8:44 AM Tsukasa OI <research_trasio@irq.a4lg.com
> <mailto:research_trasio@irq.a4lg.com>> wrote:
>
> From: Tsukasa OI <research_trasio@irq.a4lg.com
> <mailto:research_trasio@irq.a4lg.com>>
>
> It does not only deduplicate multiple relaxation feature detection,
> but enable more complex features so that querying the feature
> availability
> will get too slow if we perform it per-relocation (not per-section).
>
> Even if that wouldn't happen any time soon, it will improve the
> maintainability around the linker relaxation code.
>
>
> I think the current implementation is good enough to maintain, thanks.
>
> Nelson
>
I agree if we are not going to add/modify other kinds of linker
relaxations. But this isn't the case.
Tsukasa
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation
2023-10-15 2:29 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Nelson Chu
@ 2023-10-15 5:12 ` Tsukasa OI
0 siblings, 0 replies; 10+ messages in thread
From: Tsukasa OI @ 2023-10-15 5:12 UTC (permalink / raw)
To: Nelson Chu, Binutils
On 2023/10/15 11:29, Nelson Chu wrote:
>
>
> On Sun, Oct 15, 2023 at 8:44 AM Tsukasa OI <research_trasio@irq.a4lg.com
> <mailto:research_trasio@irq.a4lg.com>> wrote:
>
> Hi,
>
> For details, see the cover letter of PATCH v1.
>
> PATCH v1:
> <https://sourceware.org/pipermail/binutils/2023-October/129952.html
> <https://sourceware.org/pipermail/binutils/2023-October/129952.html>>
>
> Changes: v1->v2
> 1. [1/2] Minor fix to the commit message
> 2. [1/2] Deduplicate bfd_link_pic(info)
> as RISCV_RELAX_PIC feature flag
>
>
> PIC isn't a relaxation feature, and we used to use bfd_link_pic
> everywhere, so it seems no good to define it to another RISCV_RELAX_PIC.
>
> Nelson
Okay, (about PIC) I agree that it's not worth it. Even for performance
reasons, the possible improvement will be marginal (too small to get
real improvements). I'll withdraw this part from the next version.
I hope that you accept the rest (obviously you didn't as in another
e-mail but hope that you reconsider; this is just a preparation for
other changes regarding linker relaxation).
Thanks,
Tsukasa
>
>
> 3. [2/2] Change some function description comment
> from "GP-relative" to "GP/zero-relative".
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2023-10-15 5:12 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-10-14 5:03 [PATCH 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2023-10-14 5:03 ` [PATCH 1/2] RISC-V: Group relaxation features Tsukasa OI
2023-10-14 5:03 ` [PATCH 2/2] RISC-V: Prepare for more generic PCREL relaxations Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 1/2] RISC-V: Group linker relaxation features Tsukasa OI
2023-10-15 2:33 ` Nelson Chu
2023-10-15 5:07 ` Tsukasa OI
2023-10-15 0:44 ` [PATCH v2 2/2] RISC-V: Prepare for more generic PCREL relaxations Tsukasa OI
2023-10-15 2:29 ` [PATCH v2 0/2] RISC-V: Preparation for more generic linker relaxation Nelson Chu
2023-10-15 5:12 ` Tsukasa OI
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