[PATCH] Sanitize RISC-V GAS help text, documentation

[PATCH] Sanitize RISC-V GAS help text, documentation

[Palmer Dabbelt]

It looks like I missed the GAS help text when going through all the
documentation last time, so it printed some of the old-format (never
upstream) arguments.  I fixed this, and when I went to check doc/ I
noticed it was missing the '-fpic'/'-fno-pic' options.
---
 gas/ChangeLog         | 7 +++++++
 gas/config/tc-riscv.c | 9 ++-------
 gas/doc/c-riscv.texi  | 8 ++++++++
 3 files changed, 17 insertions(+), 7 deletions(-)

diff --git a/gas/ChangeLog b/gas/ChangeLog
index cf51667..ae42a80 100644
--- a/gas/ChangeLog
+++ b/gas/ChangeLog
@@ -1,3 +1,10 @@
+2017-03-21  Palmer Dabbbelt  <palmer@dabbelt.com>
+
+	* config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
+	-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
+	print an invalid default ISA string.
+	* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
+
 2017-03-16  Rinat Zelig  <rinat@mellanox.com>
 
 	* config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
index ff6d737..68b28f7 100644
--- a/gas/config/tc-riscv.c
+++ b/gas/config/tc-riscv.c
@@ -2475,15 +2475,10 @@ md_show_usage (FILE *stream)
 {
   fprintf (stream, _("\
 RISC-V options:\n\
-  -m32           assemble RV32 code\n\
-  -m64           assemble RV64 code (default)\n\
   -fpic          generate position-independent code\n\
   -fno-pic       don't generate position-independent code (default)\n\
-  -msoft-float   don't use F registers for floating-point values\n\
-  -mhard-float   use F registers for floating-point values (default)\n\
-  -mno-rvc       disable the C extension for compressed instructions (default)\n\
-  -mrvc          enable the C extension for compressed instructions\n\
-  -march=ISA     set the RISC-V architecture, RV64IMAFD by default\n\
+  -march=ISA     set the RISC-V architecture\n\
+  -mabi=ABI      set the RISC-V ABI\n\
 "));
 }
 
diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
index 8915db4..01b9931 100644
--- a/gas/doc/c-riscv.texi
+++ b/gas/doc/c-riscv.texi
@@ -26,6 +26,14 @@ The following table lists all available RISC-V specific options
 @c man begin OPTIONS
 @table @gcctabopt
 
+@cindex @samp{-fpic} option, RISC-V
+@item -fpic
+Generate position-independent code
+
+@cindex @samp{-fno-pic} option, RISC-V
+@item -fno-pic
+Don't generate position-independent code (default)
+
 @cindex @samp{-march=ISA} option, RISC-V
 @item -march=ISA
 Select the base isa, as specified by ISA.  For example -march=rv32ima.
-- 
2.10.2

Re: [PATCH] Sanitize RISC-V GAS help text, documentation

[David Malcolm]

On Tue, 2017-03-21 at 08:38 -0700, Palmer Dabbelt wrote:
> It looks like I missed the GAS help text when going through all the
> documentation last time, so it printed some of the old-format (never
> upstream) arguments.  I fixed this, and when I went to check doc/ I
> noticed it was missing the '-fpic'/'-fno-pic' options.
> ---
>  gas/ChangeLog         | 7 +++++++
>  gas/config/tc-riscv.c | 9 ++-------
>  gas/doc/c-riscv.texi  | 8 ++++++++
>  3 files changed, 17 insertions(+), 7 deletions(-)
> 
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index cf51667..ae42a80 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,3 +1,10 @@
> +2017-03-21  Palmer Dabbbelt  <palmer@dabbelt.com>
> +
> +	* config/tc-riscv.c (md_show_usage): Remode defuct -m32, 
> -m64,

FWIW, s/Remode defuct/Remove defunct/ presumably

Re: [PATCH] Sanitize RISC-V GAS help text, documentation

[Palmer Dabbelt]

On Tue, 21 Mar 2017 08:38:54 PDT (-0700), Palmer Dabbelt wrote:
> It looks like I missed the GAS help text when going through all the
> documentation last time, so it printed some of the old-format (never
> upstream) arguments.  I fixed this, and when I went to check doc/ I
> noticed it was missing the '-fpic'/'-fno-pic' options.
> ---
>  gas/ChangeLog         | 7 +++++++
>  gas/config/tc-riscv.c | 9 ++-------
>  gas/doc/c-riscv.texi  | 8 ++++++++
>  3 files changed, 17 insertions(+), 7 deletions(-)
>
> diff --git a/gas/ChangeLog b/gas/ChangeLog
> index cf51667..ae42a80 100644
> --- a/gas/ChangeLog
> +++ b/gas/ChangeLog
> @@ -1,3 +1,10 @@
> +2017-03-21  Palmer Dabbbelt  <palmer@dabbelt.com>
> +
> +	* config/tc-riscv.c (md_show_usage): Remode defuct -m32, -m64,
> +	-msoft-float, -mhard-float, -mno-rvc, and -mrvc options; and don't
> +	print an invalid default ISA string.
> +	* doc/c-riscv.texi (OPTIONS): Add -fpic and -fno-pic options.
> +
>  2017-03-16  Rinat Zelig  <rinat@mellanox.com>
>
>  	* config/tc-arc.c (assemble_insn): Only handle ".t" and ".nt"
> diff --git a/gas/config/tc-riscv.c b/gas/config/tc-riscv.c
> index ff6d737..68b28f7 100644
> --- a/gas/config/tc-riscv.c
> +++ b/gas/config/tc-riscv.c
> @@ -2475,15 +2475,10 @@ md_show_usage (FILE *stream)
>  {
>    fprintf (stream, _("\
>  RISC-V options:\n\
> -  -m32           assemble RV32 code\n\
> -  -m64           assemble RV64 code (default)\n\
>    -fpic          generate position-independent code\n\
>    -fno-pic       don't generate position-independent code (default)\n\
> -  -msoft-float   don't use F registers for floating-point values\n\
> -  -mhard-float   use F registers for floating-point values (default)\n\
> -  -mno-rvc       disable the C extension for compressed instructions (default)\n\
> -  -mrvc          enable the C extension for compressed instructions\n\
> -  -march=ISA     set the RISC-V architecture, RV64IMAFD by default\n\
> +  -march=ISA     set the RISC-V architecture\n\
> +  -mabi=ABI      set the RISC-V ABI\n\
>  "));
>  }
>
> diff --git a/gas/doc/c-riscv.texi b/gas/doc/c-riscv.texi
> index 8915db4..01b9931 100644
> --- a/gas/doc/c-riscv.texi
> +++ b/gas/doc/c-riscv.texi
> @@ -26,6 +26,14 @@ The following table lists all available RISC-V specific options
>  @c man begin OPTIONS
>  @table @gcctabopt
>
> +@cindex @samp{-fpic} option, RISC-V
> +@item -fpic
> +Generate position-independent code
> +
> +@cindex @samp{-fno-pic} option, RISC-V
> +@item -fno-pic
> +Don't generate position-independent code (default)
> +
>  @cindex @samp{-march=ISA} option, RISC-V
>  @item -march=ISA
>  Select the base isa, as specified by ISA.  For example -march=rv32ima.

Committed.