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* src/cgen ChangeLog sid-cpu.scm sid-decode.scm ...
@ 2001-04-02 14:18 bje
0 siblings, 0 replies; 3+ messages in thread
From: bje @ 2001-04-02 14:18 UTC (permalink / raw)
To: cgen-cvs
CVSROOT: /cvs/src
Module name: src
Changes by: bje@sources.redhat.com 2001-04-02 14:18:27
Modified files:
cgen : ChangeLog sid-cpu.scm sid-decode.scm sid.scm
Log message:
2001-04-02 Ben Elliston <bje@redhat.com>
* sid-cpu.scm (-last-insn): New function.
(-gen-sem-switch-engine): Loop through idesc while less than or
equal to the last instruction enum, not less than the MAX enum.
(-gen-sfrag-engine-fn): Clean up frag_label_table initialisation.
* sid-decode.scm (-gen-decode-insn-globals): Define the idesc
table's size to be the last instruction enum plus one, not
@PREFIX@_INSN_MAX.
* sid.scm (gen-cpu-insn-enum-decl): Do not append a dummy `max'
instruction onto the instruction list.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/ChangeLog.diff?cvsroot=src&r1=1.59&r2=1.60
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid-cpu.scm.diff?cvsroot=src&r1=1.2&r2=1.3
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid-decode.scm.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid.scm.diff?cvsroot=src&r1=1.3&r2=1.4
^ permalink raw reply [flat|nested] 3+ messages in thread
* src/cgen ChangeLog sid-cpu.scm sid-decode.scm ...
@ 2003-06-10 18:26 brolley
0 siblings, 0 replies; 3+ messages in thread
From: brolley @ 2003-06-10 18:26 UTC (permalink / raw)
To: cgen-cvs
CVSROOT: /cvs/src
Module name: src
Changes by: brolley@sourceware.org 2003-06-10 18:26:03
Modified files:
cgen : ChangeLog sid-cpu.scm sid-decode.scm
sid-model.scm
Log message:
2003-06-10 Dave Brolley <brolley@redhat.com>
* sid-cpu.scm: Generate #include of config.h into @prefix@-sem.cxx.
* sid-decode.scm: Generate #include of config.h into
@prefix@-decode.cxx.
* sid-model.scm: Generate #include of config.h into @prefix@-model.cxx.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/ChangeLog.diff?cvsroot=src&r1=1.153&r2=1.154
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid-cpu.scm.diff?cvsroot=src&r1=1.9&r2=1.10
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid-decode.scm.diff?cvsroot=src&r1=1.10&r2=1.11
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid-model.scm.diff?cvsroot=src&r1=1.5&r2=1.6
^ permalink raw reply [flat|nested] 3+ messages in thread
* src/cgen ChangeLog sid-cpu.scm sid-decode.scm ...
@ 2001-07-11 19:54 fche
0 siblings, 0 replies; 3+ messages in thread
From: fche @ 2001-07-11 19:54 UTC (permalink / raw)
To: cgen-cvs
CVSROOT: /cvs/src
Module name: src
Changes by: fche@sources.redhat.com 2001-07-11 19:54:40
Modified files:
cgen : ChangeLog sid-cpu.scm sid-decode.scm
utils-sim.scm
Log message:
* more 16/32-bit insn set support; simulator (sid)
2001-07-11 Frank Ch. Eigler <fche@redhat.com>
* sid-cpu.scm (-gen-mach-params): New proc to emit ...CHUNK_BITSIZE...
(cgen-desc.h): Call it.
* sid-decode.scm (-gen-decode-fn): Use base-insn-bitsize as
decode-size.
* utils-sim.scm (-gen-decode-insn-entry): For SID only, prepare
entire_insn for extraction, if it's shorter than base-insn-bitsize.
Patches:
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/ChangeLog.diff?cvsroot=src&r1=1.74&r2=1.75
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid-cpu.scm.diff?cvsroot=src&r1=1.3&r2=1.4
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/sid-decode.scm.diff?cvsroot=src&r1=1.4&r2=1.5
http://sources.redhat.com/cgi-bin/cvsweb.cgi/src/cgen/utils-sim.scm.diff?cvsroot=src&r1=1.5&r2=1.6
^ permalink raw reply [flat|nested] 3+ messages in thread
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