* Exact sequences for running cgen
@ 2003-06-13 17:46 Michael Meissner
2003-06-13 18:16 ` Doug Evans
0 siblings, 1 reply; 3+ messages in thread
From: Michael Meissner @ 2003-06-13 17:46 UTC (permalink / raw)
To: cgen
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Ok, I must be doing something wrong. Could somebody give me an exact
walk-through of how to set up the cgen environment. I have tried using the cvs
sources, and the snapshot. I have tried building cgen in place, as well as my
usual preference of building it in a separate build directory. The last time I
asked this question, I was told just run the make in place, but neither the
snapshot nor the cvs sources have a Makefile. I have tried using a Red Hat 8.0
system, as well as Red Hat 9 (using a 1.4.3 guile compiled since
Here is one attempt:
$ tar -xvjf snapshot-20030607.tar.bz2
$ cd cgen/cgen
$ ./configure --target=m32r-unknown-elf
$ make desc
At this point it runs, but if you look at the tmp-desc.h and tmp-desc.c files,
you see that it has not substituted M32R for @ARCH@ and m32r for @arch@ as I
would expect. See the attachments for the tmp-desc.h and tmp-desc.c files.
--
Michael Meissner
email: gnu@the-meissners.org
http://www.the-meissners.org
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/* CPU data header for @arch@.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#ifndef @ARCH@_CPU_H
#define @ARCH@_CPU_H
#define CGEN_ARCH @arch@
/* Given symbol S, return @arch@_cgen_<S>. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define CGEN_SYM(s) @arch@##_cgen_##s
#else
#define CGEN_SYM(s) @arch@/**/_cgen_/**/s
#endif
/* Selected cpu families. */
#define HAVE_CPU_M32RBF
#define HAVE_CPU_M32RXF
#define CGEN_INSN_LSB0_P 0
/* Minimum size of any insn (in bytes). */
#define CGEN_MIN_INSN_SIZE 2
/* Maximum size of any insn (in bytes). */
#define CGEN_MAX_INSN_SIZE 4
#define CGEN_INT_INSN_P 1
/* Maximum number of syntax elements in an instruction. */
#define CGEN_ACTUAL_MAX_SYNTAX_ELEMENTS 15
/* CGEN_MNEMONIC_OPERANDS is defined if mnemonics have operands.
e.g. In "b,a foo" the ",a" is an operand. If mnemonics have operands
we can't hash on everything up to the space. */
#define CGEN_MNEMONIC_OPERANDS
/* Maximum number of fields in an instruction. */
#define CGEN_ACTUAL_MAX_IFMT_OPERANDS 7
/* Enums. */
/* Enum declaration for insn format enums. */
typedef enum insn_op1 {
OP1_0, OP1_1, OP1_2, OP1_3
, OP1_4, OP1_5, OP1_6, OP1_7
, OP1_8, OP1_9, OP1_10, OP1_11
, OP1_12, OP1_13, OP1_14, OP1_15
} INSN_OP1;
/* Enum declaration for op2 enums. */
typedef enum insn_op2 {
OP2_0, OP2_1, OP2_2, OP2_3
, OP2_4, OP2_5, OP2_6, OP2_7
, OP2_8, OP2_9, OP2_10, OP2_11
, OP2_12, OP2_13, OP2_14, OP2_15
} INSN_OP2;
/* Enum declaration for . */
typedef enum gr_names {
H_GR_FP = 13, H_GR_LR = 14, H_GR_SP = 15, H_GR_R0 = 0
, H_GR_R1 = 1, H_GR_R2 = 2, H_GR_R3 = 3, H_GR_R4 = 4
, H_GR_R5 = 5, H_GR_R6 = 6, H_GR_R7 = 7, H_GR_R8 = 8
, H_GR_R9 = 9, H_GR_R10 = 10, H_GR_R11 = 11, H_GR_R12 = 12
, H_GR_R13 = 13, H_GR_R14 = 14, H_GR_R15 = 15
} GR_NAMES;
/* Enum declaration for . */
typedef enum cr_names {
H_CR_PSW = 0, H_CR_CBR = 1, H_CR_SPI = 2, H_CR_SPU = 3
, H_CR_BPC = 6, H_CR_BBPSW = 8, H_CR_BBPC = 14, H_CR_CR0 = 0
, H_CR_CR1 = 1, H_CR_CR2 = 2, H_CR_CR3 = 3, H_CR_CR4 = 4
, H_CR_CR5 = 5, H_CR_CR6 = 6, H_CR_CR7 = 7, H_CR_CR8 = 8
, H_CR_CR9 = 9, H_CR_CR10 = 10, H_CR_CR11 = 11, H_CR_CR12 = 12
, H_CR_CR13 = 13, H_CR_CR14 = 14, H_CR_CR15 = 15
} CR_NAMES;
/* Attributes. */
/* Enum declaration for machine type selection. */
typedef enum mach_attr {
MACH_BASE, MACH_M32R, MACH_M32RX, MACH_MAX
} MACH_ATTR;
/* Enum declaration for instruction set selection. */
typedef enum isa_attr {
ISA_M32R, ISA_MAX
} ISA_ATTR;
/* Enum declaration for parallel execution pipeline selection. */
typedef enum pipe_attr {
PIPE_NONE, PIPE_O, PIPE_S, PIPE_OS
} PIPE_ATTR;
/* Number of architecture variants. */
#define MAX_ISAS 1
#define MAX_MACHS ((int) MACH_MAX)
/* Ifield support. */
extern const struct cgen_ifld @arch@_cgen_ifld_table[];
/* Ifield attribute indices. */
/* Enum declaration for cgen_ifld attrs. */
typedef enum cgen_ifld_attr {
CGEN_IFLD_VIRTUAL, CGEN_IFLD_PCREL_ADDR, CGEN_IFLD_ABS_ADDR, CGEN_IFLD_RESERVED
, CGEN_IFLD_SIGN_OPT, CGEN_IFLD_SIGNED, CGEN_IFLD_RELOC, CGEN_IFLD_END_BOOLS
, CGEN_IFLD_START_NBOOLS = 31, CGEN_IFLD_MACH, CGEN_IFLD_END_NBOOLS
} CGEN_IFLD_ATTR;
/* Number of non-boolean elements in cgen_ifld_attr. */
#define CGEN_IFLD_NBOOL_ATTRS (CGEN_IFLD_END_NBOOLS - CGEN_IFLD_START_NBOOLS - 1)
/* Enum declaration for @arch@ ifield types. */
typedef enum ifield_type {
@ARCH@_F_NIL, @ARCH@_F_ANYOF, @ARCH@_F_OP1, @ARCH@_F_OP2
, @ARCH@_F_COND, @ARCH@_F_R1, @ARCH@_F_R2, @ARCH@_F_SIMM8
, @ARCH@_F_SIMM16, @ARCH@_F_SHIFT_OP2, @ARCH@_F_UIMM4, @ARCH@_F_UIMM5
, @ARCH@_F_UIMM16, @ARCH@_F_UIMM24, @ARCH@_F_HI16, @ARCH@_F_DISP8
, @ARCH@_F_DISP16, @ARCH@_F_DISP24, @ARCH@_F_OP23, @ARCH@_F_OP3
, @ARCH@_F_ACC, @ARCH@_F_ACCS, @ARCH@_F_ACCD, @ARCH@_F_BITS67
, @ARCH@_F_BIT14, @ARCH@_F_IMM1, @ARCH@_F_MAX
} IFIELD_TYPE;
#define MAX_IFLD ((int) @ARCH@_F_MAX)
/* Hardware attribute indices. */
/* Enum declaration for cgen_hw attrs. */
typedef enum cgen_hw_attr {
CGEN_HW_VIRTUAL, CGEN_HW_CACHE_ADDR, CGEN_HW_PC, CGEN_HW_PROFILE
, CGEN_HW_END_BOOLS, CGEN_HW_START_NBOOLS = 31, CGEN_HW_MACH, CGEN_HW_END_NBOOLS
} CGEN_HW_ATTR;
/* Number of non-boolean elements in cgen_hw_attr. */
#define CGEN_HW_NBOOL_ATTRS (CGEN_HW_END_NBOOLS - CGEN_HW_START_NBOOLS - 1)
/* Enum declaration for @arch@ hardware types. */
typedef enum cgen_hw_type {
HW_H_MEMORY, HW_H_SINT, HW_H_UINT, HW_H_ADDR
, HW_H_IADDR, HW_H_PC, HW_H_HI16, HW_H_SLO16
, HW_H_ULO16, HW_H_GR, HW_H_CR, HW_H_ACCUM
, HW_H_ACCUMS, HW_H_COND, HW_H_PSW, HW_H_BPSW
, HW_H_BBPSW, HW_H_LOCK, HW_MAX
} CGEN_HW_TYPE;
#define MAX_HW ((int) HW_MAX)
/* Operand attribute indices. */
/* Enum declaration for cgen_operand attrs. */
typedef enum cgen_operand_attr {
CGEN_OPERAND_VIRTUAL, CGEN_OPERAND_PCREL_ADDR, CGEN_OPERAND_ABS_ADDR, CGEN_OPERAND_SIGN_OPT
, CGEN_OPERAND_SIGNED, CGEN_OPERAND_NEGATIVE, CGEN_OPERAND_RELAX, CGEN_OPERAND_SEM_ONLY
, CGEN_OPERAND_RELOC, CGEN_OPERAND_HASH_PREFIX, CGEN_OPERAND_END_BOOLS, CGEN_OPERAND_START_NBOOLS = 31
, CGEN_OPERAND_MACH, CGEN_OPERAND_END_NBOOLS
} CGEN_OPERAND_ATTR;
/* Number of non-boolean elements in cgen_operand_attr. */
#define CGEN_OPERAND_NBOOL_ATTRS (CGEN_OPERAND_END_NBOOLS - CGEN_OPERAND_START_NBOOLS - 1)
/* Enum declaration for @arch@ operand types. */
typedef enum cgen_operand_type {
@ARCH@_OPERAND_PC, @ARCH@_OPERAND_SR, @ARCH@_OPERAND_DR, @ARCH@_OPERAND_SRC1
, @ARCH@_OPERAND_SRC2, @ARCH@_OPERAND_SCR, @ARCH@_OPERAND_DCR, @ARCH@_OPERAND_SIMM8
, @ARCH@_OPERAND_SIMM16, @ARCH@_OPERAND_UIMM4, @ARCH@_OPERAND_UIMM5, @ARCH@_OPERAND_UIMM16
, @ARCH@_OPERAND_IMM1, @ARCH@_OPERAND_ACCD, @ARCH@_OPERAND_ACCS, @ARCH@_OPERAND_ACC
, @ARCH@_OPERAND_HASH, @ARCH@_OPERAND_HI16, @ARCH@_OPERAND_SLO16, @ARCH@_OPERAND_ULO16
, @ARCH@_OPERAND_UIMM24, @ARCH@_OPERAND_DISP8, @ARCH@_OPERAND_DISP16, @ARCH@_OPERAND_DISP24
, @ARCH@_OPERAND_CONDBIT, @ARCH@_OPERAND_ACCUM, @ARCH@_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
#define MAX_OPERANDS 26
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
/* Insn attribute indices. */
/* Enum declaration for cgen_insn attrs. */
typedef enum cgen_insn_attr {
CGEN_INSN_ALIAS, CGEN_INSN_VIRTUAL, CGEN_INSN_UNCOND_CTI, CGEN_INSN_COND_CTI
, CGEN_INSN_SKIP_CTI, CGEN_INSN_DELAY_SLOT, CGEN_INSN_RELAXABLE, CGEN_INSN_RELAX
, CGEN_INSN_NO_DIS, CGEN_INSN_PBB, CGEN_INSN_FILL_SLOT, CGEN_INSN_SPECIAL
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_PIPE
, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
#define CGEN_INSN_NBOOL_ATTRS (CGEN_INSN_END_NBOOLS - CGEN_INSN_START_NBOOLS - 1)
/* cgen.h uses things we just defined. */
#include "opcode/cgen.h"
/* Attributes. */
extern const CGEN_ATTR_TABLE @arch@_cgen_hardware_attr_table[];
extern const CGEN_ATTR_TABLE @arch@_cgen_ifield_attr_table[];
extern const CGEN_ATTR_TABLE @arch@_cgen_operand_attr_table[];
extern const CGEN_ATTR_TABLE @arch@_cgen_insn_attr_table[];
/* Hardware decls. */
extern CGEN_KEYWORD @arch@_cgen_opval_gr_names;
extern CGEN_KEYWORD @arch@_cgen_opval_cr_names;
extern CGEN_KEYWORD @arch@_cgen_opval_h_accums;
#endif /* @ARCH@_CPU_H */
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/* CPU data for @arch@.
THIS FILE IS MACHINE GENERATED WITH CGEN.
Copyright 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003 Free Software Foundation, Inc.
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
This program is free software; you can redistribute it and/or modify
it under the terms of the GNU General Public License as published by
the Free Software Foundation; either version 2, or (at your option)
any later version.
This program is distributed in the hope that it will be useful,
but WITHOUT ANY WARRANTY; without even the implied warranty of
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
GNU General Public License for more details.
You should have received a copy of the GNU General Public License along
with this program; if not, write to the Free Software Foundation, Inc.,
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
*/
#include "sysdep.h"
#include <stdio.h>
#include <stdarg.h>
#include "ansidecl.h"
#include "bfd.h"
#include "symcat.h"
#include "@arch@-desc.h"
#include "@arch@-opc.h"
#include "opintl.h"
#include "libiberty.h"
#include "xregex.h"
/* Attributes. */
static const CGEN_ATTR_ENTRY bool_attr[] =
{
{ "#f", 0 },
{ "#t", 1 },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY MACH_attr[] =
{
{ "base", MACH_BASE },
{ "m32r", MACH_M32R },
{ "m32rx", MACH_M32RX },
{ "max", MACH_MAX },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY ISA_attr[] =
{
{ "m32r", ISA_M32R },
{ "max", ISA_MAX },
{ 0, 0 }
};
static const CGEN_ATTR_ENTRY PIPE_attr[] =
{
{ "NONE", PIPE_NONE },
{ "O", PIPE_O },
{ "S", PIPE_S },
{ "OS", PIPE_OS },
{ 0, 0 }
};
const CGEN_ATTR_TABLE @arch@_cgen_ifield_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "RESERVED", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
{ "SIGNED", &bool_attr[0], &bool_attr[0] },
{ "RELOC", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE @arch@_cgen_hardware_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
{ "PC", &bool_attr[0], &bool_attr[0] },
{ "PROFILE", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE @arch@_cgen_operand_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
{ "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
{ "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
{ "SIGNED", &bool_attr[0], &bool_attr[0] },
{ "NEGATIVE", &bool_attr[0], &bool_attr[0] },
{ "RELAX", &bool_attr[0], &bool_attr[0] },
{ "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
{ "RELOC", &bool_attr[0], &bool_attr[0] },
{ "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
const CGEN_ATTR_TABLE @arch@_cgen_insn_attr_table[] =
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
{ "ALIAS", &bool_attr[0], &bool_attr[0] },
{ "VIRTUAL", &bool_attr[0], &bool_attr[0] },
{ "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
{ "COND-CTI", &bool_attr[0], &bool_attr[0] },
{ "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
{ "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
{ "RELAXABLE", &bool_attr[0], &bool_attr[0] },
{ "RELAX", &bool_attr[0], &bool_attr[0] },
{ "NO-DIS", &bool_attr[0], &bool_attr[0] },
{ "PBB", &bool_attr[0], &bool_attr[0] },
{ "FILL-SLOT", &bool_attr[0], &bool_attr[0] },
{ "SPECIAL", &bool_attr[0], &bool_attr[0] },
{ 0, 0, 0 }
};
/* Instruction set variants. */
static const CGEN_ISA @arch@_cgen_isa_table[] = {
{ "m32r", 32, 32, 16, 32 },
{ 0, 0, 0, 0, 0 }
};
/* Machine variants. */
static const CGEN_MACH @arch@_cgen_mach_table[] = {
{ "m32r", "m32r", MACH_M32R, 0 },
{ "m32rx", "m32rx", MACH_M32RX, 0 },
{ 0, 0, 0, 0 }
};
static CGEN_KEYWORD_ENTRY @arch@_cgen_opval_gr_names_entries[] =
{
{ "fp", 13, {0, {0}}, 0, 0 },
{ "lr", 14, {0, {0}}, 0, 0 },
{ "sp", 15, {0, {0}}, 0, 0 },
{ "r0", 0, {0, {0}}, 0, 0 },
{ "r1", 1, {0, {0}}, 0, 0 },
{ "r2", 2, {0, {0}}, 0, 0 },
{ "r3", 3, {0, {0}}, 0, 0 },
{ "r4", 4, {0, {0}}, 0, 0 },
{ "r5", 5, {0, {0}}, 0, 0 },
{ "r6", 6, {0, {0}}, 0, 0 },
{ "r7", 7, {0, {0}}, 0, 0 },
{ "r8", 8, {0, {0}}, 0, 0 },
{ "r9", 9, {0, {0}}, 0, 0 },
{ "r10", 10, {0, {0}}, 0, 0 },
{ "r11", 11, {0, {0}}, 0, 0 },
{ "r12", 12, {0, {0}}, 0, 0 },
{ "r13", 13, {0, {0}}, 0, 0 },
{ "r14", 14, {0, {0}}, 0, 0 },
{ "r15", 15, {0, {0}}, 0, 0 }
};
CGEN_KEYWORD @arch@_cgen_opval_gr_names =
{
& @arch@_cgen_opval_gr_names_entries[0],
19,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY @arch@_cgen_opval_cr_names_entries[] =
{
{ "psw", 0, {0, {0}}, 0, 0 },
{ "cbr", 1, {0, {0}}, 0, 0 },
{ "spi", 2, {0, {0}}, 0, 0 },
{ "spu", 3, {0, {0}}, 0, 0 },
{ "bpc", 6, {0, {0}}, 0, 0 },
{ "bbpsw", 8, {0, {0}}, 0, 0 },
{ "bbpc", 14, {0, {0}}, 0, 0 },
{ "cr0", 0, {0, {0}}, 0, 0 },
{ "cr1", 1, {0, {0}}, 0, 0 },
{ "cr2", 2, {0, {0}}, 0, 0 },
{ "cr3", 3, {0, {0}}, 0, 0 },
{ "cr4", 4, {0, {0}}, 0, 0 },
{ "cr5", 5, {0, {0}}, 0, 0 },
{ "cr6", 6, {0, {0}}, 0, 0 },
{ "cr7", 7, {0, {0}}, 0, 0 },
{ "cr8", 8, {0, {0}}, 0, 0 },
{ "cr9", 9, {0, {0}}, 0, 0 },
{ "cr10", 10, {0, {0}}, 0, 0 },
{ "cr11", 11, {0, {0}}, 0, 0 },
{ "cr12", 12, {0, {0}}, 0, 0 },
{ "cr13", 13, {0, {0}}, 0, 0 },
{ "cr14", 14, {0, {0}}, 0, 0 },
{ "cr15", 15, {0, {0}}, 0, 0 }
};
CGEN_KEYWORD @arch@_cgen_opval_cr_names =
{
& @arch@_cgen_opval_cr_names_entries[0],
23,
0, 0, 0, 0, ""
};
static CGEN_KEYWORD_ENTRY @arch@_cgen_opval_h_accums_entries[] =
{
{ "a0", 0, {0, {0}}, 0, 0 },
{ "a1", 1, {0, {0}}, 0, 0 }
};
CGEN_KEYWORD @arch@_cgen_opval_h_accums =
{
& @arch@_cgen_opval_h_accums_entries[0],
2,
0, 0, 0, 0, ""
};
/* The hardware table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_HW_##a)
#else
#define A(a) (1 << CGEN_HW_/**/a)
#endif
const CGEN_HW_ENTRY @arch@_cgen_hw_table[] =
{
{ "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
{ "h-hi16", HW_H_HI16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-slo16", HW_H_SLO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-ulo16", HW_H_ULO16, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & @arch@_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
{ "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & @arch@_cgen_opval_cr_names, { 0, { (1<<MACH_BASE) } } },
{ "h-accum", HW_H_ACCUM, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-accums", HW_H_ACCUMS, CGEN_ASM_KEYWORD, (PTR) & @arch@_cgen_opval_h_accums, { 0, { (1<<MACH_M32RX) } } },
{ "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-psw", HW_H_PSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-bpsw", HW_H_BPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-bbpsw", HW_H_BBPSW, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ "h-lock", HW_H_LOCK, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
{ 0, 0, CGEN_ASM_NONE, 0, {0, {0}} }
};
#undef A
/* The instruction field table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_IFLD_##a)
#else
#define A(a) (1 << CGEN_IFLD_/**/a)
#endif
const CGEN_IFLD @arch@_cgen_ifld_table[] =
{
{ @ARCH@_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_OP1, "f-op1", 0, 32, 0, 4, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_OP2, "f-op2", 0, 32, 8, 4, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_COND, "f-cond", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_R1, "f-r1", 0, 32, 4, 4, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_R2, "f-r2", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_SIMM8, "f-simm8", 0, 32, 8, 8, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_SIMM16, "f-simm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_SHIFT_OP2, "f-shift-op2", 0, 32, 8, 3, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_UIMM4, "f-uimm4", 0, 32, 12, 4, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_UIMM5, "f-uimm5", 0, 32, 11, 5, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_UIMM16, "f-uimm16", 0, 32, 16, 16, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_UIMM24, "f-uimm24", 0, 32, 8, 24, { 0|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
{ @ARCH@_F_HI16, "f-hi16", 0, 32, 16, 16, { 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
{ @ARCH@_F_DISP8, "f-disp8", 0, 32, 8, 8, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ @ARCH@_F_DISP16, "f-disp16", 0, 32, 16, 16, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ @ARCH@_F_DISP24, "f-disp24", 0, 32, 8, 24, { 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
{ @ARCH@_F_OP23, "f-op23", 0, 32, 9, 3, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_OP3, "f-op3", 0, 32, 14, 2, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_ACC, "f-acc", 0, 32, 8, 1, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_ACCS, "f-accs", 0, 32, 12, 2, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_ACCD, "f-accd", 0, 32, 4, 2, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_BITS67, "f-bits67", 0, 32, 6, 2, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_BIT14, "f-bit14", 0, 32, 14, 1, { 0, { (1<<MACH_BASE) } } },
{ @ARCH@_F_IMM1, "f-imm1", 0, 32, 15, 1, { 0, { (1<<MACH_BASE) } } },
{ 0, 0, 0, 0, 0, 0, {0, {0}} }
};
#undef A
/* multi ifield declarations */
/* multi ifield definitions */
/* The operand table. */
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_OPERAND_##a)
#else
#define A(a) (1 << CGEN_OPERAND_/**/a)
#endif
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define OPERAND(op) @ARCH@_OPERAND_##op
#else
#define OPERAND(op) @ARCH@_OPERAND_/**/op
#endif
const CGEN_OPERAND @arch@_cgen_operand_table[] =
{
/* pc: program counter */
{ "pc", @ARCH@_OPERAND_PC, HW_H_PC, 0, 0,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_NIL] } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sr: source register */
{ "sr", @ARCH@_OPERAND_SR, HW_H_GR, 12, 4,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_R2] } },
{ 0, { (1<<MACH_BASE) } } },
/* dr: destination register */
{ "dr", @ARCH@_OPERAND_DR, HW_H_GR, 4, 4,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_R1] } },
{ 0, { (1<<MACH_BASE) } } },
/* src1: source register 1 */
{ "src1", @ARCH@_OPERAND_SRC1, HW_H_GR, 4, 4,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_R1] } },
{ 0, { (1<<MACH_BASE) } } },
/* src2: source register 2 */
{ "src2", @ARCH@_OPERAND_SRC2, HW_H_GR, 12, 4,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_R2] } },
{ 0, { (1<<MACH_BASE) } } },
/* scr: source control register */
{ "scr", @ARCH@_OPERAND_SCR, HW_H_CR, 12, 4,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_R2] } },
{ 0, { (1<<MACH_BASE) } } },
/* dcr: destination control register */
{ "dcr", @ARCH@_OPERAND_DCR, HW_H_CR, 4, 4,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_R1] } },
{ 0, { (1<<MACH_BASE) } } },
/* simm8: 8 bit signed immediate */
{ "simm8", @ARCH@_OPERAND_SIMM8, HW_H_SINT, 8, 8,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_SIMM8] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* simm16: 16 bit signed immediate */
{ "simm16", @ARCH@_OPERAND_SIMM16, HW_H_SINT, 16, 16,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_SIMM16] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm4: 4 bit trap number */
{ "uimm4", @ARCH@_OPERAND_UIMM4, HW_H_UINT, 12, 4,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_UIMM4] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm5: 5 bit shift count */
{ "uimm5", @ARCH@_OPERAND_UIMM5, HW_H_UINT, 11, 5,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_UIMM5] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* uimm16: 16 bit unsigned immediate */
{ "uimm16", @ARCH@_OPERAND_UIMM16, HW_H_UINT, 16, 16,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_UIMM16] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_BASE) } } },
/* imm1: 1 bit immediate */
{ "imm1", @ARCH@_OPERAND_IMM1, HW_H_UINT, 15, 1,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_IMM1] } },
{ 0|A(HASH_PREFIX), { (1<<MACH_M32RX) } } },
/* accd: accumulator destination register */
{ "accd", @ARCH@_OPERAND_ACCD, HW_H_ACCUMS, 4, 2,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_ACCD] } },
{ 0, { (1<<MACH_M32RX) } } },
/* accs: accumulator source register */
{ "accs", @ARCH@_OPERAND_ACCS, HW_H_ACCUMS, 12, 2,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_ACCS] } },
{ 0, { (1<<MACH_M32RX) } } },
/* acc: accumulator reg (d) */
{ "acc", @ARCH@_OPERAND_ACC, HW_H_ACCUMS, 8, 1,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_ACC] } },
{ 0, { (1<<MACH_M32RX) } } },
/* hash: # prefix */
{ "hash", @ARCH@_OPERAND_HASH, HW_H_SINT, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { (1<<MACH_BASE) } } },
/* hi16: high 16 bit immediate, sign optional */
{ "hi16", @ARCH@_OPERAND_HI16, HW_H_HI16, 16, 16,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_HI16] } },
{ 0|A(SIGN_OPT), { (1<<MACH_BASE) } } },
/* slo16: 16 bit signed immediate, for low() */
{ "slo16", @ARCH@_OPERAND_SLO16, HW_H_SLO16, 16, 16,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_SIMM16] } },
{ 0, { (1<<MACH_BASE) } } },
/* ulo16: 16 bit unsigned immediate, for low() */
{ "ulo16", @ARCH@_OPERAND_ULO16, HW_H_ULO16, 16, 16,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_UIMM16] } },
{ 0, { (1<<MACH_BASE) } } },
/* uimm24: 24 bit address */
{ "uimm24", @ARCH@_OPERAND_UIMM24, HW_H_ADDR, 8, 24,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_UIMM24] } },
{ 0|A(HASH_PREFIX)|A(RELOC)|A(ABS_ADDR), { (1<<MACH_BASE) } } },
/* disp8: 8 bit displacement */
{ "disp8", @ARCH@_OPERAND_DISP8, HW_H_IADDR, 8, 8,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_DISP8] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp16: 16 bit displacement */
{ "disp16", @ARCH@_OPERAND_DISP16, HW_H_IADDR, 16, 16,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_DISP16] } },
{ 0|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* disp24: 24 bit displacement */
{ "disp24", @ARCH@_OPERAND_DISP24, HW_H_IADDR, 8, 24,
{ 0, { (const PTR) &@arch@_cgen_ifld_table[@ARCH@_F_DISP24] } },
{ 0|A(RELAX)|A(RELOC)|A(PCREL_ADDR), { (1<<MACH_BASE) } } },
/* condbit: condition bit */
{ "condbit", @ARCH@_OPERAND_CONDBIT, HW_H_COND, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* accum: accumulator */
{ "accum", @ARCH@_OPERAND_ACCUM, HW_H_ACCUM, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0|A(SEM_ONLY), { (1<<MACH_BASE) } } },
/* sentinel */
{ 0, 0, 0, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { 0 } } }
};
#undef A
/* The instruction table. */
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
#define A(a) (1 << CGEN_INSN_##a)
#else
#define A(a) (1 << CGEN_INSN_/**/a)
#endif
static const CGEN_IBASE @arch@_cgen_insn_table[MAX_INSNS] =
{
/* Special null first entry.
A `num' value of zero is thus invalid.
Also, the special `invalid' insn resides here. */
{ 0, 0, 0, 0, {0, {0}} },
/* add $dr,$sr */
{
@ARCH@_INSN_ADD, "add", "add", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* add3 $dr,$sr,$hash$slo16 */
{
@ARCH@_INSN_ADD3, "add3", "add3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* and $dr,$sr */
{
@ARCH@_INSN_AND, "and", "and", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* and3 $dr,$sr,$uimm16 */
{
@ARCH@_INSN_AND3, "and3", "and3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* or $dr,$sr */
{
@ARCH@_INSN_OR, "or", "or", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* or3 $dr,$sr,$hash$ulo16 */
{
@ARCH@_INSN_OR3, "or3", "or3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* xor $dr,$sr */
{
@ARCH@_INSN_XOR, "xor", "xor", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* xor3 $dr,$sr,$uimm16 */
{
@ARCH@_INSN_XOR3, "xor3", "xor3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* addi $dr,$simm8 */
{
@ARCH@_INSN_ADDI, "addi", "addi", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* addv $dr,$sr */
{
@ARCH@_INSN_ADDV, "addv", "addv", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* addv3 $dr,$sr,$simm16 */
{
@ARCH@_INSN_ADDV3, "addv3", "addv3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* addx $dr,$sr */
{
@ARCH@_INSN_ADDX, "addx", "addx", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* bc.s $disp8 */
{
@ARCH@_INSN_BC8, "bc8", "bc.s", 16,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* bc.l $disp24 */
{
@ARCH@_INSN_BC24, "bc24", "bc.l", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* beq $src1,$src2,$disp16 */
{
@ARCH@_INSN_BEQ, "beq", "beq", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* beqz $src2,$disp16 */
{
@ARCH@_INSN_BEQZ, "beqz", "beqz", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bgez $src2,$disp16 */
{
@ARCH@_INSN_BGEZ, "bgez", "bgez", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bgtz $src2,$disp16 */
{
@ARCH@_INSN_BGTZ, "bgtz", "bgtz", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* blez $src2,$disp16 */
{
@ARCH@_INSN_BLEZ, "blez", "blez", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bltz $src2,$disp16 */
{
@ARCH@_INSN_BLTZ, "bltz", "bltz", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bnez $src2,$disp16 */
{
@ARCH@_INSN_BNEZ, "bnez", "bnez", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bl.s $disp8 */
{
@ARCH@_INSN_BL8, "bl8", "bl.s", 16,
{ 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* bl.l $disp24 */
{
@ARCH@_INSN_BL24, "bl24", "bl.l", 32,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bcl.s $disp8 */
{
@ARCH@_INSN_BCL8, "bcl8", "bcl.s", 16,
{ 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* bcl.l $disp24 */
{
@ARCH@_INSN_BCL24, "bcl24", "bcl.l", 32,
{ 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
/* bnc.s $disp8 */
{
@ARCH@_INSN_BNC8, "bnc8", "bnc.s", 16,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* bnc.l $disp24 */
{
@ARCH@_INSN_BNC24, "bnc24", "bnc.l", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bne $src1,$src2,$disp16 */
{
@ARCH@_INSN_BNE, "bne", "bne", 32,
{ 0|A(COND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bra.s $disp8 */
{
@ARCH@_INSN_BRA8, "bra8", "bra.s", 16,
{ 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* bra.l $disp24 */
{
@ARCH@_INSN_BRA24, "bra24", "bra.l", 32,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_NONE } }
},
/* bncl.s $disp8 */
{
@ARCH@_INSN_BNCL8, "bncl8", "bncl.s", 16,
{ 0|A(FILL_SLOT)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* bncl.l $disp24 */
{
@ARCH@_INSN_BNCL24, "bncl24", "bncl.l", 32,
{ 0|A(COND_CTI), { (1<<MACH_M32RX), PIPE_NONE } }
},
/* cmp $src1,$src2 */
{
@ARCH@_INSN_CMP, "cmp", "cmp", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* cmpi $src2,$simm16 */
{
@ARCH@_INSN_CMPI, "cmpi", "cmpi", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* cmpu $src1,$src2 */
{
@ARCH@_INSN_CMPU, "cmpu", "cmpu", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* cmpui $src2,$simm16 */
{
@ARCH@_INSN_CMPUI, "cmpui", "cmpui", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* cmpeq $src1,$src2 */
{
@ARCH@_INSN_CMPEQ, "cmpeq", "cmpeq", 16,
{ 0, { (1<<MACH_M32RX), PIPE_OS } }
},
/* cmpz $src2 */
{
@ARCH@_INSN_CMPZ, "cmpz", "cmpz", 16,
{ 0, { (1<<MACH_M32RX), PIPE_OS } }
},
/* div $dr,$sr */
{
@ARCH@_INSN_DIV, "div", "div", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* divu $dr,$sr */
{
@ARCH@_INSN_DIVU, "divu", "divu", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* rem $dr,$sr */
{
@ARCH@_INSN_REM, "rem", "rem", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* remu $dr,$sr */
{
@ARCH@_INSN_REMU, "remu", "remu", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* divh $dr,$sr */
{
@ARCH@_INSN_DIVH, "divh", "divh", 32,
{ 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
/* jc $sr */
{
@ARCH@_INSN_JC, "jc", "jc", 16,
{ 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* jnc $sr */
{
@ARCH@_INSN_JNC, "jnc", "jnc", 16,
{ 0|A(SPECIAL)|A(COND_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* jl $sr */
{
@ARCH@_INSN_JL, "jl", "jl", 16,
{ 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* jmp $sr */
{
@ARCH@_INSN_JMP, "jmp", "jmp", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* ld $dr,@$sr */
{
@ARCH@_INSN_LD, "ld", "ld", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* ld $dr,@($slo16,$sr) */
{
@ARCH@_INSN_LD_D, "ld-d", "ld", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* ldb $dr,@$sr */
{
@ARCH@_INSN_LDB, "ldb", "ldb", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* ldb $dr,@($slo16,$sr) */
{
@ARCH@_INSN_LDB_D, "ldb-d", "ldb", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* ldh $dr,@$sr */
{
@ARCH@_INSN_LDH, "ldh", "ldh", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* ldh $dr,@($slo16,$sr) */
{
@ARCH@_INSN_LDH_D, "ldh-d", "ldh", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* ldub $dr,@$sr */
{
@ARCH@_INSN_LDUB, "ldub", "ldub", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* ldub $dr,@($slo16,$sr) */
{
@ARCH@_INSN_LDUB_D, "ldub-d", "ldub", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* lduh $dr,@$sr */
{
@ARCH@_INSN_LDUH, "lduh", "lduh", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* lduh $dr,@($slo16,$sr) */
{
@ARCH@_INSN_LDUH_D, "lduh-d", "lduh", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* ld $dr,@$sr+ */
{
@ARCH@_INSN_LD_PLUS, "ld-plus", "ld", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* ld24 $dr,$uimm24 */
{
@ARCH@_INSN_LD24, "ld24", "ld24", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* ldi8 $dr,$simm8 */
{
@ARCH@_INSN_LDI8, "ldi8", "ldi8", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* ldi16 $dr,$hash$slo16 */
{
@ARCH@_INSN_LDI16, "ldi16", "ldi16", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* lock $dr,@$sr */
{
@ARCH@_INSN_LOCK, "lock", "lock", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* machi $src1,$src2 */
{
@ARCH@_INSN_MACHI, "machi", "machi", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* machi $src1,$src2,$acc */
{
@ARCH@_INSN_MACHI_A, "machi-a", "machi", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* maclo $src1,$src2 */
{
@ARCH@_INSN_MACLO, "maclo", "maclo", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* maclo $src1,$src2,$acc */
{
@ARCH@_INSN_MACLO_A, "maclo-a", "maclo", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* macwhi $src1,$src2 */
{
@ARCH@_INSN_MACWHI, "macwhi", "macwhi", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* macwhi $src1,$src2,$acc */
{
@ARCH@_INSN_MACWHI_A, "macwhi-a", "macwhi", 16,
{ 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
/* macwlo $src1,$src2 */
{
@ARCH@_INSN_MACWLO, "macwlo", "macwlo", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* macwlo $src1,$src2,$acc */
{
@ARCH@_INSN_MACWLO_A, "macwlo-a", "macwlo", 16,
{ 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
/* mul $dr,$sr */
{
@ARCH@_INSN_MUL, "mul", "mul", 16,
{ 0, { (1<<MACH_BASE), PIPE_S } }
},
/* mulhi $src1,$src2 */
{
@ARCH@_INSN_MULHI, "mulhi", "mulhi", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mulhi $src1,$src2,$acc */
{
@ARCH@_INSN_MULHI_A, "mulhi-a", "mulhi", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mullo $src1,$src2 */
{
@ARCH@_INSN_MULLO, "mullo", "mullo", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mullo $src1,$src2,$acc */
{
@ARCH@_INSN_MULLO_A, "mullo-a", "mullo", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mulwhi $src1,$src2 */
{
@ARCH@_INSN_MULWHI, "mulwhi", "mulwhi", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mulwhi $src1,$src2,$acc */
{
@ARCH@_INSN_MULWHI_A, "mulwhi-a", "mulwhi", 16,
{ 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
/* mulwlo $src1,$src2 */
{
@ARCH@_INSN_MULWLO, "mulwlo", "mulwlo", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mulwlo $src1,$src2,$acc */
{
@ARCH@_INSN_MULWLO_A, "mulwlo-a", "mulwlo", 16,
{ 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_S } }
},
/* mv $dr,$sr */
{
@ARCH@_INSN_MV, "mv", "mv", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* mvfachi $dr */
{
@ARCH@_INSN_MVFACHI, "mvfachi", "mvfachi", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mvfachi $dr,$accs */
{
@ARCH@_INSN_MVFACHI_A, "mvfachi-a", "mvfachi", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mvfaclo $dr */
{
@ARCH@_INSN_MVFACLO, "mvfaclo", "mvfaclo", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mvfaclo $dr,$accs */
{
@ARCH@_INSN_MVFACLO_A, "mvfaclo-a", "mvfaclo", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mvfacmi $dr */
{
@ARCH@_INSN_MVFACMI, "mvfacmi", "mvfacmi", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mvfacmi $dr,$accs */
{
@ARCH@_INSN_MVFACMI_A, "mvfacmi-a", "mvfacmi", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mvfc $dr,$scr */
{
@ARCH@_INSN_MVFC, "mvfc", "mvfc", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* mvtachi $src1 */
{
@ARCH@_INSN_MVTACHI, "mvtachi", "mvtachi", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mvtachi $src1,$accs */
{
@ARCH@_INSN_MVTACHI_A, "mvtachi-a", "mvtachi", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mvtaclo $src1 */
{
@ARCH@_INSN_MVTACLO, "mvtaclo", "mvtaclo", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* mvtaclo $src1,$accs */
{
@ARCH@_INSN_MVTACLO_A, "mvtaclo-a", "mvtaclo", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mvtc $sr,$dcr */
{
@ARCH@_INSN_MVTC, "mvtc", "mvtc", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* neg $dr,$sr */
{
@ARCH@_INSN_NEG, "neg", "neg", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* nop */
{
@ARCH@_INSN_NOP, "nop", "nop", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* not $dr,$sr */
{
@ARCH@_INSN_NOT, "not", "not", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* rac */
{
@ARCH@_INSN_RAC, "rac", "rac", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* rac $accd,$accs,$imm1 */
{
@ARCH@_INSN_RAC_DSI, "rac-dsi", "rac", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* rach */
{
@ARCH@_INSN_RACH, "rach", "rach", 16,
{ 0, { (1<<MACH_M32R), PIPE_S } }
},
/* rach $accd,$accs,$imm1 */
{
@ARCH@_INSN_RACH_DSI, "rach-dsi", "rach", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* rte */
{
@ARCH@_INSN_RTE, "rte", "rte", 16,
{ 0|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* seth $dr,$hash$hi16 */
{
@ARCH@_INSN_SETH, "seth", "seth", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* sll $dr,$sr */
{
@ARCH@_INSN_SLL, "sll", "sll", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* sll3 $dr,$sr,$simm16 */
{
@ARCH@_INSN_SLL3, "sll3", "sll3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* slli $dr,$uimm5 */
{
@ARCH@_INSN_SLLI, "slli", "slli", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* sra $dr,$sr */
{
@ARCH@_INSN_SRA, "sra", "sra", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* sra3 $dr,$sr,$simm16 */
{
@ARCH@_INSN_SRA3, "sra3", "sra3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* srai $dr,$uimm5 */
{
@ARCH@_INSN_SRAI, "srai", "srai", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* srl $dr,$sr */
{
@ARCH@_INSN_SRL, "srl", "srl", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* srl3 $dr,$sr,$simm16 */
{
@ARCH@_INSN_SRL3, "srl3", "srl3", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* srli $dr,$uimm5 */
{
@ARCH@_INSN_SRLI, "srli", "srli", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* st $src1,@$src2 */
{
@ARCH@_INSN_ST, "st", "st", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* st $src1,@($slo16,$src2) */
{
@ARCH@_INSN_ST_D, "st-d", "st", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* stb $src1,@$src2 */
{
@ARCH@_INSN_STB, "stb", "stb", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* stb $src1,@($slo16,$src2) */
{
@ARCH@_INSN_STB_D, "stb-d", "stb", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* sth $src1,@$src2 */
{
@ARCH@_INSN_STH, "sth", "sth", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* sth $src1,@($slo16,$src2) */
{
@ARCH@_INSN_STH_D, "sth-d", "sth", 32,
{ 0, { (1<<MACH_BASE), PIPE_NONE } }
},
/* st $src1,@+$src2 */
{
@ARCH@_INSN_ST_PLUS, "st-plus", "st", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* st $src1,@-$src2 */
{
@ARCH@_INSN_ST_MINUS, "st-minus", "st", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* sub $dr,$sr */
{
@ARCH@_INSN_SUB, "sub", "sub", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* subv $dr,$sr */
{
@ARCH@_INSN_SUBV, "subv", "subv", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* subx $dr,$sr */
{
@ARCH@_INSN_SUBX, "subx", "subx", 16,
{ 0, { (1<<MACH_BASE), PIPE_OS } }
},
/* trap $uimm4 */
{
@ARCH@_INSN_TRAP, "trap", "trap", 16,
{ 0|A(FILL_SLOT)|A(UNCOND_CTI), { (1<<MACH_BASE), PIPE_O } }
},
/* unlock $src1,@$src2 */
{
@ARCH@_INSN_UNLOCK, "unlock", "unlock", 16,
{ 0, { (1<<MACH_BASE), PIPE_O } }
},
/* satb $dr,$sr */
{
@ARCH@_INSN_SATB, "satb", "satb", 32,
{ 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
/* sath $dr,$sr */
{
@ARCH@_INSN_SATH, "sath", "sath", 32,
{ 0, { (1<<MACH_M32RX), PIPE_NONE } }
},
/* sat $dr,$sr */
{
@ARCH@_INSN_SAT, "sat", "sat", 32,
{ 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_NONE } }
},
/* pcmpbz $src2 */
{
@ARCH@_INSN_PCMPBZ, "pcmpbz", "pcmpbz", 16,
{ 0|A(SPECIAL), { (1<<MACH_M32RX), PIPE_OS } }
},
/* sadd */
{
@ARCH@_INSN_SADD, "sadd", "sadd", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* macwu1 $src1,$src2 */
{
@ARCH@_INSN_MACWU1, "macwu1", "macwu1", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* msblo $src1,$src2 */
{
@ARCH@_INSN_MSBLO, "msblo", "msblo", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* mulwu1 $src1,$src2 */
{
@ARCH@_INSN_MULWU1, "mulwu1", "mulwu1", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* maclh1 $src1,$src2 */
{
@ARCH@_INSN_MACLH1, "maclh1", "maclh1", 16,
{ 0, { (1<<MACH_M32RX), PIPE_S } }
},
/* sc */
{
@ARCH@_INSN_SC, "sc", "sc", 16,
{ 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
/* snc */
{
@ARCH@_INSN_SNC, "snc", "snc", 16,
{ 0|A(SPECIAL)|A(SKIP_CTI), { (1<<MACH_M32RX), PIPE_O } }
},
};
#undef OP
#undef A
/* Initialize anything needed to be done once, before any cpu_open call. */
static void init_tables PARAMS ((void));
static void
init_tables ()
{
}
static const CGEN_MACH * lookup_mach_via_bfd_name
PARAMS ((const CGEN_MACH *, const char *));
static void build_hw_table PARAMS ((CGEN_CPU_TABLE *));
static void build_ifield_table PARAMS ((CGEN_CPU_TABLE *));
static void build_operand_table PARAMS ((CGEN_CPU_TABLE *));
static void build_insn_table PARAMS ((CGEN_CPU_TABLE *));
static void @arch@_cgen_rebuild_tables PARAMS ((CGEN_CPU_TABLE *));
/* Subroutine of @arch@_cgen_cpu_open to look up a mach via its bfd name. */
static const CGEN_MACH *
lookup_mach_via_bfd_name (table, name)
const CGEN_MACH *table;
const char *name;
{
while (table->name)
{
if (strcmp (name, table->bfd_name) == 0)
return table;
++table;
}
abort ();
}
/* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
static void
build_hw_table (cd)
CGEN_CPU_TABLE *cd;
{
int i;
int machs = cd->machs;
const CGEN_HW_ENTRY *init = & @arch@_cgen_hw_table[0];
/* MAX_HW is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_HW_ENTRY **selected =
(const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
cd->hw_table.init_entries = init;
cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
/* ??? For now we just use machs to determine which ones we want. */
for (i = 0; init[i].name != NULL; ++i)
if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
& machs)
selected[init[i].type] = &init[i];
cd->hw_table.entries = selected;
cd->hw_table.num_entries = MAX_HW;
}
/* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
static void
build_ifield_table (cd)
CGEN_CPU_TABLE *cd;
{
cd->ifld_table = & @arch@_cgen_ifld_table[0];
}
/* Subroutine of @arch@_cgen_cpu_open to build the hardware table. */
static void
build_operand_table (cd)
CGEN_CPU_TABLE *cd;
{
int i;
int machs = cd->machs;
const CGEN_OPERAND *init = & @arch@_cgen_operand_table[0];
/* MAX_OPERANDS is only an upper bound on the number of selected entries.
However each entry is indexed by it's enum so there can be holes in
the table. */
const CGEN_OPERAND **selected =
(const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
cd->operand_table.init_entries = init;
cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
/* ??? For now we just use mach to determine which ones we want. */
for (i = 0; init[i].name != NULL; ++i)
if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
& machs)
selected[init[i].type] = &init[i];
cd->operand_table.entries = selected;
cd->operand_table.num_entries = MAX_OPERANDS;
}
/* Subroutine of @arch@_cgen_cpu_open to build the hardware table.
??? This could leave out insns not supported by the specified mach/isa,
but that would cause errors like "foo only supported by bar" to become
"unknown insn", so for now we include all insns and require the app to
do the checking later.
??? On the other hand, parsing of such insns may require their hardware or
operand elements to be in the table [which they mightn't be]. */
static void
build_insn_table (cd)
CGEN_CPU_TABLE *cd;
{
int i;
const CGEN_IBASE *ib = & @arch@_cgen_insn_table[0];
CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
for (i = 0; i < MAX_INSNS; ++i)
insns[i].base = &ib[i];
cd->insn_table.init_entries = insns;
cd->insn_table.entry_size = sizeof (CGEN_IBASE);
cd->insn_table.num_init_entries = MAX_INSNS;
}
/* Subroutine of @arch@_cgen_cpu_open to rebuild the tables. */
static void
@arch@_cgen_rebuild_tables (cd)
CGEN_CPU_TABLE *cd;
{
int i;
unsigned int isas = cd->isas;
unsigned int machs = cd->machs;
cd->int_insn_p = CGEN_INT_INSN_P;
/* Data derived from the isa spec. */
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
cd->default_insn_bitsize = UNSET;
cd->base_insn_bitsize = UNSET;
cd->min_insn_bitsize = 65535; /* some ridiculously big number */
cd->max_insn_bitsize = 0;
for (i = 0; i < MAX_ISAS; ++i)
if (((1 << i) & isas) != 0)
{
const CGEN_ISA *isa = & @arch@_cgen_isa_table[i];
/* Default insn sizes of all selected isas must be
equal or we set the result to 0, meaning "unknown". */
if (cd->default_insn_bitsize == UNSET)
cd->default_insn_bitsize = isa->default_insn_bitsize;
else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
; /* this is ok */
else
cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
/* Base insn sizes of all selected isas must be equal
or we set the result to 0, meaning "unknown". */
if (cd->base_insn_bitsize == UNSET)
cd->base_insn_bitsize = isa->base_insn_bitsize;
else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
; /* this is ok */
else
cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
/* Set min,max insn sizes. */
if (isa->min_insn_bitsize < cd->min_insn_bitsize)
cd->min_insn_bitsize = isa->min_insn_bitsize;
if (isa->max_insn_bitsize > cd->max_insn_bitsize)
cd->max_insn_bitsize = isa->max_insn_bitsize;
}
/* Data derived from the mach spec. */
for (i = 0; i < MAX_MACHS; ++i)
if (((1 << i) & machs) != 0)
{
const CGEN_MACH *mach = & @arch@_cgen_mach_table[i];
if (mach->insn_chunk_bitsize != 0)
{
if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
{
fprintf (stderr, "@arch@_cgen_rebuild_tables: conflicting insn-chunk-bitsize values: `%d' vs. `%d'\n",
cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
abort ();
}
cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
}
}
/* Determine which hw elements are used by MACH. */
build_hw_table (cd);
/* Build the ifield table. */
build_ifield_table (cd);
/* Determine which operands are used by MACH/ISA. */
build_operand_table (cd);
/* Build the instruction table. */
build_insn_table (cd);
}
/* Initialize a cpu table and return a descriptor.
It's much like opening a file, and must be the first function called.
The arguments are a set of (type/value) pairs, terminated with
CGEN_CPU_OPEN_END.
Currently supported values:
CGEN_CPU_OPEN_ISAS: bitmap of values in enum isa_attr
CGEN_CPU_OPEN_MACHS: bitmap of values in enum mach_attr
CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
CGEN_CPU_OPEN_ENDIAN: specify endian choice
CGEN_CPU_OPEN_END: terminates arguments
??? Simultaneous multiple isas might not make sense, but it's not (yet)
precluded.
??? We only support ISO C stdargs here, not K&R.
Laziness, plus experiment to see if anything requires K&R - eventually
K&R will no longer be supported - e.g. GDB is currently trying this. */
CGEN_CPU_DESC
@arch@_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
{
CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
static int init_p;
unsigned int isas = 0; /* 0 = "unspecified" */
unsigned int machs = 0; /* 0 = "unspecified" */
enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
va_list ap;
if (! init_p)
{
init_tables ();
init_p = 1;
}
memset (cd, 0, sizeof (*cd));
va_start (ap, arg_type);
while (arg_type != CGEN_CPU_OPEN_END)
{
switch (arg_type)
{
case CGEN_CPU_OPEN_ISAS :
isas = va_arg (ap, unsigned int);
break;
case CGEN_CPU_OPEN_MACHS :
machs = va_arg (ap, unsigned int);
break;
case CGEN_CPU_OPEN_BFDMACH :
{
const char *name = va_arg (ap, const char *);
const CGEN_MACH *mach =
lookup_mach_via_bfd_name (@arch@_cgen_mach_table, name);
machs |= 1 << mach->num;
break;
}
case CGEN_CPU_OPEN_ENDIAN :
endian = va_arg (ap, enum cgen_endian);
break;
default :
fprintf (stderr, "@arch@_cgen_cpu_open: unsupported argument `%d'\n",
arg_type);
abort (); /* ??? return NULL? */
}
arg_type = va_arg (ap, enum cgen_cpu_open_arg);
}
va_end (ap);
/* mach unspecified means "all" */
if (machs == 0)
machs = (1 << MAX_MACHS) - 1;
/* base mach is always selected */
machs |= 1;
/* isa unspecified means "all" */
if (isas == 0)
isas = (1 << MAX_ISAS) - 1;
if (endian == CGEN_ENDIAN_UNKNOWN)
{
/* ??? If target has only one, could have a default. */
fprintf (stderr, "@arch@_cgen_cpu_open: no endianness specified\n");
abort ();
}
cd->isas = isas;
cd->machs = machs;
cd->endian = endian;
/* FIXME: for the sparc case we can determine insn-endianness statically.
The worry here is where both data and insn endian can be independently
chosen, in which case this function will need another argument.
Actually, will want to allow for more arguments in the future anyway. */
cd->insn_endian = endian;
/* Table (re)builder. */
cd->rebuild_tables = @arch@_cgen_rebuild_tables;
@arch@_cgen_rebuild_tables (cd);
/* Default to not allowing signed overflow. */
cd->signed_overflow_ok_p = 0;
return (CGEN_CPU_DESC) cd;
}
/* Cover fn to @arch@_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
MACH_NAME is the bfd name of the mach. */
CGEN_CPU_DESC
@arch@_cgen_cpu_open_1 (mach_name, endian)
const char *mach_name;
enum cgen_endian endian;
{
return @arch@_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
CGEN_CPU_OPEN_ENDIAN, endian,
CGEN_CPU_OPEN_END);
}
/* Close a cpu table.
??? This can live in a machine independent file, but there's currently
no place to put this file (there's no libcgen). libopcodes is the wrong
place as some simulator ports use this but they don't use libopcodes. */
void
@arch@_cgen_cpu_close (cd)
CGEN_CPU_DESC cd;
{
unsigned int i;
const CGEN_INSN *insns;
if (cd->macro_insn_table.init_entries)
{
insns = cd->macro_insn_table.init_entries;
for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX ((insns)))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->insn_table.init_entries)
{
insns = cd->insn_table.init_entries;
for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
{
if (CGEN_INSN_RX (insns))
regfree (CGEN_INSN_RX (insns));
}
}
if (cd->macro_insn_table.init_entries)
free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
if (cd->insn_table.init_entries)
free ((CGEN_INSN *) cd->insn_table.init_entries);
if (cd->hw_table.entries)
free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
if (cd->operand_table.entries)
free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
free (cd);
}
^ permalink raw reply [flat|nested] 3+ messages in thread
* Exact sequences for running cgen
2003-06-13 17:46 Exact sequences for running cgen Michael Meissner
@ 2003-06-13 18:16 ` Doug Evans
2003-06-15 16:55 ` Michael Meissner
0 siblings, 1 reply; 3+ messages in thread
From: Doug Evans @ 2003-06-13 18:16 UTC (permalink / raw)
To: Michael Meissner; +Cc: cgen
Michael Meissner writes:
> Ok, I must be doing something wrong. Could somebody give me an exact
> walk-through of how to set up the cgen environment. I have tried using the cvs
> sources, and the snapshot. I have tried building cgen in place, as well as my
> usual preference of building it in a separate build directory. The last time I
> asked this question, I was told just run the make in place, but neither the
> snapshot nor the cvs sources have a Makefile. I have tried using a Red Hat 8.0
> system, as well as Red Hat 9 (using a 1.4.3 guile compiled since
>
> Here is one attempt:
>
> $ tar -xvjf snapshot-20030607.tar.bz2
> $ cd cgen/cgen
> $ ./configure --target=m32r-unknown-elf
> $ make desc
>
> At this point it runs, but if you look at the tmp-desc.h and tmp-desc.c files,
> you see that it has not substituted M32R for @ARCH@ and m32r for @arch@ as I
> would expect. See the attachments for the tmp-desc.h and tmp-desc.c files.
The tmp-desc.[ch] files get subsequently fed through sed to s/@ARCH@/FOO/
and this happens when you run the generators from the opcodes directory.
"Final" versions of the generated files are always built from the
application dir (pedantic: except html since there is no app. dir).
The rules in cgen/Makefile exist just so one can generate something
and have a gander at them to see if they look correct.
In normal production work, one configures with --enable-cgen-maint,
and builds in the opcodes directory and lets the dependencies
in opcodes/Makefile regenerate the files whenever the .cpu file changes.
Ditto for sim, sid, etc.
So, exact walk-through:
1) mkdir obj
2) cd obj
3) /path/to/binutils+cgen/configure --target=m32r-elf --enable-cgen-maint
4) touch /path/to/binutils+cgen/cgen/cpu/m32r.cpu # ensure files get rebuilt
5) cd opcodes
6) make stamp-m32r
i.e. Regarding:
> The last time I
> asked this question, I was told just run the make in place, but neither the
> snapshot nor the cvs sources have a Makefile
I should have made clear that "in place" means in the opcodes
build directory, not cgen.
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: Exact sequences for running cgen
2003-06-13 18:16 ` Doug Evans
@ 2003-06-15 16:55 ` Michael Meissner
0 siblings, 0 replies; 3+ messages in thread
From: Michael Meissner @ 2003-06-15 16:55 UTC (permalink / raw)
To: cgen
On Fri, Jun 13, 2003 at 11:15:52AM -0700, Doug Evans wrote:
> Michael Meissner writes:
> > Ok, I must be doing something wrong. Could somebody give me an exact
> > walk-through of how to set up the cgen environment. I have tried using the cvs
> > sources, and the snapshot. I have tried building cgen in place, as well as my
> > usual preference of building it in a separate build directory. The last time I
> > asked this question, I was told just run the make in place, but neither the
> > snapshot nor the cvs sources have a Makefile. I have tried using a Red Hat 8.0
> > system, as well as Red Hat 9 (using a 1.4.3 guile compiled since
> >
> > Here is one attempt:
> >
> > $ tar -xvjf snapshot-20030607.tar.bz2
> > $ cd cgen/cgen
> > $ ./configure --target=m32r-unknown-elf
> > $ make desc
> >
> > At this point it runs, but if you look at the tmp-desc.h and tmp-desc.c files,
> > you see that it has not substituted M32R for @ARCH@ and m32r for @arch@ as I
> > would expect. See the attachments for the tmp-desc.h and tmp-desc.c files.
>
> The tmp-desc.[ch] files get subsequently fed through sed to s/@ARCH@/FOO/
> and this happens when you run the generators from the opcodes directory.
> "Final" versions of the generated files are always built from the
> application dir (pedantic: except html since there is no app. dir).
> The rules in cgen/Makefile exist just so one can generate something
> and have a gander at them to see if they look correct.
>
> In normal production work, one configures with --enable-cgen-maint,
> and builds in the opcodes directory and lets the dependencies
> in opcodes/Makefile regenerate the files whenever the .cpu file changes.
> Ditto for sim, sid, etc.
>
> So, exact walk-through:
>
> 1) mkdir obj
> 2) cd obj
> 3) /path/to/binutils+cgen/configure --target=m32r-elf --enable-cgen-maint
> 4) touch /path/to/binutils+cgen/cgen/cpu/m32r.cpu # ensure files get rebuilt
> 5) cd opcodes
> 6) make stamp-m32r
Thanks, thats a help. I guess I missed it on the first read-through of the
manual.
--
Michael Meissner
email: gnu@the-meissners.org
http://www.the-meissners.org
^ permalink raw reply [flat|nested] 3+ messages in thread
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2003-06-13 17:46 Exact sequences for running cgen Michael Meissner
2003-06-13 18:16 ` Doug Evans
2003-06-15 16:55 ` Michael Meissner
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