x86-like target

x86-like target

[Stan Cox]

What is the best way to handle an x86 like target wrt endianness?  By
x86 like I mean: 
1. instructions are variable length "big endian" bytestreams
2. immediate and address fields within instructions are little endian
3. the processor is little endian

Defining as:
  (default-insn-bitsize 32)
  (base-insn-bitsize 32)
  (default-insn-word-bitsize 32)
  derived/anyof operands
  big endian bfd
  pass CGEN_ENDIAN_BIG to m16c_cgen_cpu_open  
assembles instructions correctly except immediates and displacements
are, of course, big endian.  Changing:
  little endian bfd
  pass CGEN_ENDIAN_BIG to m16c_cgen_cpu_open  
  set BFD_ENDIAN_BIG in disassemble.c
assembles instructions correctly except immediates and displacements
are still not correct and relocations cannot be handled by
the generic relocation handler since instruction bytes are now fetched
in little endian order. 

What is the best way to support this so that immediates from cgen,
addresses from gas, and addresses and relocations from ld are all handled
correctly? 

Re: x86-like target

[Frank Ch. Eigler]

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Hi -

> [...one configuration...]
> assembles instructions correctly except immediates and displacements
> are, of course, big endian.
> [...another configuration...]
> assembles instructions correctly except immediates and displacements
> are still not correct and relocations cannot be handled by
> the generic relocation handler since instruction bytes are now fetched
> in little endian order. 
> [...]

Have you tried custom ifield inserters/extractors?
Probably the first configuration is a better fit.

- FChE

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