* [patch] mep: ivc2 support
@ 2009-06-24 3:27 DJ Delorie
0 siblings, 0 replies; 2+ messages in thread
From: DJ Delorie @ 2009-06-24 3:27 UTC (permalink / raw)
To: binutils, sid, cgen
[second try, the first was too big for some of the lists. This has no
regenerated files, and is compressed]
Various patches needed to better support IVC2 intrinsics and fix some
minor bugs. Committed.
[cgen]
* intrinsics.scm: Updates to support IVC2.
(belongs-to-group?): Check IVC2 slots.
(-slots-attribute): New.
(targets::attributes): Add SLOTS.
(target:add-well-known-intrinsics): Add CPMOV.
(md-insn): Add CPTYPE and CRET?.
(add-md-insn): Likewise.
(add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has
duplicate insns with different bit patterns.
(write-cgen-insn?): Add cret? support.
(intrinsics.h): Add vector types.
(runtime-op): Add vector support.
(intrinsic-protos.h): Let GCC define its types. Add cret? support.
* cpu/mep-core.cpu: Add CPTYPE and CRET attributes.
* cpu/mep-ivc2.cpu: Update all insns to include type information.
(h-cr-ivc2): Default to typeless.
(h-ccr-ivc2): Fix register width.
(SLOTS): Fix values and default.
(ivc2_*): Add control register names.
(crop, crqp, crpp, croc, crqc, crpc): Default to typeless.
[opcodes]
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
[sid/component/cgen-cpu/mep]
* ivc2-cop.cxx (ivc2_cphadd_w): Change to return value.
(ivc2_cpsubaca0u_b): Remove debug line.
* ivc2-cpu.h (ivc2_cpccadd_b): Change to return value.
* mep-cop1-16-decode.cxx: Regenerate.
* mep-cop1-16-sem.cxx: Regenerate.
* mep-cop1-32-decode.cxx: Regenerate.
* mep-cop1-32-sem.cxx: Regenerate.
* mep-cop1-48-decode.cxx: Regenerate.
* mep-cop1-48-sem.cxx: Regenerate.
* mep-cop1-64-decode.cxx: Regenerate.
* mep-cop1-64-sem.cxx: Regenerate.
* mep-core1-decode.cxx: Regenerate.
* mep-cpu.h: Regenerate.
* mep-decode.cxx: Regenerate.
* mep-desc.h: Regenerate.
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#E@4`
`
end
^ permalink raw reply [flat|nested] 2+ messages in thread
* [patch] mep: ivc2 support
@ 2009-06-24 3:14 DJ Delorie
0 siblings, 0 replies; 2+ messages in thread
From: DJ Delorie @ 2009-06-24 3:14 UTC (permalink / raw)
To: binutils, sid, cgen
Various patches needed to better support IVC2 intrinsics and fix some
minor bugs. Committed.
[cgen]
* intrinsics.scm: Updates to support IVC2.
(belongs-to-group?): Check IVC2 slots.
(-slots-attribute): New.
(targets::attributes): Add SLOTS.
(target:add-well-known-intrinsics): Add CPMOV.
(md-insn): Add CPTYPE and CRET?.
(add-md-insn): Likewise.
(add-intrinsic-for-isa): Disable the duplicate tests, as IVC2 has
duplicate insns with different bit patterns.
(write-cgen-insn?): Add cret? support.
(intrinsics.h): Add vector types.
(runtime-op): Add vector support.
(intrinsic-protos.h): Let GCC define its types. Add cret? support.
* cpu/mep-core.cpu: Add CPTYPE and CRET attributes.
* cpu/mep-ivc2.cpu: Update all insns to include type information.
(h-cr-ivc2): Default to typeless.
(h-ccr-ivc2): Fix register width.
(SLOTS): Fix values and default.
(ivc2_*): Add control register names.
(crop, crqp, crpp, croc, crqc, crpc): Default to typeless.
[opcodes]
* mep-desc.c: Regenerate.
* mep-desc.h: Regenerate.
* mep-dis.c: Regenerate.
* mep-ibld.c: Regenerate.
* mep-opc.c: Regenerate.
[sid/component/cgen-cpu/mep]
* ivc2-cop.cxx (ivc2_cphadd_w): Change to return value.
(ivc2_cpsubaca0u_b): Remove debug line.
* ivc2-cpu.h (ivc2_cpccadd_b): Change to return value.
* mep-cop1-16-decode.cxx: Regenerate.
* mep-cop1-16-sem.cxx: Regenerate.
* mep-cop1-32-decode.cxx: Regenerate.
* mep-cop1-32-sem.cxx: Regenerate.
* mep-cop1-48-decode.cxx: Regenerate.
* mep-cop1-48-sem.cxx: Regenerate.
* mep-cop1-64-decode.cxx: Regenerate.
* mep-cop1-64-sem.cxx: Regenerate.
* mep-core1-decode.cxx: Regenerate.
* mep-cpu.h: Regenerate.
* mep-decode.cxx: Regenerate.
* mep-desc.h: Regenerate.
Index: cgen/intrinsics.scm
===================================================================
RCS file: /cvs/src/src/cgen/intrinsics.scm,v
retrieving revision 1.3
diff -p -U3 -r1.3 intrinsics.scm
--- cgen/intrinsics.scm 14 May 2009 01:39:58 -0000 1.3
+++ cgen/intrinsics.scm 24 Jun 2009 02:59:23 -0000
@@ -359,7 +359,7 @@
(else "r"))))))))
;; The first hard register available to the intrinsics generator.
-(define target:first-unused-register 97)
+(define target:first-unused-register 113)
;; The instructions mapped to a particular intrinsic can be subdivided
;; into groups, each representing a particular form of code generation.
@@ -370,7 +370,14 @@
;; True if INSN belongs to GROUP, where GROUP is a membmer of TARGET:GROUPS.
(define (target:belongs-to-group? insn group)
(case (obj-attr-value (md-insn:cgen-insn insn) 'SLOT)
- ((NONE) #t)
+ ((NONE)
+ (if (obj-attr-value (md-insn:cgen-insn insn) 'SLOTS)
+ (case (obj-attr-value (md-insn:cgen-insn insn) 'SLOTS)
+ ((CORE) #t)
+ ((C3) (equal? group 'normal))
+ (else (equal? group 'vliw))
+ )
+ (equal? group 'normal)))
((C3) (equal? group 'normal))
((V1 V3) (equal? group 'vliw))))
@@ -402,6 +409,12 @@
(define (-stall-attribute insn)
(string-downcase (st (obj-attr-value insn 'STALL))))
+(define (-slots-attribute insn)
+ (let ((slots (obj-attr-value insn 'SLOTS)))
+ (if slots
+ (string-downcase (gen-c-symbol (st slots)))
+ "core")))
+
;; Return the define_insn attributes for INSN as a list of (NAME . VALUE)
;; pairs.
(define (target:attributes insn)
@@ -410,6 +423,7 @@
(cons 'latency (-latency-attribute cgen-insn))
(cons 'length (-length-attribute cgen-insn))
(cons 'slot (-slot-attribute cgen-insn))
+ (cons 'slots (-slots-attribute cgen-insn))
(if (eq? (obj-attr-value cgen-insn 'STALL) 'SHIFTI)
(cons 'shiftop "operand2")
(cons 'stall (-stall-attribute cgen-insn))))))
@@ -446,6 +460,7 @@
(apply-list well-known-intrinsic
`(("cmov")
+ ("cpmov")
("cmovi" set)
("cmov1")
("cmov2")
@@ -683,8 +698,13 @@
;; will have a valid WRITE-INDEX.
;;
;; OPERANDS is a concatenation of OUTPUTS and INPUTS.
+;;
+;; CPTYPE is the type to use for coprocessor operands (like V4HI)
+;;
+;; CRET? is set if the first argument is returned rather than passed.
+
(make-struct md-insn (md-name index intrinsic cgen-insn syntax arguments
- inputs outputs operands))
+ inputs outputs operands cptype cret?))
;; Return the name of the underlying cgen insn, mostly used for
;; error reporting.
@@ -969,7 +989,14 @@
(quiet-inputs (find (lambda (op)
(and (not (memq op inputs))
(not (memq op outputs))))
- arguments)))
+ arguments))
+
+ ;; Allow an intrinsic to specify a type for coprocessor
+ ;; operands, as they tend to be insn-specific vector types.
+ (cptype (obj-attr-value insn 'CPTYPE))
+
+ (cret? (equal? (obj-attr-value insn 'CRET) 'FIRST))
+ )
;; Number each argument operand according to its position in the list.
(number-list md-operand:set-arg-index! arguments 0)
@@ -1000,7 +1027,7 @@
(cons (md-insn:make (sa md-prefix (gen-c-symbol (obj:name insn)))
#f intrinsic insn syntax
arguments inputs outputs
- (append outputs inputs))
+ (append outputs inputs) cptype cret?)
md-insns))))
;; Make INSN available when generating code for ISA, updating INSN's
@@ -1020,19 +1047,24 @@
;; implementation. If it isn't, report an error, otherwise
;; use INSN as the new bellwether.
(let ((bellwether (cdr entry)))
- (if (not (md-insn:syntax<=? bellwether insn))
- (error (sa "instructions \"" (md-insn:cgen-name insn)
- "\" and \"" (md-insn:cgen-name bellwether)
- "\" are both mapped to intrinsic \""
- (intrinsic:name intrinsic)
- "\" but do not have a compatible syntax")))
-
- (if (not (md-insn:operands<=? bellwether insn))
- (error (sa "instructions \"" (md-insn:cgen-name insn)
- "\" and \"" (md-insn:cgen-name bellwether)
- "\" are both mapped to intrinsic \""
- (intrinsic:name intrinsic)
- "\" but do not have compatible semantics")))
+
+;; This is temporarily disabled as some IVC2 intrinsics *do* have the
+;; same actual signature and operands, but different bit encodings
+;; depending on the slot. This different syntax makes them not match.
+
+;; (if (not (md-insn:syntax<=? bellwether insn))
+;; (error (sa "instructions \"" (md-insn:cgen-name insn)
+;; "\" and \"" (md-insn:cgen-name bellwether)
+;; "\" are both mapped to intrinsic \""
+;; (intrinsic:name intrinsic)
+;; "\" but do not have a compatible syntax")))
+
+;; (if (not (md-insn:operands<=? bellwether insn))
+;; (error (sa "instructions \"" (md-insn:cgen-name insn)
+;; "\" and \"" (md-insn:cgen-name bellwether)
+;; "\" are both mapped to intrinsic \""
+;; (intrinsic:name intrinsic)
+;; "\" but do not have compatible semantics")))
(set-cdr! entry insn)))))
@@ -1285,10 +1317,21 @@
(if (not (get-immediate-predicate name))
(set-immediate-predicate! name op)))))
-(define (enum-type op)
+(define (enum-type op cptype)
(cond
- ((is-h-cr64? (md-operand:hw op)) "cgen_regnum_operand_type_DI")
- ((is-h-cr? (md-operand:hw op)) "cgen_regnum_operand_type_SI")
+ ((is-h-cr64? (md-operand:hw op))
+ (case cptype
+ ((V8QI) "cgen_regnum_operand_type_V8QI")
+ ((V4HI) "cgen_regnum_operand_type_V4HI")
+ ((V2SI) "cgen_regnum_operand_type_V2SI")
+ ((V8UQI) "cgen_regnum_operand_type_V8UQI")
+ ((V4UHI) "cgen_regnum_operand_type_V4UHI")
+ ((V2USI) "cgen_regnum_operand_type_V2USI")
+ ((VECT) "cgen_regnum_operand_type_VECTOR")
+ ((CP_DATA_BUS_INT) "cgen_regnum_operand_type_CP_DATA_BUS_INT")
+ (else "cgen_regnum_operand_type_DI")))
+ ((is-h-cr? (md-operand:hw op))
+ "cgen_regnum_operand_type_SI")
(else
(case (md-operand:cdata op)
((POINTER) "cgen_regnum_operand_type_POINTER")
@@ -1319,6 +1362,9 @@
(string-write (st (length (md-insn:arguments insn))))
(comma-line-break)
+ (string-write (if (md-insn:cret? insn) "1" "0"))
+
+ (comma-line-break)
(write-construct "{ " " }"
(write-nonempty-list
comma-break
@@ -1337,7 +1383,7 @@
"{ " (st (md-operand:upper-bound op))
", " (st (target:base-reg (md-operand:hw op))))
(string-write "{ 0, 0"))
- (string-write ", " (enum-type op)
+ (string-write ", " (enum-type op (md-insn:cptype insn))
", " (if (and (not (equal? (md-operand:cdata op) 'REGNUM))
(md-operand:write-index op))
"1" "0")
@@ -1410,6 +1456,13 @@
" cgen_regnum_operand_type_SI, /* __cop long */\n"
" cgen_regnum_operand_type_DI, /* __cop long long */\n"
" cgen_regnum_operand_type_CP_DATA_BUS_INT, /* cp_data_bus_int */\n"
+ " cgen_regnum_operand_type_VECTOR, /* opaque vector type */\n"
+ " cgen_regnum_operand_type_V8QI, /* V8QI vector type */\n"
+ " cgen_regnum_operand_type_V4HI, /* V4HI vector type */\n"
+ " cgen_regnum_operand_type_V2SI, /* V2SI vector type */\n"
+ " cgen_regnum_operand_type_V8UQI, /* V8UQI vector type */\n"
+ " cgen_regnum_operand_type_V4UHI, /* V4UHI vector type */\n"
+ " cgen_regnum_operand_type_V2USI, /* V2USI vector type */\n"
" cgen_regnum_operand_type_DEFAULT = cgen_regnum_operand_type_LONG\n"
"};\n"
"\n"
@@ -1443,6 +1496,9 @@
" /* The number of arguments to the intrinsic function. */\n"
" unsigned int num_args;\n"
"\n"
+ " /* If true, the first argument is the return value. */\n"
+ " unsigned int cret_p;\n"
+ "\n"
" /* Maps operand numbers to argument numbers. */\n"
" unsigned int op_mapping[10];\n"
"\n"
@@ -1512,7 +1568,7 @@
;; PROTOTYPE GENERATOR
;; -------------------
-(define (runtime-type op)
+(define (runtime-type op cptype retval)
(sa (case (md-operand:cdata op)
((POINTER) "long *")
((LABEL) "void *")
@@ -1522,10 +1578,21 @@
((USHORT) "unsigned short")
((CHAR) "char")
((UCHAR) "unsigned char")
- ((CP_DATA_BUS_INT) "cp_data_bus_int")
+ ((CP_DATA_BUS_INT)
+ ;;(logit 0 "op " (md-operand:cdata op) " cptype " cptype "\n")
+ (case cptype
+ ((V2SI) "cp_v2si")
+ ((V4HI) "cp_v4hi")
+ ((V8QI) "cp_v8qi")
+ ((V2USI) "cp_v2usi")
+ ((V4UHI) "cp_v4uhi")
+ ((V8UQI) "cp_v8uqi")
+ ((VECT) "cp_vector")
+ (else "cp_data_bus_int")))
(else "long"))
(if (and (not (equal? (md-operand:cdata op) 'REGNUM))
- (md-operand:write-index op))
+ (md-operand:write-index op)
+ (not retval))
"*" "")))
(define (intrinsic-protos.h) ; i.e., intrinsics.h
@@ -1534,11 +1601,19 @@
"/* DO NOT EDIT: This file is automatically generated by CGEN.\n"
" Any changes you make will be discarded when it is next regenerated.\n"
"*/\n\n"
+ "/* GCC defines these internally, as follows... \n";
"#if __MEP_CONFIG_CP_DATA_BUS_WIDTH == 64\n"
" typedef long long cp_data_bus_int;\n"
"#else\n"
" typedef long cp_data_bus_int;\n"
- "#endif\n")
+ "#endif\n"
+ "typedef char cp_v8qi __attribute__((vector_size(8)));\n"
+ "typedef unsigned char cp_v8uqi __attribute__((vector_size(8)));\n"
+ "typedef short cp_v4hi __attribute__((vector_size(8)));\n"
+ "typedef unsigned short cp_v4uhi __attribute__((vector_size(8)));\n"
+ "typedef int cp_v2si __attribute__((vector_size(8)));\n"
+ "typedef unsigned int cp_v2usi __attribute__((vector_size(8)));\n"
+ "*/\n\n")
(analyze-intrinsics!)
(message "Generating prototype file...\n")
(target:for-each-isa!
@@ -1549,9 +1624,18 @@
(let ((entry (assoc isa (intrinsic:isas intrinsic))))
(if entry
(let* ((insn (cdr entry))
- (proto (sa "void " (intrinsic:name intrinsic)
- " (" (stringize (map runtime-type
- (md-insn:arguments insn))
+ (arguments (md-insn:arguments insn))
+ (retval (if (md-insn:cret? insn)
+ (runtime-type (car arguments) (md-insn:cptype insn) #t)
+ "void"))
+ (proto (sa retval " " (intrinsic:name intrinsic)
+ " (" (stringize (map (lambda (arg)
+ (runtime-type arg
+ (md-insn:cptype insn) #f))
+ (if (md-insn:cret? insn)
+ (cdr arguments)
+ arguments)
+ )
", ")
");"))
(proto-len (string-length proto))
Index: cgen/cpu/mep-core.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/mep-core.cpu,v
retrieving revision 1.6
diff -p -U3 -r1.6 mep-core.cpu
--- cgen/cpu/mep-core.cpu 30 Apr 2009 21:07:57 -0000 1.6
+++ cgen/cpu/mep-core.cpu 24 Jun 2009 02:59:23 -0000
@@ -615,6 +615,25 @@
(default LONG))
(define-attr
+ (type enum)
+ (for insn)
+ (name CPTYPE)
+ (comment "datatype to use for coprocessor values")
+ (values CP_DATA_BUS_INT VECT V2SI V4HI V8QI V2USI V4UHI V8UQI)
+ (default CP_DATA_BUS_INT))
+
+(define-attr
+ (type enum)
+ (for insn)
+ (name CRET)
+ ;; VOID - all arguments are passed as parameters; if any are written, pointers to them are passed.
+ ;; FIRST - the first argument is the return value.
+ ;; FIRSTCOPY - the first argument is the return value, but a copy is also the first parameter.
+ (values VOID FIRST FIRSTCOPY)
+ (default VOID)
+ (comment "Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it."))
+
+(define-attr
(type integer)
(for operand)
(name ALIGN)
Index: cgen/cpu/mep-ivc2.cpu
===================================================================
RCS file: /cvs/src/src/cgen/cpu/mep-ivc2.cpu,v
retrieving revision 1.4
diff -p -U3 -r1.4 mep-ivc2.cpu
--- cgen/cpu/mep-ivc2.cpu 28 May 2009 22:53:08 -0000 1.4
+++ cgen/cpu/mep-ivc2.cpu 24 Jun 2009 02:59:23 -0000
@@ -40,7 +40,7 @@
(define-hardware
(name h-cr-ivc2)
(comment "64-bit coprocessor registers for ivc2 coprocessor")
- (attrs VIRTUAL all-mep-core-isas)
+ (attrs VIRTUAL all-mep-core-isas (CDATA CP_DATA_BUS_INT))
(type register DI (64))
(set (index newval) (c-call VOID "h_cr64_set" index newval))
(get (index) (c-call DI "h_cr64_get" index))
@@ -56,9 +56,9 @@
(name h-ccr-ivc2)
(comment "Coprocessor control registers for ivc2 coprocessor")
(attrs VIRTUAL all-mep-isas)
- (type register DI (64))
+ (type register SI (32))
(set (index newval) (c-call VOID "h_ccr_set" index newval))
- (get (index) (c-call DI "h_ccr_get" index))
+ (get (index) (c-call SI "h_ccr_get" index))
(indices keyword ""
(.splice
@@ -98,7 +98,8 @@
(for insn)
(name SLOTS)
(comment "slots for which this opcode is valid - c3, p0s, p0, p1")
- (values core c3 p0s p0 p1)
+ (values CORE C3 P0S P0 P1)
+ (default CORE)
)
;-----------------------------------------------------------------------------
@@ -173,9 +174,36 @@
)
)
-(dnop croc "$CRo C3" (all-mep-isas) h-cr64 f-ivc2-5u7)
-(dnop crqc "$CRq C3" (all-mep-isas) h-cr64 f-ivc2-5u21)
-(dnop crpc "$CRp C3" (all-mep-isas) h-cr64 f-ivc2-5u26)
+(dnop ivc2_csar0 "ivc2_csar0" (all-ivc2-isas) h-ccr-ivc2 0)
+(dnop ivc2_cc "ivc2_cc" (all-ivc2-isas) h-ccr-ivc2 1)
+(dnop ivc2_cofr0 "ivc2_cofr0" (all-ivc2-isas) h-ccr-ivc2 4)
+(dnop ivc2_cofr1 "ivc2_cofr1" (all-ivc2-isas) h-ccr-ivc2 5)
+(dnop ivc2_cofa0 "ivc2_cofa0" (all-ivc2-isas) h-ccr-ivc2 6)
+(dnop ivc2_cofa1 "ivc2_cofa1" (all-ivc2-isas) h-ccr-ivc2 7)
+
+(dnop ivc2_csar1 "ivc2_csar1" (all-ivc2-isas) h-ccr-ivc2 15)
+
+(dnop ivc2_acc0_0 "acc0_0" (all-ivc2-isas) h-ccr-ivc2 16)
+(dnop ivc2_acc0_1 "acc0_1" (all-ivc2-isas) h-ccr-ivc2 17)
+(dnop ivc2_acc0_2 "acc0_2" (all-ivc2-isas) h-ccr-ivc2 18)
+(dnop ivc2_acc0_3 "acc0_3" (all-ivc2-isas) h-ccr-ivc2 19)
+(dnop ivc2_acc0_4 "acc0_4" (all-ivc2-isas) h-ccr-ivc2 20)
+(dnop ivc2_acc0_5 "acc0_5" (all-ivc2-isas) h-ccr-ivc2 21)
+(dnop ivc2_acc0_6 "acc0_6" (all-ivc2-isas) h-ccr-ivc2 22)
+(dnop ivc2_acc0_7 "acc0_7" (all-ivc2-isas) h-ccr-ivc2 23)
+
+(dnop ivc2_acc1_0 "acc1_0" (all-ivc2-isas) h-ccr-ivc2 24)
+(dnop ivc2_acc1_1 "acc1_1" (all-ivc2-isas) h-ccr-ivc2 25)
+(dnop ivc2_acc1_2 "acc1_2" (all-ivc2-isas) h-ccr-ivc2 26)
+(dnop ivc2_acc1_3 "acc1_3" (all-ivc2-isas) h-ccr-ivc2 27)
+(dnop ivc2_acc1_4 "acc1_4" (all-ivc2-isas) h-ccr-ivc2 28)
+(dnop ivc2_acc1_5 "acc1_5" (all-ivc2-isas) h-ccr-ivc2 29)
+(dnop ivc2_acc1_6 "acc1_6" (all-ivc2-isas) h-ccr-ivc2 30)
+(dnop ivc2_acc1_7 "acc1_7" (all-ivc2-isas) h-ccr-ivc2 31)
+
+(dnop croc "$CRo C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u7)
+(dnop crqc "$CRq C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u21)
+(dnop crpc "$CRp C3" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u26)
(dnop ivc-x-6-1 "filler" (all-mep-isas) h-uint f-ivc2-1u6)
(dnop ivc-x-6-2 "filler" (all-mep-isas) h-uint f-ivc2-2u6)
@@ -204,9 +232,9 @@
(dnop simm8p20 "sImm8p20" (all-mep-isas) h-sint f-ivc2-8s20)
(dnop imm8p20 "Imm8p20" (all-mep-isas) h-uint f-ivc2-8u20)
-(dnop crop "$CRo Pn" (all-mep-isas) h-cr64 f-ivc2-5u23)
-(dnop crqp "$CRq Pn" (all-mep-isas) h-cr64 f-ivc2-5u13)
-(dnop crpp "$CRp Pn" (all-mep-isas) h-cr64 f-ivc2-5u18)
+(dnop crop "$CRo Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u23)
+(dnop crqp "$CRq Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u13)
+(dnop crpp "$CRp Pn" (all-mep-isas (CDATA CP_DATA_BUS_INT)) h-cr64 f-ivc2-5u18)
(dnop ivc-x-0-2 "filler" (all-mep-isas) h-uint f-ivc2-2u0)
(dnop ivc-x-0-3 "filler" (all-mep-isas) h-uint f-ivc2-3u0)
@@ -410,7 +438,7 @@
; 1111 000 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.b =croc,crqc,crpc (c3_1)
(dni cpadd3_b_C3 "cpadd3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST))
"cpadd3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -422,7 +450,7 @@
; 1111 001 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.h =croc,crqc,crpc (c3_1)
(dni cpadd3_h_C3 "cpadd3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST))
"cpadd3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -434,7 +462,7 @@
; 1111 010 ooooo 0111 00000 qqqqq ppppp 0 cpadd3.w =croc,crqc,crpc (c3_1)
(dni cpadd3_w_C3 "cpadd3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST))
"cpadd3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -446,7 +474,7 @@
; 1111 011 ooooo 0111 00000 qqqqq ppppp 0 cdadd3 =croc,crqc,crpc (c3_1)
(dni cdadd3_C3 "cdadd3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdadd3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdadd3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -458,7 +486,7 @@
; 1111 100 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.b =croc,crqc,crpc (c3_1)
(dni cpsub3_b_C3 "cpsub3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsub3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -470,7 +498,7 @@
; 1111 101 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.h =croc,crqc,crpc (c3_1)
(dni cpsub3_h_C3 "cpsub3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsub3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -482,7 +510,7 @@
; 1111 110 ooooo 0111 00000 qqqqq ppppp 0 cpsub3.w =croc,crqc,crpc (c3_1)
(dni cpsub3_w_C3 "cpsub3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsub3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -494,7 +522,7 @@
; 1111 111 ooooo 0111 00000 qqqqq ppppp 0 cdsub3 =croc,crqc,crpc (c3_1)
(dni cdsub3_C3 "cdsub3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsub3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsub3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x0) )
@@ -506,7 +534,7 @@
; 1111 000 ooooo 0111 00001 qqqqq ppppp 0 cpand3 =croc,crqc,crpc (c3_1)
(dni cpand3_C3 "cpand3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpand3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST))
"cpand3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
@@ -518,7 +546,7 @@
; 1111 001 ooooo 0111 00001 qqqqq ppppp 0 cpor3 =croc,crqc,crpc (c3_1)
(dni cpor3_C3 "cpor3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpor3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST))
"cpor3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
@@ -530,7 +558,7 @@
; 1111 010 ooooo 0111 00001 qqqqq ppppp 0 cpnor3 =croc,crqc,crpc (c3_1)
(dni cpnor3_C3 "cpnor3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnor3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST))
"cpnor3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
@@ -542,7 +570,7 @@
; 1111 011 ooooo 0111 00001 qqqqq ppppp 0 cpxor3 =croc,crqc,crpc (c3_1)
(dni cpxor3_C3 "cpxor3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpxor3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST))
"cpxor3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
@@ -554,7 +582,7 @@
; 1111 100 ooooo 0111 00001 qqqqq ppppp 0 cpsel =croc,crqc,crpc (c3_1)
(dni cpsel_C3 "cpsel $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsel"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpsel $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
@@ -566,7 +594,7 @@
; 1111 iii ooooo 0111 11101 qqqqq ppppp 0 cpfsftbi =croc,crqc,crpc,imm3p4 (c3_1)
(dni cpfsftbi_C3 "cpfsftbi $croc,$crqc,$crpc,imm3p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbi"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpfsftbi $croc,$crqc,$crpc,$imm3p4"
(+ MAJ_15 imm3p4 croc (f-sub4 7)
(f-ivc2-5u16 #x1d) crqc crpc (f-ivc2-1u31 #x0) )
@@ -578,7 +606,7 @@
; 1111 110 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs0 =croc,crqc,crpc (c3_1)
(dni cpfsftbs0_C3 "cpfsftbs0 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs0"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpfsftbs0 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
@@ -590,7 +618,7 @@
; 1111 111 ooooo 0111 00001 qqqqq ppppp 0 cpfsftbs1 =croc,crqc,crpc (c3_1)
(dni cpfsftbs1_C3 "cpfsftbs1 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpfsftbs1 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x0) )
@@ -602,7 +630,7 @@
; 1111 000 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.b =croc,crqc,crpc (c3_1)
(dni cpunpacku_b_C3 "cpunpacku.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST))
"cpunpacku.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
@@ -614,7 +642,7 @@
; 1111 001 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.h =croc,crqc,crpc (c3_1)
(dni cpunpacku_h_C3 "cpunpacku.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST))
"cpunpacku.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
@@ -626,7 +654,7 @@
; 1111 010 ooooo 0111 00010 qqqqq ppppp 0 cpunpacku.w =croc,crqc,crpc (c3_1)
(dni cpunpacku_w_C3 "cpunpacku.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST))
"cpunpacku.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
@@ -638,7 +666,7 @@
; 1111 100 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.b =croc,crqc,crpc (c3_1)
(dni cpunpackl_b_C3 "cpunpackl.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST))
"cpunpackl.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
@@ -650,7 +678,7 @@
; 1111 101 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.h =croc,crqc,crpc (c3_1)
(dni cpunpackl_h_C3 "cpunpackl.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST))
"cpunpackl.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
@@ -662,7 +690,7 @@
; 1111 110 ooooo 0111 00010 qqqqq ppppp 0 cpunpackl.w =croc,crqc,crpc (c3_1)
(dni cpunpackl_w_C3 "cpunpackl.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST))
"cpunpackl.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x2) crqc crpc (f-ivc2-1u31 #x0) )
@@ -674,7 +702,7 @@
; 1111 100 ooooo 0111 00011 qqqqq ppppp 0 cppacku.b =croc,crqc,crpc (c3_1)
(dni cppacku_b_C3 "cppacku.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacku_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST))
"cppacku.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) )
@@ -686,7 +714,7 @@
; 1111 101 ooooo 0111 00011 qqqqq ppppp 0 cppack.b =croc,crqc,crpc (c3_1)
(dni cppack_b_C3 "cppack.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST))
"cppack.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) )
@@ -698,7 +726,7 @@
; 1111 111 ooooo 0111 00011 qqqqq ppppp 0 cppack.h =croc,crqc,crpc (c3_1)
(dni cppack_h_C3 "cppack.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST))
"cppack.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
(f-ivc2-5u16 #x3) crqc crpc (f-ivc2-1u31 #x0) )
@@ -710,7 +738,7 @@
; 1111 000 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.b =croc,crqc,crpc (c3_1)
(dni cpsrl3_b_C3 "cpsrl3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsrl3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
@@ -722,7 +750,7 @@
; 1111 001 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.b =croc,crqc,crpc (c3_1)
(dni cpssrl3_b_C3 "cpssrl3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST))
"cpssrl3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
@@ -734,7 +762,7 @@
; 1111 010 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.h =croc,crqc,crpc (c3_1)
(dni cpsrl3_h_C3 "cpsrl3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsrl3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
@@ -746,7 +774,7 @@
; 1111 011 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.h =croc,crqc,crpc (c3_1)
(dni cpssrl3_h_C3 "cpssrl3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssrl3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
@@ -758,7 +786,7 @@
; 1111 100 ooooo 0111 00100 qqqqq ppppp 0 cpsrl3.w =croc,crqc,crpc (c3_1)
(dni cpsrl3_w_C3 "cpsrl3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsrl3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
@@ -770,7 +798,7 @@
; 1111 101 ooooo 0111 00100 qqqqq ppppp 0 cpssrl3.w =croc,crqc,crpc (c3_1)
(dni cpssrl3_w_C3 "cpssrl3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssrl3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
@@ -782,7 +810,7 @@
; 1111 110 ooooo 0111 00100 qqqqq ppppp 0 cdsrl3 =croc,crqc,crpc (c3_1)
(dni cdsrl3_C3 "cdsrl3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrl3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsrl3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x4) crqc crpc (f-ivc2-1u31 #x0) )
@@ -794,7 +822,7 @@
; 1111 000 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.b =croc,crqc,crpc (c3_1)
(dni cpsra3_b_C3 "cpsra3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsra3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
@@ -806,7 +834,7 @@
; 1111 001 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.b =croc,crqc,crpc (c3_1)
(dni cpssra3_b_C3 "cpssra3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST))
"cpssra3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
@@ -818,7 +846,7 @@
; 1111 010 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.h =croc,crqc,crpc (c3_1)
(dni cpsra3_h_C3 "cpsra3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsra3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
@@ -830,7 +858,7 @@
; 1111 011 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.h =croc,crqc,crpc (c3_1)
(dni cpssra3_h_C3 "cpssra3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssra3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
@@ -842,7 +870,7 @@
; 1111 100 ooooo 0111 00101 qqqqq ppppp 0 cpsra3.w =croc,crqc,crpc (c3_1)
(dni cpsra3_w_C3 "cpsra3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsra3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
@@ -854,7 +882,7 @@
; 1111 101 ooooo 0111 00101 qqqqq ppppp 0 cpssra3.w =croc,crqc,crpc (c3_1)
(dni cpssra3_w_C3 "cpssra3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssra3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
@@ -866,7 +894,7 @@
; 1111 110 ooooo 0111 00101 qqqqq ppppp 0 cdsra3 =croc,crqc,crpc (c3_1)
(dni cdsra3_C3 "cdsra3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsra3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsra3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x5) crqc crpc (f-ivc2-1u31 #x0) )
@@ -878,7 +906,7 @@
; 1111 000 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.b =croc,crqc,crpc (c3_1)
(dni cpsll3_b_C3 "cpsll3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsll3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
@@ -890,7 +918,7 @@
; 1111 001 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.b =croc,crqc,crpc (c3_1)
(dni cpssll3_b_C3 "cpssll3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST))
"cpssll3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
@@ -902,7 +930,7 @@
; 1111 010 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.h =croc,crqc,crpc (c3_1)
(dni cpsll3_h_C3 "cpsll3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsll3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
@@ -914,7 +942,7 @@
; 1111 011 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.h =croc,crqc,crpc (c3_1)
(dni cpssll3_h_C3 "cpssll3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssll3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
@@ -926,7 +954,7 @@
; 1111 100 ooooo 0111 00110 qqqqq ppppp 0 cpsll3.w =croc,crqc,crpc (c3_1)
(dni cpsll3_w_C3 "cpsll3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsll3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
@@ -938,7 +966,7 @@
; 1111 101 ooooo 0111 00110 qqqqq ppppp 0 cpssll3.w =croc,crqc,crpc (c3_1)
(dni cpssll3_w_C3 "cpssll3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssll3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
@@ -950,7 +978,7 @@
; 1111 110 ooooo 0111 00110 qqqqq ppppp 0 cdsll3 =croc,crqc,crpc (c3_1)
(dni cdsll3_C3 "cdsll3 $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsll3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsll3 $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x6) crqc crpc (f-ivc2-1u31 #x0) )
@@ -962,7 +990,7 @@
; 1111 010 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.h =croc,crqc,crpc (c3_1)
(dni cpsla3_h_C3 "cpsla3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsla3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) )
@@ -974,7 +1002,7 @@
; 1111 100 ooooo 0111 00111 qqqqq ppppp 0 cpsla3.w =croc,crqc,crpc (c3_1)
(dni cpsla3_w_C3 "cpsla3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsla3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x7) crqc crpc (f-ivc2-1u31 #x0) )
@@ -986,7 +1014,7 @@
; 1111 010 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.h =croc,crqc,crpc (c3_1)
(dni cpsadd3_h_C3 "cpsadd3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsadd3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
@@ -998,7 +1026,7 @@
; 1111 011 ooooo 0111 01000 qqqqq ppppp 0 cpsadd3.w =croc,crqc,crpc (c3_1)
(dni cpsadd3_w_C3 "cpsadd3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsadd3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1010,31 +1038,33 @@
; 1111 110 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.h =croc,crqc,crpc (c3_1)
(dni cpssub3_h_C3 "cpssub3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssub3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
(set croc (c-call DI "ivc2_cpssub3_h" pc crqc crpc)) )
()
)
; 1111 111 ooooo 0111 01000 qqqqq ppppp 0 cpssub3.w =croc,crqc,crpc (c3_1)
(dni cpssub3_w_C3 "cpssub3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssub3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
(f-ivc2-5u16 #x8) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
(set croc (c-call DI "ivc2_cpssub3_w" pc crqc crpc)) )
()
)
; 1111 000 ooooo 0111 01001 qqqqq ppppp 0 cpextuaddu3.b =croc,crqc,crpc (c3_1)
(dni cpextuaddu3_b_C3 "cpextuaddu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuaddu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextuaddu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1046,7 +1076,7 @@
; 1111 001 ooooo 0111 01001 qqqqq ppppp 0 cpextuadd3.b =croc,crqc,crpc (c3_1)
(dni cpextuadd3_b_C3 "cpextuadd3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuadd3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextuadd3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1058,7 +1088,7 @@
; 1111 010 ooooo 0111 01001 qqqqq ppppp 0 cpextladdu3.b =croc,crqc,crpc (c3_1)
(dni cpextladdu3_b_C3 "cpextladdu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladdu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextladdu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1070,7 +1100,7 @@
; 1111 011 ooooo 0111 01001 qqqqq ppppp 0 cpextladd3.b =croc,crqc,crpc (c3_1)
(dni cpextladd3_b_C3 "cpextladd3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladd3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextladd3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1082,7 +1112,7 @@
; 1111 100 ooooo 0111 01001 qqqqq ppppp 0 cpextusubu3.b =croc,crqc,crpc (c3_1)
(dni cpextusubu3_b_C3 "cpextusubu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusubu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextusubu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1094,7 +1124,7 @@
; 1111 101 ooooo 0111 01001 qqqqq ppppp 0 cpextusub3.b =croc,crqc,crpc (c3_1)
(dni cpextusub3_b_C3 "cpextusub3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusub3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextusub3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1106,7 +1136,7 @@
; 1111 110 ooooo 0111 01001 qqqqq ppppp 0 cpextlsubu3.b =croc,crqc,crpc (c3_1)
(dni cpextlsubu3_b_C3 "cpextlsubu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsubu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextlsubu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1118,7 +1148,7 @@
; 1111 111 ooooo 0111 01001 qqqqq ppppp 0 cpextlsub3.b =croc,crqc,crpc (c3_1)
(dni cpextlsub3_b_C3 "cpextlsub3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsub3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextlsub3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
(f-ivc2-5u16 #x9) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1130,7 +1160,7 @@
; 1111 000 ooooo 0111 01010 qqqqq ppppp 0 cpaveu3.b =croc,crqc,crpc (c3_1)
(dni cpaveu3_b_C3 "cpaveu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaveu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpaveu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1142,7 +1172,7 @@
; 1111 001 ooooo 0111 01010 qqqqq ppppp 0 cpave3.b =croc,crqc,crpc (c3_1)
(dni cpave3_b_C3 "cpave3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST))
"cpave3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1154,7 +1184,7 @@
; 1111 010 ooooo 0111 01010 qqqqq ppppp 0 cpave3.h =croc,crqc,crpc (c3_1)
(dni cpave3_h_C3 "cpave3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST))
"cpave3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1166,7 +1196,7 @@
; 1111 011 ooooo 0111 01010 qqqqq ppppp 0 cpave3.w =croc,crqc,crpc (c3_1)
(dni cpave3_w_C3 "cpave3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST))
"cpave3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1178,7 +1208,7 @@
; 1111 100 ooooo 0111 01010 qqqqq ppppp 0 cpaddsru3.b =croc,crqc,crpc (c3_1)
(dni cpaddsru3_b_C3 "cpaddsru3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsru3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST))
"cpaddsru3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1190,7 +1220,7 @@
; 1111 101 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.b =croc,crqc,crpc (c3_1)
(dni cpaddsr3_b_C3 "cpaddsr3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST))
"cpaddsr3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1202,7 +1232,7 @@
; 1111 110 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.h =croc,crqc,crpc (c3_1)
(dni cpaddsr3_h_C3 "cpaddsr3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST))
"cpaddsr3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x6) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1214,7 +1244,7 @@
; 1111 111 ooooo 0111 01010 qqqqq ppppp 0 cpaddsr3.w =croc,crqc,crpc (c3_1)
(dni cpaddsr3_w_C3 "cpaddsr3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST))
"cpaddsr3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x7) croc (f-sub4 7)
(f-ivc2-5u16 #xa) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1226,7 +1256,7 @@
; 1111 000 ooooo 0111 01011 qqqqq ppppp 0 cpabsu3.b =croc,crqc,crpc (c3_1)
(dni cpabsu3_b_C3 "cpabsu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpabsu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1238,7 +1268,7 @@
; 1111 001 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.b =croc,crqc,crpc (c3_1)
(dni cpabs3_b_C3 "cpabs3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST))
"cpabs3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1250,7 +1280,7 @@
; 1111 010 ooooo 0111 01011 qqqqq ppppp 0 cpabs3.h =croc,crqc,crpc (c3_1)
(dni cpabs3_h_C3 "cpabs3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST))
"cpabs3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) croc (f-sub4 7)
(f-ivc2-5u16 #xb) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1262,7 +1292,7 @@
; 1111 000 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.b =croc,crqc,crpc (c3_1)
(dni cpmaxu3_b_C3 "cpmaxu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpmaxu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1274,7 +1304,7 @@
; 1111 001 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.b =croc,crqc,crpc (c3_1)
(dni cpmax3_b_C3 "cpmax3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST))
"cpmax3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1286,7 +1316,7 @@
; 1111 011 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.h =croc,crqc,crpc (c3_1)
(dni cpmax3_h_C3 "cpmax3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST))
"cpmax3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1298,7 +1328,7 @@
; 1111 100 ooooo 0111 01100 qqqqq ppppp 0 cpmaxu3.w =croc,crqc,crpc (c3_1)
(dni cpmaxu3_w_C3 "cpmaxu3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST))
"cpmaxu3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1310,7 +1340,7 @@
; 1111 101 ooooo 0111 01100 qqqqq ppppp 0 cpmax3.w =croc,crqc,crpc (c3_1)
(dni cpmax3_w_C3 "cpmax3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST))
"cpmax3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #xc) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1322,7 +1352,7 @@
; 1111 000 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.b =croc,crqc,crpc (c3_1)
(dni cpminu3_b_C3 "cpminu3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpminu3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1334,7 +1364,7 @@
; 1111 001 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.b =croc,crqc,crpc (c3_1)
(dni cpmin3_b_C3 "cpmin3.b $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST))
"cpmin3.b $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) croc (f-sub4 7)
(f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1346,7 +1376,7 @@
; 1111 011 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.h =croc,crqc,crpc (c3_1)
(dni cpmin3_h_C3 "cpmin3.h $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST))
"cpmin3.h $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) croc (f-sub4 7)
(f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1358,7 +1388,7 @@
; 1111 100 ooooo 0111 01101 qqqqq ppppp 0 cpminu3.w =croc,crqc,crpc (c3_1)
(dni cpminu3_w_C3 "cpminu3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST))
"cpminu3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x4) croc (f-sub4 7)
(f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1370,7 +1400,7 @@
; 1111 101 ooooo 0111 01101 qqqqq ppppp 0 cpmin3.w =croc,crqc,crpc (c3_1)
(dni cpmin3_w_C3 "cpmin3.w $croc,$crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST))
"cpmin3.w $croc,$crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x5) croc (f-sub4 7)
(f-ivc2-5u16 #xd) crqc crpc (f-ivc2-1u31 #x0) )
@@ -1382,7 +1412,7 @@
; 1111 000 ooooo 0111 10000 00000 00000 0 cpmovfrcsar0 =croc (c3_1)
(dni cpmovfrcsar0_C3 "cpmovfrcsar0 $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar0"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmovfrcsar0 $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) )
@@ -1394,7 +1424,7 @@
; 1111 000 ooooo 0111 10000 00000 01111 0 cpmovfrcsar1 =croc (c3_1)
(dni cpmovfrcsar1_C3 "cpmovfrcsar1 $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar1"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmovfrcsar1 $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) )
@@ -1406,7 +1436,7 @@
; 1111 000 ooooo 0111 10000 00000 00001 0 cpmovfrcc =croc (c3_1)
(dni cpmovfrcc_C3 "cpmovfrcc $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcc"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmovfrcc $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x10) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) )
@@ -1454,7 +1484,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00000 0 cpmov =croc,crqc (c3_1)
(dni cpmov_C3 "cpmov $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmov"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmov $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) )
@@ -1466,7 +1496,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00001 0 cpabsz.b =croc,crqc (c3_1)
(dni cpabsz_b_C3 "cpabsz.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST))
"cpabsz.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1) (f-ivc2-1u31 #x0) )
@@ -1478,7 +1508,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00010 0 cpabsz.h =croc,crqc (c3_1)
(dni cpabsz_h_C3 "cpabsz.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST))
"cpabsz.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) )
@@ -1490,7 +1520,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00011 0 cpabsz.w =croc,crqc (c3_1)
(dni cpabsz_w_C3 "cpabsz.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST))
"cpabsz.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) )
@@ -1502,7 +1532,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00100 0 cpldz.h =croc,crqc (c3_1)
(dni cpldz_h_C3 "cpldz.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST))
"cpldz.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) )
@@ -1514,7 +1544,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00101 0 cpldz.w =croc,crqc (c3_1)
(dni cpldz_w_C3 "cpldz.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST))
"cpldz.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) )
@@ -1526,7 +1556,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00110 0 cpnorm.h =croc,crqc (c3_1)
(dni cpnorm_h_C3 "cpnorm.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST))
"cpnorm.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) )
@@ -1538,7 +1568,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 00111 0 cpnorm.w =croc,crqc (c3_1)
(dni cpnorm_w_C3 "cpnorm.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST))
"cpnorm.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) )
@@ -1550,7 +1580,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 01000 0 cphaddu.b =croc,crqc (c3_1)
(dni cphaddu_b_C3 "cphaddu.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphaddu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST))
"cphaddu.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x8) (f-ivc2-1u31 #x0) )
@@ -1562,7 +1592,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 01001 0 cphadd.b =croc,crqc (c3_1)
(dni cphadd_b_C3 "cphadd.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST))
"cphadd.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x9) (f-ivc2-1u31 #x0) )
@@ -1574,7 +1604,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 01010 0 cphadd.h =croc,crqc (c3_1)
(dni cphadd_h_C3 "cphadd.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST))
"cphadd.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xa) (f-ivc2-1u31 #x0) )
@@ -1586,7 +1616,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 01011 0 cphadd.w =croc,crqc (c3_1)
(dni cphadd_w_C3 "cphadd.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST))
"cphadd.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xb) (f-ivc2-1u31 #x0) )
@@ -1598,19 +1628,19 @@
; 1111 000 ooooo 0111 10001 qqqqq 01100 0 cpccadd.b +crqc (c3_1)
(dni cpccadd_b_C3 "cpccadd.b $crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpccadd_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY))
"cpccadd.b $crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xc) (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
- (c-call "ivc2_cpccadd_b" pc (index-of crqc)) )
+ (set crqc (c-call DI "ivc2_cpccadd_b" pc crqc)) )
()
)
; 1111 000 ooooo 0111 10001 qqqqq 01101 0 cpbcast.b =croc,crqc (c3_1)
(dni cpbcast_b_C3 "cpbcast.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST))
"cpbcast.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xd) (f-ivc2-1u31 #x0) )
@@ -1622,7 +1652,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 01110 0 cpbcast.h =croc,crqc (c3_1)
(dni cpbcast_h_C3 "cpbcast.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST))
"cpbcast.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xe) (f-ivc2-1u31 #x0) )
@@ -1634,7 +1664,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 01111 0 cpbcast.w =croc,crqc (c3_1)
(dni cpbcast_w_C3 "cpbcast.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST))
"cpbcast.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #xf) (f-ivc2-1u31 #x0) )
@@ -1646,7 +1676,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10000 0 cpextuu.b =croc,crqc (c3_1)
(dni cpextuu_b_C3 "cpextuu.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST))
"cpextuu.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x0) )
@@ -1658,7 +1688,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10001 0 cpextu.b =croc,crqc (c3_1)
(dni cpextu_b_C3 "cpextu.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST))
"cpextu.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x0) )
@@ -1670,7 +1700,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10010 0 cpextuu.h =croc,crqc (c3_1)
(dni cpextuu_h_C3 "cpextuu.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST))
"cpextuu.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x0) )
@@ -1682,7 +1712,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10011 0 cpextu.h =croc,crqc (c3_1)
(dni cpextu_h_C3 "cpextu.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST))
"cpextu.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x0) )
@@ -1694,7 +1724,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10100 0 cpextlu.b =croc,crqc (c3_1)
(dni cpextlu_b_C3 "cpextlu.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST))
"cpextlu.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x0) )
@@ -1706,7 +1736,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10101 0 cpextl.b =croc,crqc (c3_1)
(dni cpextl_b_C3 "cpextl.b $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST))
"cpextl.b $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x0) )
@@ -1718,7 +1748,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10110 0 cpextlu.h =croc,crqc (c3_1)
(dni cpextlu_h_C3 "cpextlu.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST))
"cpextlu.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x0) )
@@ -1730,7 +1760,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 10111 0 cpextl.h =croc,crqc (c3_1)
(dni cpextl_h_C3 "cpextl.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST))
"cpextl.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x0) )
@@ -1742,7 +1772,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11000 0 cpcastub.h =croc,crqc (c3_1)
(dni cpcastub_h_C3 "cpcastub.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST))
"cpcastub.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x18) (f-ivc2-1u31 #x0) )
@@ -1754,7 +1784,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11001 0 cpcastb.h =croc,crqc (c3_1)
(dni cpcastb_h_C3 "cpcastb.h $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST))
"cpcastb.h $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x19) (f-ivc2-1u31 #x0) )
@@ -1766,7 +1796,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11100 0 cpcastub.w =croc,crqc (c3_1)
(dni cpcastub_w_C3 "cpcastub.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST))
"cpcastub.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1c) (f-ivc2-1u31 #x0) )
@@ -1778,7 +1808,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11101 0 cpcastb.w =croc,crqc (c3_1)
(dni cpcastb_w_C3 "cpcastb.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST))
"cpcastb.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1d) (f-ivc2-1u31 #x0) )
@@ -1790,7 +1820,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11110 0 cpcastuh.w =croc,crqc (c3_1)
(dni cpcastuh_w_C3 "cpcastuh.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastuh_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST))
"cpcastuh.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1e) (f-ivc2-1u31 #x0) )
@@ -1802,7 +1832,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11111 0 cpcasth.w =croc,crqc (c3_1)
(dni cpcasth_w_C3 "cpcasth.w $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcasth_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST))
"cpcasth.w $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1f) (f-ivc2-1u31 #x0) )
@@ -1814,7 +1844,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11010 0 cdcastuw =croc,crqc (c3_1)
(dni cdcastuw_C3 "cdcastuw $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastuw"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdcastuw $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1a) (f-ivc2-1u31 #x0) )
@@ -1826,7 +1856,7 @@
; 1111 000 ooooo 0111 10001 qqqqq 11011 0 cdcastw =croc,crqc (c3_1)
(dni cdcastw_C3 "cdcastw $croc,$crqc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastw"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdcastw $croc,$crqc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x11) crqc (f-ivc2-5u26 #x1b) (f-ivc2-1u31 #x0) )
@@ -1838,595 +1868,644 @@
; 1111 0000 0000 0111 10010 qqqqq ppppp 0 cpcmpeqz.b crqc,crpc (c3_1)
(dni cpcmpeqz_b_C3 "cpcmpeqz.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeqz_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI))
"cpcmpeqz.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeqz_b" pc crqc crpc) )
()
)
; 1111 0000 0001 0111 10010 qqqqq ppppp 0 cpcmpeq.b crqc,crpc (c3_1)
(dni cpcmpeq_b_C3 "cpcmpeq.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI))
"cpcmpeq.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeq_b" pc crqc crpc) )
()
)
; 1111 0000 0011 0111 10010 qqqqq ppppp 0 cpcmpeq.h crqc,crpc (c3_1)
(dni cpcmpeq_h_C3 "cpcmpeq.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI))
"cpcmpeq.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeq_h" pc crqc crpc) )
()
)
; 1111 0000 0101 0111 10010 qqqqq ppppp 0 cpcmpeq.w crqc,crpc (c3_1)
(dni cpcmpeq_w_C3 "cpcmpeq.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI))
"cpcmpeq.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeq_w" pc crqc crpc) )
()
)
; 1111 0000 1001 0111 10010 qqqqq ppppp 0 cpcmpne.b crqc,crpc (c3_1)
(dni cpcmpne_b_C3 "cpcmpne.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI))
"cpcmpne.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpne_b" pc crqc crpc) )
()
)
; 1111 0000 1011 0111 10010 qqqqq ppppp 0 cpcmpne.h crqc,crpc (c3_1)
(dni cpcmpne_h_C3 "cpcmpne.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI))
"cpcmpne.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpne_h" pc crqc crpc) )
()
)
; 1111 0000 1101 0111 10010 qqqqq ppppp 0 cpcmpne.w crqc,crpc (c3_1)
(dni cpcmpne_w_C3 "cpcmpne.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI))
"cpcmpne.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpne_w" pc crqc crpc) )
()
)
; 1111 0001 0000 0111 10010 qqqqq ppppp 0 cpcmpgtu.b crqc,crpc (c3_1)
(dni cpcmpgtu_b_C3 "cpcmpgtu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI))
"cpcmpgtu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgtu_b" pc crqc crpc) )
()
)
; 1111 0001 0001 0111 10010 qqqqq ppppp 0 cpcmpgt.b crqc,crpc (c3_1)
(dni cpcmpgt_b_C3 "cpcmpgt.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI))
"cpcmpgt.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgt_b" pc crqc crpc) )
()
)
; 1111 0001 0011 0111 10010 qqqqq ppppp 0 cpcmpgt.h crqc,crpc (c3_1)
(dni cpcmpgt_h_C3 "cpcmpgt.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI))
"cpcmpgt.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgt_h" pc crqc crpc) )
()
)
; 1111 0001 0100 0111 10010 qqqqq ppppp 0 cpcmpgtu.w crqc,crpc (c3_1)
(dni cpcmpgtu_w_C3 "cpcmpgtu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI))
"cpcmpgtu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgtu_w" pc crqc crpc) )
()
)
; 1111 0001 0101 0111 10010 qqqqq ppppp 0 cpcmpgt.w crqc,crpc (c3_1)
(dni cpcmpgt_w_C3 "cpcmpgt.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI))
"cpcmpgt.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgt_w" pc crqc crpc) )
()
)
; 1111 0001 1000 0111 10010 qqqqq ppppp 0 cpcmpgeu.b crqc,crpc (c3_1)
(dni cpcmpgeu_b_C3 "cpcmpgeu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI))
"cpcmpgeu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x18) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgeu_b" pc crqc crpc) )
()
)
; 1111 0001 1001 0111 10010 qqqqq ppppp 0 cpcmpge.b crqc,crpc (c3_1)
(dni cpcmpge_b_C3 "cpcmpge.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI))
"cpcmpge.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x19) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpge_b" pc crqc crpc) )
()
)
; 1111 0001 1011 0111 10010 qqqqq ppppp 0 cpcmpge.h crqc,crpc (c3_1)
(dni cpcmpge_h_C3 "cpcmpge.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI))
"cpcmpge.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpge_h" pc crqc crpc) )
()
)
; 1111 0001 1100 0111 10010 qqqqq ppppp 0 cpcmpgeu.w crqc,crpc (c3_1)
(dni cpcmpgeu_w_C3 "cpcmpgeu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI))
"cpcmpgeu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgeu_w" pc crqc crpc) )
()
)
; 1111 0001 1101 0111 10010 qqqqq ppppp 0 cpcmpge.w crqc,crpc (c3_1)
(dni cpcmpge_w_C3 "cpcmpge.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI))
"cpcmpge.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpge_w" pc crqc crpc) )
()
)
; 1111 0010 0001 0111 10010 qqqqq ppppp 0 cpacmpeq.b crqc,crpc (c3_1)
(dni cpacmpeq_b_C3 "cpacmpeq.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI))
"cpacmpeq.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpeq_b" pc crqc crpc) )
()
)
; 1111 0010 0011 0111 10010 qqqqq ppppp 0 cpacmpeq.h crqc,crpc (c3_1)
(dni cpacmpeq_h_C3 "cpacmpeq.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI))
"cpacmpeq.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpeq_h" pc crqc crpc) )
()
)
; 1111 0010 0101 0111 10010 qqqqq ppppp 0 cpacmpeq.w crqc,crpc (c3_1)
(dni cpacmpeq_w_C3 "cpacmpeq.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI))
"cpacmpeq.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpeq_w" pc crqc crpc) )
()
)
; 1111 0010 1001 0111 10010 qqqqq ppppp 0 cpacmpne.b crqc,crpc (c3_1)
(dni cpacmpne_b_C3 "cpacmpne.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI))
"cpacmpne.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpne_b" pc crqc crpc) )
()
)
; 1111 0010 1011 0111 10010 qqqqq ppppp 0 cpacmpne.h crqc,crpc (c3_1)
(dni cpacmpne_h_C3 "cpacmpne.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI))
"cpacmpne.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpne_h" pc crqc crpc) )
()
)
; 1111 0010 1101 0111 10010 qqqqq ppppp 0 cpacmpne.w crqc,crpc (c3_1)
(dni cpacmpne_w_C3 "cpacmpne.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI))
"cpacmpne.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpne_w" pc crqc crpc) )
()
)
; 1111 0011 0000 0111 10010 qqqqq ppppp 0 cpacmpgtu.b crqc,crpc (c3_1)
(dni cpacmpgtu_b_C3 "cpacmpgtu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI))
"cpacmpgtu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpgtu_b" pc crqc crpc) )
()
)
; 1111 0011 0001 0111 10010 qqqqq ppppp 0 cpacmpgt.b crqc,crpc (c3_1)
(dni cpacmpgt_b_C3 "cpacmpgt.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI))
"cpacmpgt.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpgt_b" pc crqc crpc) )
()
)
; 1111 0011 0011 0111 10010 qqqqq ppppp 0 cpacmpgt.h crqc,crpc (c3_1)
(dni cpacmpgt_h_C3 "cpacmpgt.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI))
"cpacmpgt.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpgt_h" pc crqc crpc) )
()
)
; 1111 0011 0100 0111 10010 qqqqq ppppp 0 cpacmpgtu.w crqc,crpc (c3_1)
(dni cpacmpgtu_w_C3 "cpacmpgtu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI))
"cpacmpgtu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpgtu_w" pc crqc crpc) )
()
)
; 1111 0011 0101 0111 10010 qqqqq ppppp 0 cpacmpgt.w crqc,crpc (c3_1)
(dni cpacmpgt_w_C3 "cpacmpgt.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI))
"cpacmpgt.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpgt_w" pc crqc crpc) )
()
)
; 1111 0011 1000 0111 10010 qqqqq ppppp 0 cpacmpgeu.b crqc,crpc (c3_1)
(dni cpacmpgeu_b_C3 "cpacmpgeu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI))
"cpacmpgeu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x18) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpgeu_b" pc crqc crpc) )
()
)
; 1111 0011 1001 0111 10010 qqqqq ppppp 0 cpacmpge.b crqc,crpc (c3_1)
(dni cpacmpge_b_C3 "cpacmpge.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI))
"cpacmpge.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x19) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpge_b" pc crqc crpc) )
()
)
; 1111 0011 1011 0111 10010 qqqqq ppppp 0 cpacmpge.h crqc,crpc (c3_1)
(dni cpacmpge_h_C3 "cpacmpge.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI))
"cpacmpge.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpge_h" pc crqc crpc) )
()
)
; 1111 0011 1100 0111 10010 qqqqq ppppp 0 cpacmpgeu.w crqc,crpc (c3_1)
(dni cpacmpgeu_w_C3 "cpacmpgeu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI))
"cpacmpgeu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1c) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpgeu_w" pc crqc crpc) )
()
)
; 1111 0011 1101 0111 10010 qqqqq ppppp 0 cpacmpge.w crqc,crpc (c3_1)
(dni cpacmpge_w_C3 "cpacmpge.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI))
"cpacmpge.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1d) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpacmpge_w" pc crqc crpc) )
()
)
; 1111 0100 0001 0111 10010 qqqqq ppppp 0 cpocmpeq.b crqc,crpc (c3_1)
(dni cpocmpeq_b_C3 "cpocmpeq.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI))
"cpocmpeq.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpeq_b" pc crqc crpc) )
()
)
; 1111 0100 0011 0111 10010 qqqqq ppppp 0 cpocmpeq.h crqc,crpc (c3_1)
(dni cpocmpeq_h_C3 "cpocmpeq.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI))
"cpocmpeq.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpeq_h" pc crqc crpc) )
()
)
; 1111 0100 0101 0111 10010 qqqqq ppppp 0 cpocmpeq.w crqc,crpc (c3_1)
(dni cpocmpeq_w_C3 "cpocmpeq.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI))
"cpocmpeq.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpeq_w" pc crqc crpc) )
()
)
; 1111 0100 1001 0111 10010 qqqqq ppppp 0 cpocmpne.b crqc,crpc (c3_1)
(dni cpocmpne_b_C3 "cpocmpne.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI))
"cpocmpne.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpne_b" pc crqc crpc) )
()
)
; 1111 0100 1011 0111 10010 qqqqq ppppp 0 cpocmpne.h crqc,crpc (c3_1)
(dni cpocmpne_h_C3 "cpocmpne.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI))
"cpocmpne.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpne_h" pc crqc crpc) )
()
)
; 1111 0100 1101 0111 10010 qqqqq ppppp 0 cpocmpne.w crqc,crpc (c3_1)
(dni cpocmpne_w_C3 "cpocmpne.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI))
"cpocmpne.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpne_w" pc crqc crpc) )
()
)
; 1111 0101 0000 0111 10010 qqqqq ppppp 0 cpocmpgtu.b crqc,crpc (c3_1)
(dni cpocmpgtu_b_C3 "cpocmpgtu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI))
"cpocmpgtu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpgtu_b" pc crqc crpc) )
()
)
; 1111 0101 0001 0111 10010 qqqqq ppppp 0 cpocmpgt.b crqc,crpc (c3_1)
(dni cpocmpgt_b_C3 "cpocmpgt.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI))
"cpocmpgt.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpgt_b" pc crqc crpc) )
()
)
; 1111 0101 0011 0111 10010 qqqqq ppppp 0 cpocmpgt.h crqc,crpc (c3_1)
(dni cpocmpgt_h_C3 "cpocmpgt.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI))
"cpocmpgt.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpgt_h" pc crqc crpc) )
()
)
; 1111 0101 0100 0111 10010 qqqqq ppppp 0 cpocmpgtu.w crqc,crpc (c3_1)
(dni cpocmpgtu_w_C3 "cpocmpgtu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI))
"cpocmpgtu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpgtu_w" pc crqc crpc) )
()
)
; 1111 0101 0101 0111 10010 qqqqq ppppp 0 cpocmpgt.w crqc,crpc (c3_1)
(dni cpocmpgt_w_C3 "cpocmpgt.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI))
"cpocmpgt.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpgt_w" pc crqc crpc) )
()
)
; 1111 0101 1000 0111 10010 qqqqq ppppp 0 cpocmpgeu.b crqc,crpc (c3_1)
(dni cpocmpgeu_b_C3 "cpocmpgeu.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI))
"cpocmpgeu.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x18) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpgeu_b" pc crqc crpc) )
()
)
; 1111 0101 1001 0111 10010 qqqqq ppppp 0 cpocmpge.b crqc,crpc (c3_1)
(dni cpocmpge_b_C3 "cpocmpge.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI))
"cpocmpge.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x19) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpge_b" pc crqc crpc) )
()
)
; 1111 0101 1011 0111 10010 qqqqq ppppp 0 cpocmpge.h crqc,crpc (c3_1)
(dni cpocmpge_h_C3 "cpocmpge.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI))
"cpocmpge.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpge_h" pc crqc crpc) )
()
)
; 1111 0101 1100 0111 10010 qqqqq ppppp 0 cpocmpgeu.w crqc,crpc (c3_1)
(dni cpocmpgeu_w_C3 "cpocmpgeu.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI))
"cpocmpgeu.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1c) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpgeu_w" pc crqc crpc) )
()
)
; 1111 0101 1101 0111 10010 qqqqq ppppp 0 cpocmpge.w crqc,crpc (c3_1)
(dni cpocmpge_w_C3 "cpocmpge.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI))
"cpocmpge.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #x1d) (f-sub4 7)
(f-ivc2-5u16 #x12) crqc crpc (f-ivc2-1u31 #x0) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpocmpge_w" pc crqc crpc) )
()
)
; 1111 00xx xiii 0111 10100 qqqqq ppppp 0 cpsrli3.b =crqc,crpc,imm3p9 (c3_imm)
(dni cpsrli3_b_C3 "cpsrli3.b $crqc,$crpc,imm3p9 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsrli3.b $crqc,$crpc,$imm3p9"
(+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7)
(f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2438,7 +2517,7 @@
; 1111 01xx iiii 0111 10100 qqqqq ppppp 0 cpsrli3.h =crqc,crpc,imm4p8 (c3_imm)
(dni cpsrli3_h_C3 "cpsrli3.h $crqc,$crpc,imm4p8 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsrli3.h $crqc,$crpc,$imm4p8"
(+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
(f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2450,7 +2529,7 @@
; 1111 10xi iiii 0111 10100 qqqqq ppppp 0 cpsrli3.w =crqc,crpc,imm5p7 (c3_imm)
(dni cpsrli3_w_C3 "cpsrli3.w $crqc,$crpc,imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsrli3.w $crqc,$crpc,$imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2462,7 +2541,7 @@
; 1111 11ii iiii 0111 10100 qqqqq ppppp 0 cdsrli3 =crqc,crpc,imm6p6 (c3_imm)
(dni cdsrli3_C3 "cdsrli3 $crqc,$crpc,imm6p6 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrli3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsrli3 $crqc,$crpc,$imm6p6"
(+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
(f-ivc2-5u16 #x14) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2474,7 +2553,7 @@
; 1111 00xx xiii 0111 10101 qqqqq ppppp 0 cpsrai3.b =crqc,crpc,imm3p9 (c3_imm)
(dni cpsrai3_b_C3 "cpsrai3.b $crqc,$crpc,imm3p9 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsrai3.b $crqc,$crpc,$imm3p9"
(+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7)
(f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2486,7 +2565,7 @@
; 1111 01xx iiii 0111 10101 qqqqq ppppp 0 cpsrai3.h =crqc,crpc,imm4p8 (c3_imm)
(dni cpsrai3_h_C3 "cpsrai3.h $crqc,$crpc,imm4p8 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsrai3.h $crqc,$crpc,$imm4p8"
(+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
(f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2498,7 +2577,7 @@
; 1111 10xi iiii 0111 10101 qqqqq ppppp 0 cpsrai3.w =crqc,crpc,imm5p7 (c3_imm)
(dni cpsrai3_w_C3 "cpsrai3.w $crqc,$crpc,imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsrai3.w $crqc,$crpc,$imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2510,7 +2589,7 @@
; 1111 11ii iiii 0111 10101 qqqqq ppppp 0 cdsrai3 =crqc,crpc,imm6p6 (c3_imm)
(dni cdsrai3_C3 "cdsrai3 $crqc,$crpc,imm6p6 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrai3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsrai3 $crqc,$crpc,$imm6p6"
(+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
(f-ivc2-5u16 #x15) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2522,7 +2601,7 @@
; 1111 00xx xiii 0111 10110 qqqqq ppppp 0 cpslli3.b =crqc,crpc,imm3p9 (c3_imm)
(dni cpslli3_b_C3 "cpslli3.b $crqc,$crpc,imm3p9 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST))
"cpslli3.b $crqc,$crpc,$imm3p9"
(+ MAJ_15 ivc-x-6-3 (f-ivc2-2u4 #x0) imm3p9 (f-sub4 7)
(f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2534,7 +2613,7 @@
; 1111 01xx iiii 0111 10110 qqqqq ppppp 0 cpslli3.h =crqc,crpc,imm4p8 (c3_imm)
(dni cpslli3_h_C3 "cpslli3.h $crqc,$crpc,imm4p8 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST))
"cpslli3.h $crqc,$crpc,$imm4p8"
(+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
(f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2546,7 +2625,7 @@
; 1111 10xi iiii 0111 10110 qqqqq ppppp 0 cpslli3.w =crqc,crpc,imm5p7 (c3_imm)
(dni cpslli3_w_C3 "cpslli3.w $crqc,$crpc,imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST))
"cpslli3.w $crqc,$crpc,$imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2558,7 +2637,7 @@
; 1111 11ii iiii 0111 10110 qqqqq ppppp 0 cdslli3 =crqc,crpc,imm6p6 (c3_imm)
(dni cdslli3_C3 "cdslli3 $crqc,$crpc,imm6p6 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdslli3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdslli3 $crqc,$crpc,$imm6p6"
(+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
(f-ivc2-5u16 #x16) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2570,7 +2649,7 @@
; 1111 01xx iiii 0111 10111 qqqqq ppppp 0 cpslai3.h =crqc,crpc,imm4p8 (c3_imm)
(dni cpslai3_h_C3 "cpslai3.h $crqc,$crpc,imm4p8 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST))
"cpslai3.h $crqc,$crpc,$imm4p8"
(+ MAJ_15 ivc-x-6-2 (f-ivc2-2u4 #x1) imm4p8 (f-sub4 7)
(f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2582,7 +2661,7 @@
; 1111 10xi iiii 0111 10111 qqqqq ppppp 0 cpslai3.w =crqc,crpc,imm5p7 (c3_imm)
(dni cpslai3_w_C3 "cpslai3.w $crqc,$crpc,imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST))
"cpslai3.w $crqc,$crpc,$imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x2) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x17) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2594,7 +2673,7 @@
; 1111 00xi iiii 0111 11000 qqqqq ppppp 0 cpclipiu3.w =crqc,crpc,imm5p7 (c3_imm)
(dni cpclipiu3_w_C3 "cpclipiu3.w $crqc,$crpc,imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipiu3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST))
"cpclipiu3.w $crqc,$crpc,$imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x0) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2606,7 +2685,7 @@
; 1111 01xi iiii 0111 11000 qqqqq ppppp 0 cpclipi3.w =crqc,crpc,imm5p7 (c3_imm)
(dni cpclipi3_w_C3 "cpclipi3.w $crqc,$crpc,imm5p7 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipi3_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST))
"cpclipi3.w $crqc,$crpc,$imm5p7"
(+ MAJ_15 ivc-x-6-1 (f-ivc2-2u4 #x1) imm5p7 (f-sub4 7)
(f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2618,7 +2697,7 @@
; 1111 10ii iiii 0111 11000 qqqqq ppppp 0 cdclipiu3 =crqc,crpc,imm6p6 (c3_imm)
(dni cdclipiu3_C3 "cdclipiu3 $crqc,$crpc,imm6p6 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipiu3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdclipiu3 $crqc,$crpc,$imm6p6"
(+ MAJ_15 (f-ivc2-2u4 #x2) imm6p6 (f-sub4 7)
(f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2630,7 +2709,7 @@
; 1111 11ii iiii 0111 11000 qqqqq ppppp 0 cdclipi3 =crqc,crpc,imm6p6 (c3_imm)
(dni cdclipi3_C3 "cdclipi3 $crqc,$crpc,imm6p6 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipi3"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdclipi3 $crqc,$crpc,$imm6p6"
(+ MAJ_15 (f-ivc2-2u4 #x3) imm6p6 (f-sub4 7)
(f-ivc2-5u16 #x18) crqc crpc (f-ivc2-1u31 #x0) )
@@ -2642,7 +2721,7 @@
; 1111 iiii iiii 0111 11001 qqqqq 00000 0 cpmovi.b =crqc,simm8p4 (c3_imm)
(dni cpmovi_b_C3 "cpmovi.b $crqc,simm8p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST))
"cpmovi.b $crqc,$simm8p4"
(+ MAJ_15 simm8p4 (f-sub4 7)
(f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x0) )
@@ -2654,7 +2733,7 @@
; 1111 iiii iiii 0111 11001 qqqqq 00010 0 cpmoviu.h =crqc,imm8p4 (c3_imm)
(dni cpmoviu_h_C3 "cpmoviu.h $crqc,imm8p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_h") (CPTYPE V4UHI) (CRET FIRST))
"cpmoviu.h $crqc,$imm8p4"
(+ MAJ_15 imm8p4 (f-sub4 7)
(f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x0) )
@@ -2666,7 +2745,7 @@
; 1111 iiii iiii 0111 11001 qqqqq 00011 0 cpmovi.h =crqc,simm8p4 (c3_imm)
(dni cpmovi_h_C3 "cpmovi.h $crqc,simm8p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovi.h $crqc,$simm8p4"
(+ MAJ_15 simm8p4 (f-sub4 7)
(f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x0) )
@@ -2678,7 +2757,7 @@
; 1111 iiii iiii 0111 11001 qqqqq 00100 0 cpmoviu.w =crqc,imm8p4 (c3_imm)
(dni cpmoviu_w_C3 "cpmoviu.w $crqc,imm8p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST))
"cpmoviu.w $crqc,$imm8p4"
(+ MAJ_15 imm8p4 (f-sub4 7)
(f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x0) )
@@ -2690,7 +2769,7 @@
; 1111 iiii iiii 0111 11001 qqqqq 00101 0 cpmovi.w =crqc,simm8p4 (c3_imm)
(dni cpmovi_w_C3 "cpmovi.w $crqc,simm8p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovi.w $crqc,$simm8p4"
(+ MAJ_15 simm8p4 (f-sub4 7)
(f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x0) )
@@ -2702,7 +2781,7 @@
; 1111 iiii iiii 0111 11001 qqqqq 00110 0 cdmoviu =crqc,imm8p4 (c3_imm)
(dni cdmoviu_C3 "cdmoviu $crqc,imm8p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmoviu"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdmoviu $crqc,$imm8p4"
(+ MAJ_15 imm8p4 (f-sub4 7)
(f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x0) )
@@ -2714,7 +2793,7 @@
; 1111 iiii iiii 0111 11001 qqqqq 00111 0 cdmovi =crqc,simm8p4 (c3_imm)
(dni cdmovi_C3 "cdmovi $crqc,simm8p4 C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmovi"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdmovi $crqc,$simm8p4"
(+ MAJ_15 simm8p4 (f-sub4 7)
(f-ivc2-5u16 #x19) crqc (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x0) )
@@ -2726,331 +2805,503 @@
; 1111 0000 0000 0111 00000 qqqqq ppppp 1 cpadda1u.b crqc,crpc (c3_1)
(dni cpadda1u_b_C3 "cpadda1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI))
"cpadda1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpadda1u_b" pc crqc crpc) )
()
)
; 1111 0000 0001 0111 00000 qqqqq ppppp 1 cpadda1.b crqc,crpc (c3_1)
(dni cpadda1_b_C3 "cpadda1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpadda1_b") (CPTYPE V8QI))
"cpadda1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpadda1_b" pc crqc crpc) )
()
)
; 1111 0000 0010 0111 00000 qqqqq ppppp 1 cpaddua1.h crqc,crpc (c3_1)
(dni cpaddua1_h_C3 "cpaddua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI))
"cpaddua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x2) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpaddua1_h" pc crqc crpc) )
()
)
; 1111 0000 0011 0111 00000 qqqqq ppppp 1 cpaddla1.h crqc,crpc (c3_1)
(dni cpaddla1_h_C3 "cpaddla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI))
"cpaddla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpaddla1_h" pc crqc crpc) )
()
)
; 1111 0000 0100 0111 00000 qqqqq ppppp 1 cpaddaca1u.b crqc,crpc (c3_1)
(dni cpaddaca1u_b_C3 "cpaddaca1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI))
"cpaddaca1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddaca1u_b" pc crqc crpc) )
()
)
; 1111 0000 0101 0111 00000 qqqqq ppppp 1 cpaddaca1.b crqc,crpc (c3_1)
(dni cpaddaca1_b_C3 "cpaddaca1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI))
"cpaddaca1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddaca1_b" pc crqc crpc) )
()
)
; 1111 0000 0110 0111 00000 qqqqq ppppp 1 cpaddacua1.h crqc,crpc (c3_1)
(dni cpaddacua1_h_C3 "cpaddacua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI))
"cpaddacua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x6) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddacua1_h" pc crqc crpc) )
()
)
; 1111 0000 0111 0111 00000 qqqqq ppppp 1 cpaddacla1.h crqc,crpc (c3_1)
(dni cpaddacla1_h_C3 "cpaddacla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI))
"cpaddacla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x7) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddacla1_h" pc crqc crpc) )
()
)
; 1111 0000 1000 0111 00000 qqqqq ppppp 1 cpsuba1u.b crqc,crpc (c3_1)
(dni cpsuba1u_b_C3 "cpsuba1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI))
"cpsuba1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsuba1u_b" pc crqc crpc) )
()
)
; 1111 0000 1001 0111 00000 qqqqq ppppp 1 cpsuba1.b crqc,crpc (c3_1)
(dni cpsuba1_b_C3 "cpsuba1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI))
"cpsuba1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsuba1_b" pc crqc crpc) )
()
)
; 1111 0000 1010 0111 00000 qqqqq ppppp 1 cpsubua1.h crqc,crpc (c3_1)
(dni cpsubua1_h_C3 "cpsubua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI))
"cpsubua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsubua1_h" pc crqc crpc) )
()
)
; 1111 0000 1011 0111 00000 qqqqq ppppp 1 cpsubla1.h crqc,crpc (c3_1)
(dni cpsubla1_h_C3 "cpsubla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI))
"cpsubla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpsubla1_h" pc crqc crpc) )
()
)
; 1111 0000 1100 0111 00000 qqqqq ppppp 1 cpsubaca1u.b crqc,crpc (c3_1)
(dni cpsubaca1u_b_C3 "cpsubaca1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI))
"cpsubaca1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubaca1u_b" pc crqc crpc) )
()
)
; 1111 0000 1101 0111 00000 qqqqq ppppp 1 cpsubaca1.b crqc,crpc (c3_1)
(dni cpsubaca1_b_C3 "cpsubaca1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI))
"cpsubaca1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubaca1_b" pc crqc crpc) )
()
)
; 1111 0000 1110 0111 00000 qqqqq ppppp 1 cpsubacua1.h crqc,crpc (c3_1)
(dni cpsubacua1_h_C3 "cpsubacua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI))
"cpsubacua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubacua1_h" pc crqc crpc) )
()
)
; 1111 0000 1111 0111 00000 qqqqq ppppp 1 cpsubacla1.h crqc,crpc (c3_1)
(dni cpsubacla1_h_C3 "cpsubacla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI))
"cpsubacla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubacla1_h" pc crqc crpc) )
()
)
; 1111 0001 0000 0111 00000 qqqqq ppppp 1 cpabsa1u.b crqc,crpc (c3_1)
(dni cpabsa1u_b_C3 "cpabsa1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI))
"cpabsa1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpabsa1u_b" pc crqc crpc) )
()
)
; 1111 0001 0001 0111 00000 qqqqq ppppp 1 cpabsa1.b crqc,crpc (c3_1)
(dni cpabsa1_b_C3 "cpabsa1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI))
"cpabsa1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpabsa1_b" pc crqc crpc) )
()
)
; 1111 0001 0010 0111 00000 qqqqq ppppp 1 cpabsua1.h crqc,crpc (c3_1)
(dni cpabsua1_h_C3 "cpabsua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI))
"cpabsua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpabsua1_h" pc crqc crpc) )
()
)
; 1111 0001 0011 0111 00000 qqqqq ppppp 1 cpabsla1.h crqc,crpc (c3_1)
(dni cpabsla1_h_C3 "cpabsla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI))
"cpabsla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpabsla1_h" pc crqc crpc) )
()
)
; 1111 0001 0100 0111 00000 qqqqq ppppp 1 cpsada1u.b crqc,crpc (c3_1)
(dni cpsada1u_b_C3 "cpsada1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI))
"cpsada1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsada1u_b" pc crqc crpc) )
()
)
; 1111 0001 0101 0111 00000 qqqqq ppppp 1 cpsada1.b crqc,crpc (c3_1)
(dni cpsada1_b_C3 "cpsada1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsada1_b") (CPTYPE V8QI))
"cpsada1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsada1_b" pc crqc crpc) )
()
)
; 1111 0001 0110 0111 00000 qqqqq ppppp 1 cpsadua1.h crqc,crpc (c3_1)
(dni cpsadua1_h_C3 "cpsadua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI))
"cpsadua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsadua1_h" pc crqc crpc) )
()
)
; 1111 0001 0111 0111 00000 qqqqq ppppp 1 cpsadla1.h crqc,crpc (c3_1)
(dni cpsadla1_h_C3 "cpsadla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI))
"cpsadla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsadla1_h" pc crqc crpc) )
()
)
; 1111 0010 0000 0111 00000 qqqqq ppppp 1 cpseta1.h crqc,crpc (c3_1)
(dni cpseta1_h_C3 "cpseta1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpseta1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpseta1_h") (CPTYPE V4HI))
"cpseta1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpseta1_h" pc crqc crpc) )
()
)
; 1111 0010 0010 0111 00000 qqqqq ppppp 1 cpsetua1.w crqc,crpc (c3_1)
(dni cpsetua1_w_C3 "cpsetua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI))
"cpsetua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x2) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsetua1_w" pc crqc crpc) )
()
)
; 1111 0010 0011 0111 00000 qqqqq ppppp 1 cpsetla1.w crqc,crpc (c3_1)
(dni cpsetla1_w_C3 "cpsetla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI))
"cpsetla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x3) (f-sub4 7)
(f-ivc2-5u16 #x0) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpsetla1_w" pc crqc crpc) )
()
)
; 1111 000 ooooo 0111 00100 00000 00000 1 cpmova1.b =croc (c3_1)
(dni cpmova1_b_C3 "cpmova1.b $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmova1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST))
"cpmova1.b $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
@@ -3062,7 +3313,7 @@
; 1111 000 ooooo 0111 00100 00000 00010 1 cpmovua1.h =croc (c3_1)
(dni cpmovua1_h_C3 "cpmovua1.h $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovua1.h $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x2) (f-ivc2-1u31 #x1) )
@@ -3074,7 +3325,7 @@
; 1111 000 ooooo 0111 00100 00000 00011 1 cpmovla1.h =croc (c3_1)
(dni cpmovla1_h_C3 "cpmovla1.h $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovla1.h $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x3) (f-ivc2-1u31 #x1) )
@@ -3086,7 +3337,7 @@
; 1111 000 ooooo 0111 00100 00000 00100 1 cpmovuua1.w =croc (c3_1)
(dni cpmovuua1_w_C3 "cpmovuua1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovuua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovuua1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x4) (f-ivc2-1u31 #x1) )
@@ -3098,7 +3349,7 @@
; 1111 000 ooooo 0111 00100 00000 00101 1 cpmovula1.w =croc (c3_1)
(dni cpmovula1_w_C3 "cpmovula1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovula1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovula1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x5) (f-ivc2-1u31 #x1) )
@@ -3110,7 +3361,7 @@
; 1111 000 ooooo 0111 00100 00000 00110 1 cpmovlua1.w =croc (c3_1)
(dni cpmovlua1_w_C3 "cpmovlua1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovlua1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x6) (f-ivc2-1u31 #x1) )
@@ -3122,7 +3373,7 @@
; 1111 000 ooooo 0111 00100 00000 00111 1 cpmovlla1.w =croc (c3_1)
(dni cpmovlla1_w_C3 "cpmovlla1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovlla1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x7) (f-ivc2-1u31 #x1) )
@@ -3134,7 +3385,7 @@
; 1111 000 ooooo 0111 00100 00000 10000 1 cppacka1u.b =croc (c3_1)
(dni cppacka1u_b_C3 "cppacka1u.b $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST))
"cppacka1u.b $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x10) (f-ivc2-1u31 #x1) )
@@ -3146,7 +3397,7 @@
; 1111 000 ooooo 0111 00100 00000 10001 1 cppacka1.b =croc (c3_1)
(dni cppacka1_b_C3 "cppacka1.b $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST))
"cppacka1.b $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x11) (f-ivc2-1u31 #x1) )
@@ -3158,7 +3409,7 @@
; 1111 000 ooooo 0111 00100 00000 10010 1 cppackua1.h =croc (c3_1)
(dni cppackua1_h_C3 "cppackua1.h $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST))
"cppackua1.h $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x12) (f-ivc2-1u31 #x1) )
@@ -3170,7 +3421,7 @@
; 1111 000 ooooo 0111 00100 00000 10011 1 cppackla1.h =croc (c3_1)
(dni cppackla1_h_C3 "cppackla1.h $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST))
"cppackla1.h $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x13) (f-ivc2-1u31 #x1) )
@@ -3182,7 +3433,7 @@
; 1111 000 ooooo 0111 00100 00000 10100 1 cppackua1.w =croc (c3_1)
(dni cppackua1_w_C3 "cppackua1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST))
"cppackua1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x14) (f-ivc2-1u31 #x1) )
@@ -3194,7 +3445,7 @@
; 1111 000 ooooo 0111 00100 00000 10101 1 cppackla1.w =croc (c3_1)
(dni cppackla1_w_C3 "cppackla1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST))
"cppackla1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x15) (f-ivc2-1u31 #x1) )
@@ -3206,7 +3457,7 @@
; 1111 000 ooooo 0111 00100 00000 10110 1 cpmovhua1.w =croc (c3_1)
(dni cpmovhua1_w_C3 "cpmovhua1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovhua1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x16) (f-ivc2-1u31 #x1) )
@@ -3218,7 +3469,7 @@
; 1111 000 ooooo 0111 00100 00000 10111 1 cpmovhla1.w =croc (c3_1)
(dni cpmovhla1_w_C3 "cpmovhla1.w $croc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovhla1.w $croc"
(+ MAJ_15 (f-ivc2-3u4 #x0) croc (f-sub4 7)
(f-ivc2-5u16 #x4) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x17) (f-ivc2-1u31 #x1) )
@@ -3236,6 +3487,14 @@
(f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsrla1" pc crqc) )
()
)
@@ -3248,6 +3507,14 @@
(f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsraa1" pc crqc) )
()
)
@@ -3260,6 +3527,14 @@
(f-ivc2-5u16 #x2) crqc (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpslla1" pc crqc) )
()
)
@@ -3272,6 +3547,14 @@
(f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsrlia1" pc imm5p7) )
()
)
@@ -3284,6 +3567,14 @@
(f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsraia1" pc imm5p7) )
()
)
@@ -3296,558 +3587,818 @@
(f-ivc2-5u16 #x3) (f-ivc2-5u21 #x0) (f-ivc2-5u26 #x0) (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsllia1" pc imm5p7) )
()
)
; 1111 0000 0000 0111 00001 qqqqq ppppp 1 cpssqa1u.b crqc,crpc (c3_1)
(dni cpssqa1u_b_C3 "cpssqa1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI))
"cpssqa1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x0) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpssqa1u_b" pc crqc crpc) )
()
)
; 1111 0000 0001 0111 00001 qqqqq ppppp 1 cpssqa1.b crqc,crpc (c3_1)
(dni cpssqa1_b_C3 "cpssqa1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI))
"cpssqa1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpssqa1_b" pc crqc crpc) )
()
)
; 1111 0000 0100 0111 00001 qqqqq ppppp 1 cpssda1u.b crqc,crpc (c3_1)
(dni cpssda1u_b_C3 "cpssda1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI))
"cpssda1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x4) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpssda1u_b" pc crqc crpc) )
()
)
; 1111 0000 0101 0111 00001 qqqqq ppppp 1 cpssda1.b crqc,crpc (c3_1)
(dni cpssda1_b_C3 "cpssda1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpssda1_b") (CPTYPE V8QI))
"cpssda1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x5) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpssda1_b" pc crqc crpc) )
()
)
; 1111 0000 1000 0111 00001 qqqqq ppppp 1 cpmula1u.b crqc,crpc (c3_1)
(dni cpmula1u_b_C3 "cpmula1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI))
"cpmula1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x8) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmula1u_b" pc crqc crpc) )
()
)
; 1111 0000 1001 0111 00001 qqqqq ppppp 1 cpmula1.b crqc,crpc (c3_1)
(dni cpmula1_b_C3 "cpmula1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmula1_b") (CPTYPE V8QI))
"cpmula1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x9) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmula1_b" pc crqc crpc) )
()
)
; 1111 0000 1010 0111 00001 qqqqq ppppp 1 cpmulua1.h crqc,crpc (c3_1)
(dni cpmulua1_h_C3 "cpmulua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI))
"cpmulua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xa) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmulua1_h" pc crqc crpc) )
()
)
; 1111 0000 1011 0111 00001 qqqqq ppppp 1 cpmulla1.h crqc,crpc (c3_1)
(dni cpmulla1_h_C3 "cpmulla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI))
"cpmulla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpmulla1_h" pc crqc crpc) )
()
)
; 1111 0000 1100 0111 00001 qqqqq ppppp 1 cpmulua1u.w crqc,crpc (c3_1)
(dni cpmulua1u_w_C3 "cpmulua1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1u_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI))
"cpmulua1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xc) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmulua1u_w" pc crqc crpc) )
()
)
; 1111 0000 1101 0111 00001 qqqqq ppppp 1 cpmulla1u.w crqc,crpc (c3_1)
(dni cpmulla1u_w_C3 "cpmulla1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1u_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI))
"cpmulla1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xd) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpmulla1u_w" pc crqc crpc) )
()
)
; 1111 0000 1110 0111 00001 qqqqq ppppp 1 cpmulua1.w crqc,crpc (c3_1)
(dni cpmulua1_w_C3 "cpmulua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI))
"cpmulua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xe) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmulua1_w" pc crqc crpc) )
()
)
; 1111 0000 1111 0111 00001 qqqqq ppppp 1 cpmulla1.w crqc,crpc (c3_1)
(dni cpmulla1_w_C3 "cpmulla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI))
"cpmulla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #xf) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpmulla1_w" pc crqc crpc) )
()
)
; 1111 0001 0000 0111 00001 qqqqq ppppp 1 cpmada1u.b crqc,crpc (c3_1)
(dni cpmada1u_b_C3 "cpmada1u.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1u_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI))
"cpmada1u.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x10) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmada1u_b" pc crqc crpc) )
()
)
; 1111 0001 0001 0111 00001 qqqqq ppppp 1 cpmada1.b crqc,crpc (c3_1)
(dni cpmada1_b_C3 "cpmada1.b $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1_b"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmada1_b") (CPTYPE V8QI))
"cpmada1.b $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x11) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmada1_b" pc crqc crpc) )
()
)
; 1111 0001 0010 0111 00001 qqqqq ppppp 1 cpmadua1.h crqc,crpc (c3_1)
(dni cpmadua1_h_C3 "cpmadua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI))
"cpmadua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadua1_h" pc crqc crpc) )
()
)
; 1111 0001 0011 0111 00001 qqqqq ppppp 1 cpmadla1.h crqc,crpc (c3_1)
(dni cpmadla1_h_C3 "cpmadla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI))
"cpmadla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadla1_h" pc crqc crpc) )
()
)
; 1111 0001 0100 0111 00001 qqqqq ppppp 1 cpmadua1u.w crqc,crpc (c3_1)
(dni cpmadua1u_w_C3 "cpmadua1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1u_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI))
"cpmadua1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x14) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadua1u_w" pc crqc crpc) )
()
)
; 1111 0001 0101 0111 00001 qqqqq ppppp 1 cpmadla1u.w crqc,crpc (c3_1)
(dni cpmadla1u_w_C3 "cpmadla1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1u_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI))
"cpmadla1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x15) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadla1u_w" pc crqc crpc) )
()
)
; 1111 0001 0110 0111 00001 qqqqq ppppp 1 cpmadua1.w crqc,crpc (c3_1)
(dni cpmadua1_w_C3 "cpmadua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI))
"cpmadua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadua1_w" pc crqc crpc) )
()
)
; 1111 0001 0111 0111 00001 qqqqq ppppp 1 cpmadla1.w crqc,crpc (c3_1)
(dni cpmadla1_w_C3 "cpmadla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI))
"cpmadla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadla1_w" pc crqc crpc) )
()
)
; 1111 0001 1010 0111 00001 qqqqq ppppp 1 cpmsbua1.h crqc,crpc (c3_1)
(dni cpmsbua1_h_C3 "cpmsbua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI))
"cpmsbua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1a) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbua1_h" pc crqc crpc) )
()
)
; 1111 0001 1011 0111 00001 qqqqq ppppp 1 cpmsbla1.h crqc,crpc (c3_1)
(dni cpmsbla1_h_C3 "cpmsbla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI))
"cpmsbla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbla1_h" pc crqc crpc) )
()
)
; 1111 0001 1100 0111 00001 qqqqq ppppp 1 cpmsbua1u.w crqc,crpc (c3_1)
(dni cpmsbua1u_w_C3 "cpmsbua1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1u_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI))
"cpmsbua1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1c) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbua1u_w" pc crqc crpc) )
()
)
; 1111 0001 1101 0111 00001 qqqqq ppppp 1 cpmsbla1u.w crqc,crpc (c3_1)
(dni cpmsbla1u_w_C3 "cpmsbla1u.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1u_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI))
"cpmsbla1u.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1d) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbla1u_w" pc crqc crpc) )
()
)
; 1111 0001 1110 0111 00001 qqqqq ppppp 1 cpmsbua1.w crqc,crpc (c3_1)
(dni cpmsbua1_w_C3 "cpmsbua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI))
"cpmsbua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1e) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbua1_w" pc crqc crpc) )
()
)
; 1111 0001 1111 0111 00001 qqqqq ppppp 1 cpmsbla1.w crqc,crpc (c3_1)
(dni cpmsbla1_w_C3 "cpmsbla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI))
"cpmsbla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x0) (f-ivc2-5u7 #x1f) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbla1_w" pc crqc crpc) )
()
)
; 1111 0011 0010 0111 00001 qqqqq ppppp 1 cpsmadua1.h crqc,crpc (c3_1)
(dni cpsmadua1_h_C3 "cpsmadua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI))
"cpsmadua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadua1_h" pc crqc crpc) )
()
)
; 1111 0011 0011 0111 00001 qqqqq ppppp 1 cpsmadla1.h crqc,crpc (c3_1)
(dni cpsmadla1_h_C3 "cpsmadla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI))
"cpsmadla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadla1_h" pc crqc crpc) )
()
)
; 1111 0011 0110 0111 00001 qqqqq ppppp 1 cpsmadua1.w crqc,crpc (c3_1)
(dni cpsmadua1_w_C3 "cpsmadua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI))
"cpsmadua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadua1_w" pc crqc crpc) )
()
)
; 1111 0011 0111 0111 00001 qqqqq ppppp 1 cpsmadla1.w crqc,crpc (c3_1)
(dni cpsmadla1_w_C3 "cpsmadla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI))
"cpsmadla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadla1_w" pc crqc crpc) )
()
)
; 1111 0011 1010 0111 00001 qqqqq ppppp 1 cpsmsbua1.h crqc,crpc (c3_1)
(dni cpsmsbua1_h_C3 "cpsmsbua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI))
"cpsmsbua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1a) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbua1_h" pc crqc crpc) )
()
)
; 1111 0011 1011 0111 00001 qqqqq ppppp 1 cpsmsbla1.h crqc,crpc (c3_1)
(dni cpsmsbla1_h_C3 "cpsmsbla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI))
"cpsmsbla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbla1_h" pc crqc crpc) )
()
)
; 1111 0011 1110 0111 00001 qqqqq ppppp 1 cpsmsbua1.w crqc,crpc (c3_1)
(dni cpsmsbua1_w_C3 "cpsmsbua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI))
"cpsmsbua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1e) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbua1_w" pc crqc crpc) )
()
)
; 1111 0011 1111 0111 00001 qqqqq ppppp 1 cpsmsbla1.w crqc,crpc (c3_1)
(dni cpsmsbla1_w_C3 "cpsmsbla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI))
"cpsmsbla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x1) (f-ivc2-5u7 #x1f) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbla1_w" pc crqc crpc) )
()
)
; 1111 0100 1010 0111 00001 qqqqq ppppp 1 cpmulslua1.h crqc,crpc (c3_1)
(dni cpmulslua1_h_C3 "cpmulslua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI))
"cpmulslua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xa) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslua1_h" pc crqc crpc) )
()
)
; 1111 0100 1011 0111 00001 qqqqq ppppp 1 cpmulslla1.h crqc,crpc (c3_1)
(dni cpmulslla1_h_C3 "cpmulslla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI))
"cpmulslla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xb) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslla1_h" pc crqc crpc) )
()
)
; 1111 0100 1110 0111 00001 qqqqq ppppp 1 cpmulslua1.w crqc,crpc (c3_1)
(dni cpmulslua1_w_C3 "cpmulslua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI))
"cpmulslua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xe) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslua1_w" pc crqc crpc) )
()
)
; 1111 0100 1111 0111 00001 qqqqq ppppp 1 cpmulslla1.w crqc,crpc (c3_1)
(dni cpmulslla1_w_C3 "cpmulslla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI))
"cpmulslla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x2) (f-ivc2-5u7 #xf) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslla1_w" pc crqc crpc) )
()
)
; 1111 0111 0010 0111 00001 qqqqq ppppp 1 cpsmadslua1.h crqc,crpc (c3_1)
(dni cpsmadslua1_h_C3 "cpsmadslua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI))
"cpsmadslua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x12) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslua1_h" pc crqc crpc) )
()
)
; 1111 0111 0011 0111 00001 qqqqq ppppp 1 cpsmadslla1.h crqc,crpc (c3_1)
(dni cpsmadslla1_h_C3 "cpsmadslla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI))
"cpsmadslla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x13) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslla1_h" pc crqc crpc) )
()
)
; 1111 0111 0110 0111 00001 qqqqq ppppp 1 cpsmadslua1.w crqc,crpc (c3_1)
(dni cpsmadslua1_w_C3 "cpsmadslua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI))
"cpsmadslua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x16) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslua1_w" pc crqc crpc) )
()
)
; 1111 0111 0111 0111 00001 qqqqq ppppp 1 cpsmadslla1.w crqc,crpc (c3_1)
(dni cpsmadslla1_w_C3 "cpsmadslla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI))
"cpsmadslla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x17) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslla1_w" pc crqc crpc) )
()
)
; 1111 0111 1010 0111 00001 qqqqq ppppp 1 cpsmsbslua1.h crqc,crpc (c3_1)
(dni cpsmsbslua1_h_C3 "cpsmsbslua1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI))
"cpsmsbslua1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1a) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslua1_h" pc crqc crpc) )
()
)
; 1111 0111 1011 0111 00001 qqqqq ppppp 1 cpsmsbslla1.h crqc,crpc (c3_1)
(dni cpsmsbslla1_h_C3 "cpsmsbslla1.h $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_h"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI))
"cpsmsbslla1.h $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1b) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslla1_h" pc crqc crpc) )
()
)
; 1111 0111 1110 0111 00001 qqqqq ppppp 1 cpsmsbslua1.w crqc,crpc (c3_1)
(dni cpsmsbslua1_w_C3 "cpsmsbslua1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI))
"cpsmsbslua1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1e) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslua1_w" pc crqc crpc) )
()
)
; 1111 0111 1111 0111 00001 qqqqq ppppp 1 cpsmsbslla1.w crqc,crpc (c3_1)
(dni cpsmsbslla1_w_C3 "cpsmsbslla1.w $crqc,$crpc C3"
- (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_w"))
+ (OPTIONAL_CP_INSN ivc2-c3-isa (SLOTS C3) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI))
"cpsmsbslla1.w $crqc,$crpc"
(+ MAJ_15 (f-ivc2-3u4 #x3) (f-ivc2-5u7 #x1f) (f-sub4 7)
(f-ivc2-5u16 #x1) crqc crpc (f-ivc2-1u31 #x1) )
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslla1_w" pc crqc crpc) )
()
)
@@ -3865,7 +4416,7 @@
; 00001 qqqqq ppppp ooooo cpadd3.b =crop,crqp,crpp (p0_1)
(dni cpadd3_b_P0S_P1 "cpadd3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_b") (CPTYPE V8QI) (CRET FIRST))
"cpadd3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3876,7 +4427,7 @@
; 00010 qqqqq ppppp ooooo cpadd3.h =crop,crqp,crpp (p0_1)
(dni cpadd3_h_P0S_P1 "cpadd3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_h") (CPTYPE V4HI) (CRET FIRST))
"cpadd3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x2) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3887,7 +4438,7 @@
; 00011 qqqqq ppppp ooooo cpadd3.w =crop,crqp,crpp (p0_1)
(dni cpadd3_w_P0S_P1 "cpadd3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpadd3_w") (CPTYPE V2SI) (CRET FIRST))
"cpadd3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x3) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3898,7 +4449,7 @@
; 00101 qqqqq ppppp ooooo cpunpacku.b =crop,crqp,crpp (p0_1)
(dni cpunpacku_b_P0S_P1 "cpunpacku.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_b") (CPTYPE V8UQI) (CRET FIRST))
"cpunpacku.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x5) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3909,7 +4460,7 @@
; 00110 qqqqq ppppp ooooo cpunpacku.h =crop,crqp,crpp (p0_1)
(dni cpunpacku_h_P0S_P1 "cpunpacku.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_h") (CPTYPE V4UHI) (CRET FIRST))
"cpunpacku.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x6) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3920,7 +4471,7 @@
; 00111 qqqqq ppppp ooooo cpunpacku.w =crop,crqp,crpp (p0_1)
(dni cpunpacku_w_P0S_P1 "cpunpacku.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpacku_w") (CPTYPE V2USI) (CRET FIRST))
"cpunpacku.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x7) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3931,7 +4482,7 @@
; 01001 qqqqq ppppp ooooo cpunpackl.b =crop,crqp,crpp (p0_1)
(dni cpunpackl_b_P0S_P1 "cpunpackl.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_b") (CPTYPE V8QI) (CRET FIRST))
"cpunpackl.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x9) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3942,7 +4493,7 @@
; 01010 qqqqq ppppp ooooo cpunpackl.h =crop,crqp,crpp (p0_1)
(dni cpunpackl_h_P0S_P1 "cpunpackl.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_h") (CPTYPE V4HI) (CRET FIRST))
"cpunpackl.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xa) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3953,7 +4504,7 @@
; 01011 qqqqq ppppp ooooo cpunpackl.w =crop,crqp,crpp (p0_1)
(dni cpunpackl_w_P0S_P1 "cpunpackl.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpunpackl_w") (CPTYPE V2SI) (CRET FIRST))
"cpunpackl.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xb) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3964,7 +4515,7 @@
; 00100 qqqqq ppppp ooooo cpsel =crop,crqp,crpp (p0_1)
(dni cpsel_P0S_P1 "cpsel $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpsel"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpsel") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpsel $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x4) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3975,7 +4526,7 @@
; 01100 qqqqq ppppp ooooo cpfsftbs0 =crop,crqp,crpp (p0_1)
(dni cpfsftbs0_P0S_P1 "cpfsftbs0 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpfsftbs0 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xc) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3986,7 +4537,7 @@
; 01101 qqqqq ppppp ooooo cpfsftbs1 =crop,crqp,crpp (p0_1)
(dni cpfsftbs1_P0S_P1 "cpfsftbs1 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs1"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpfsftbs1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpfsftbs1 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #xd) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -3997,7 +4548,7 @@
; 10000 qqqqq 00000 ooooo cpmov =crop,crqp (p0_1)
(dni cpmov_P0S_P1 "cpmov $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmov"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmov") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmov $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4008,7 +4559,7 @@
; 10000 qqqqq 00001 ooooo cpabsz.b =crop,crqp (p0_1)
(dni cpabsz_b_P0S_P1 "cpabsz.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_b") (CPTYPE V8QI) (CRET FIRST))
"cpabsz.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4019,7 +4570,7 @@
; 10000 qqqqq 00010 ooooo cpabsz.h =crop,crqp (p0_1)
(dni cpabsz_h_P0S_P1 "cpabsz.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_h") (CPTYPE V4HI) (CRET FIRST))
"cpabsz.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4030,7 +4581,7 @@
; 10000 qqqqq 00011 ooooo cpabsz.w =crop,crqp (p0_1)
(dni cpabsz_w_P0S_P1 "cpabsz.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpabsz_w") (CPTYPE V2SI) (CRET FIRST))
"cpabsz.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4041,7 +4592,7 @@
; 10000 qqqqq 00100 ooooo cpldz.h =crop,crqp (p0_1)
(dni cpldz_h_P0S_P1 "cpldz.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_h") (CPTYPE V4HI) (CRET FIRST))
"cpldz.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4052,7 +4603,7 @@
; 10000 qqqqq 00101 ooooo cpldz.w =crop,crqp (p0_1)
(dni cpldz_w_P0S_P1 "cpldz.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpldz_w") (CPTYPE V2SI) (CRET FIRST))
"cpldz.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4063,7 +4614,7 @@
; 10000 qqqqq 00110 ooooo cpnorm.h =crop,crqp (p0_1)
(dni cpnorm_h_P0S_P1 "cpnorm.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_h") (CPTYPE V4HI) (CRET FIRST))
"cpnorm.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4074,7 +4625,7 @@
; 10000 qqqqq 00111 ooooo cpnorm.w =crop,crqp (p0_1)
(dni cpnorm_w_P0S_P1 "cpnorm.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpnorm_w") (CPTYPE V2SI) (CRET FIRST))
"cpnorm.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4085,7 +4636,7 @@
; 10000 qqqqq 01000 ooooo cphaddu.b =crop,crqp (p0_1)
(dni cphaddu_b_P0S_P1 "cphaddu.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphaddu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphaddu_b") (CPTYPE V8UQI) (CRET FIRST))
"cphaddu.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4096,7 +4647,7 @@
; 10000 qqqqq 01001 ooooo cphadd.b =crop,crqp (p0_1)
(dni cphadd_b_P0S_P1 "cphadd.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_b") (CPTYPE V8QI) (CRET FIRST))
"cphadd.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4107,7 +4658,7 @@
; 10000 qqqqq 01010 ooooo cphadd.h =crop,crqp (p0_1)
(dni cphadd_h_P0S_P1 "cphadd.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_h") (CPTYPE V4HI) (CRET FIRST))
"cphadd.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4118,7 +4669,7 @@
; 10000 qqqqq 01011 ooooo cphadd.w =crop,crqp (p0_1)
(dni cphadd_w_P0S_P1 "cphadd.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cphadd_w") (CPTYPE V2SI) (CRET FIRST))
"cphadd.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4129,18 +4680,18 @@
; 10000 qqqqq 01100 00000 cpccadd.b +crqp (p0_1)
(dni cpccadd_b_P0S_P1 "cpccadd.b $crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpccadd_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpccadd_b") (CPTYPE V8QI) (CRET FIRSTCOPY))
"cpccadd.b $crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xc) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
- (c-call "ivc2_cpccadd_b" pc (index-of crqp)) )
+ (set crqp (c-call DI "ivc2_cpccadd_b" pc crqp)) )
()
)
; 10000 qqqqq 01101 ooooo cpbcast.b =crop,crqp (p0_1)
(dni cpbcast_b_P0S_P1 "cpbcast.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_b") (CPTYPE V8QI) (CRET FIRST))
"cpbcast.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4151,7 +4702,7 @@
; 10000 qqqqq 01110 ooooo cpbcast.h =crop,crqp (p0_1)
(dni cpbcast_h_P0S_P1 "cpbcast.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_h") (CPTYPE V4HI) (CRET FIRST))
"cpbcast.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4162,7 +4713,7 @@
; 10000 qqqqq 01111 ooooo cpbcast.w =crop,crqp (p0_1)
(dni cpbcast_w_P0S_P1 "cpbcast.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpbcast_w") (CPTYPE V2SI) (CRET FIRST))
"cpbcast.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4173,7 +4724,7 @@
; 10000 qqqqq 10000 ooooo cpextuu.b =crop,crqp (p0_1)
(dni cpextuu_b_P0S_P1 "cpextuu.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_b") (CPTYPE V8UQI) (CRET FIRST))
"cpextuu.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4184,7 +4735,7 @@
; 10000 qqqqq 10001 ooooo cpextu.b =crop,crqp (p0_1)
(dni cpextu_b_P0S_P1 "cpextu.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_b") (CPTYPE V8UQI) (CRET FIRST))
"cpextu.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4195,7 +4746,7 @@
; 10000 qqqqq 10010 ooooo cpextuu.h =crop,crqp (p0_1)
(dni cpextuu_h_P0S_P1 "cpextuu.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextuu_h") (CPTYPE V4UHI) (CRET FIRST))
"cpextuu.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4206,7 +4757,7 @@
; 10000 qqqqq 10011 ooooo cpextu.h =crop,crqp (p0_1)
(dni cpextu_h_P0S_P1 "cpextu.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextu_h") (CPTYPE V4UHI) (CRET FIRST))
"cpextu.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4217,7 +4768,7 @@
; 10000 qqqqq 10100 ooooo cpextlu.b =crop,crqp (p0_1)
(dni cpextlu_b_P0S_P1 "cpextlu.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_b") (CPTYPE V8UQI) (CRET FIRST))
"cpextlu.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x14) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4228,7 +4779,7 @@
; 10000 qqqqq 10101 ooooo cpextl.b =crop,crqp (p0_1)
(dni cpextl_b_P0S_P1 "cpextl.b $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_b") (CPTYPE V8QI) (CRET FIRST))
"cpextl.b $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x15) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4239,7 +4790,7 @@
; 10000 qqqqq 10110 ooooo cpextlu.h =crop,crqp (p0_1)
(dni cpextlu_h_P0S_P1 "cpextlu.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextlu_h") (CPTYPE V4UHI) (CRET FIRST))
"cpextlu.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x16) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4250,7 +4801,7 @@
; 10000 qqqqq 10111 ooooo cpextl.h =crop,crqp (p0_1)
(dni cpextl_h_P0S_P1 "cpextl.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpextl_h") (CPTYPE V4HI) (CRET FIRST))
"cpextl.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x17) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4261,7 +4812,7 @@
; 10000 qqqqq 11000 ooooo cpcastub.h =crop,crqp (p0_1)
(dni cpcastub_h_P0S_P1 "cpcastub.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_h") (CPTYPE V4HI) (CRET FIRST))
"cpcastub.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x18) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4272,7 +4823,7 @@
; 10000 qqqqq 11001 ooooo cpcastb.h =crop,crqp (p0_1)
(dni cpcastb_h_P0S_P1 "cpcastb.h $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_h") (CPTYPE V4HI) (CRET FIRST))
"cpcastb.h $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x19) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4283,7 +4834,7 @@
; 10000 qqqqq 11100 ooooo cpcastub.w =crop,crqp (p0_1)
(dni cpcastub_w_P0S_P1 "cpcastub.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastub_w") (CPTYPE V2SI) (CRET FIRST))
"cpcastub.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1c) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4294,7 +4845,7 @@
; 10000 qqqqq 11101 ooooo cpcastb.w =crop,crqp (p0_1)
(dni cpcastb_w_P0S_P1 "cpcastb.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastb_w") (CPTYPE V2SI) (CRET FIRST))
"cpcastb.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1d) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4305,7 +4856,7 @@
; 10000 qqqqq 11110 ooooo cpcastuh.w =crop,crqp (p0_1)
(dni cpcastuh_w_P0S_P1 "cpcastuh.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastuh_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcastuh_w") (CPTYPE V2SI) (CRET FIRST))
"cpcastuh.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1e) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4316,7 +4867,7 @@
; 10000 qqqqq 11111 ooooo cpcasth.w =crop,crqp (p0_1)
(dni cpcasth_w_P0S_P1 "cpcasth.w $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcasth_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcasth_w") (CPTYPE V2SI) (CRET FIRST))
"cpcasth.w $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1f) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4327,7 +4878,7 @@
; 10000 qqqqq 11010 ooooo cdcastuw =crop,crqp (p0_1)
(dni cdcastuw_P0S_P1 "cdcastuw $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastuw"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastuw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdcastuw $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1a) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4338,7 +4889,7 @@
; 10000 qqqqq 11011 ooooo cdcastw =crop,crqp (p0_1)
(dni cdcastw_P0S_P1 "cdcastw $crop,$crqp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastw"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cdcastw") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdcastw $crop,$crqp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x10) crqp (f-ivc2-5u18 #x1b) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4349,7 +4900,7 @@
; 10001 00000 00000 ooooo cpmovfrcsar0 =crop (p0_1)
(dni cpmovfrcsar0_P0S_P1 "cpmovfrcsar0 $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar0"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar0") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmovfrcsar0 $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4360,7 +4911,7 @@
; 10001 00000 01111 ooooo cpmovfrcsar1 =crop (p0_1)
(dni cpmovfrcsar1_P0S_P1 "cpmovfrcsar1 $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar1"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcsar1") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmovfrcsar1 $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4371,7 +4922,7 @@
; 10001 00000 00001 ooooo cpmovfrcc =crop (p0_1)
(dni cpmovfrcc_P0S_P1 "cpmovfrcc $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcc"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovfrcc") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpmovfrcc $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x11) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4415,491 +4966,680 @@
; 10010 qqqqq ppppp 00000 cpcmpeqz.b crqp,crpp (p0_1)
(dni cpcmpeqz_b_P0S_P1 "cpcmpeqz.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeqz_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeqz_b") (CPTYPE V8QI))
"cpcmpeqz.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeqz_b" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 00001 cpcmpeq.b crqp,crpp (p0_1)
(dni cpcmpeq_b_P0S_P1 "cpcmpeq.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_b") (CPTYPE V8QI))
"cpcmpeq.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeq_b" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 00011 cpcmpeq.h crqp,crpp (p0_1)
(dni cpcmpeq_h_P0S_P1 "cpcmpeq.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_h") (CPTYPE V4HI))
"cpcmpeq.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeq_h" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 00101 cpcmpeq.w crqp,crpp (p0_1)
(dni cpcmpeq_w_P0S_P1 "cpcmpeq.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpeq_w") (CPTYPE V2SI))
"cpcmpeq.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpeq_w" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 01001 cpcmpne.b crqp,crpp (p0_1)
(dni cpcmpne_b_P0S_P1 "cpcmpne.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_b") (CPTYPE V8QI))
"cpcmpne.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpne_b" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 01011 cpcmpne.h crqp,crpp (p0_1)
(dni cpcmpne_h_P0S_P1 "cpcmpne.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_h") (CPTYPE V4HI))
"cpcmpne.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpne_h" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 01101 cpcmpne.w crqp,crpp (p0_1)
(dni cpcmpne_w_P0S_P1 "cpcmpne.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpne_w") (CPTYPE V2SI))
"cpcmpne.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpne_w" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 10000 cpcmpgtu.b crqp,crpp (p0_1)
(dni cpcmpgtu_b_P0S_P1 "cpcmpgtu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_b") (CPTYPE V8UQI))
"cpcmpgtu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgtu_b" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 10001 cpcmpgt.b crqp,crpp (p0_1)
(dni cpcmpgt_b_P0S_P1 "cpcmpgt.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_b") (CPTYPE V8QI))
"cpcmpgt.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgt_b" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 10011 cpcmpgt.h crqp,crpp (p0_1)
(dni cpcmpgt_h_P0S_P1 "cpcmpgt.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_h") (CPTYPE V4HI))
"cpcmpgt.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgt_h" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 10100 cpcmpgtu.w crqp,crpp (p0_1)
(dni cpcmpgtu_w_P0S_P1 "cpcmpgtu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgtu_w") (CPTYPE V2USI))
"cpcmpgtu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgtu_w" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 10101 cpcmpgt.w crqp,crpp (p0_1)
(dni cpcmpgt_w_P0S_P1 "cpcmpgt.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgt_w") (CPTYPE V2SI))
"cpcmpgt.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgt_w" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 11000 cpcmpgeu.b crqp,crpp (p0_1)
(dni cpcmpgeu_b_P0S_P1 "cpcmpgeu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_b") (CPTYPE V8UQI))
"cpcmpgeu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgeu_b" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 11001 cpcmpge.b crqp,crpp (p0_1)
(dni cpcmpge_b_P0S_P1 "cpcmpge.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_b") (CPTYPE V8QI))
"cpcmpge.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpge_b" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 11011 cpcmpge.h crqp,crpp (p0_1)
(dni cpcmpge_h_P0S_P1 "cpcmpge.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_h") (CPTYPE V4HI))
"cpcmpge.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpge_h" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 11100 cpcmpgeu.w crqp,crpp (p0_1)
(dni cpcmpgeu_w_P0S_P1 "cpcmpgeu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpgeu_w") (CPTYPE V2USI))
"cpcmpgeu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpgeu_w" pc crqp crpp) )
()
)
; 10010 qqqqq ppppp 11101 cpcmpge.w crqp,crpp (p0_1)
(dni cpcmpge_w_P0S_P1 "cpcmpge.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpcmpge_w") (CPTYPE V2SI))
"cpcmpge.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x12) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cc 0)
(c-call "ivc2_cpcmpge_w" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00000 cpadda0u.b crqp,crpp (p0_1)
(dni cpadda0u_b_P0S "cpadda0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0u_b") (CPTYPE V8UQI))
"cpadda0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpadda0u_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00001 cpadda0.b crqp,crpp (p0_1)
(dni cpadda0_b_P0S "cpadda0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpadda0_b") (CPTYPE V8QI))
"cpadda0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpadda0_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00010 cpaddua0.h crqp,crpp (p0_1)
(dni cpaddua0_h_P0S "cpaddua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddua0_h") (CPTYPE V4HI))
"cpaddua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpaddua0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00011 cpaddla0.h crqp,crpp (p0_1)
(dni cpaddla0_h_P0S "cpaddla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddla0_h") (CPTYPE V4HI))
"cpaddla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
(c-call "ivc2_cpaddla0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00100 cpaddaca0u.b crqp,crpp (p0_1)
(dni cpaddaca0u_b_P0S "cpaddaca0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0u_b") (CPTYPE V8UQI))
"cpaddaca0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpaddaca0u_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00101 cpaddaca0.b crqp,crpp (p0_1)
(dni cpaddaca0_b_P0S "cpaddaca0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddaca0_b") (CPTYPE V8QI))
"cpaddaca0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpaddaca0_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00110 cpaddacua0.h crqp,crpp (p0_1)
(dni cpaddacua0_h_P0S "cpaddacua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacua0_h") (CPTYPE V4HI))
"cpaddacua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpaddacua0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 00111 cpaddacla0.h crqp,crpp (p0_1)
(dni cpaddacla0_h_P0S "cpaddacla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpaddacla0_h") (CPTYPE V4HI))
"cpaddacla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpaddacla0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01000 cpsuba0u.b crqp,crpp (p0_1)
(dni cpsuba0u_b_P0S "cpsuba0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0u_b") (CPTYPE V8UQI))
"cpsuba0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsuba0u_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01001 cpsuba0.b crqp,crpp (p0_1)
(dni cpsuba0_b_P0S "cpsuba0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsuba0_b") (CPTYPE V8QI))
"cpsuba0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsuba0_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01010 cpsubua0.h crqp,crpp (p0_1)
(dni cpsubua0_h_P0S "cpsubua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubua0_h") (CPTYPE V4HI))
"cpsubua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsubua0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01011 cpsubla0.h crqp,crpp (p0_1)
(dni cpsubla0_h_P0S "cpsubla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubla0_h") (CPTYPE V4HI))
"cpsubla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
(c-call "ivc2_cpsubla0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01100 cpsubaca0u.b crqp,crpp (p0_1)
(dni cpsubaca0u_b_P0S "cpsubaca0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0u_b") (CPTYPE V8UQI))
"cpsubaca0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsubaca0u_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01101 cpsubaca0.b crqp,crpp (p0_1)
(dni cpsubaca0_b_P0S "cpsubaca0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubaca0_b") (CPTYPE V8QI))
"cpsubaca0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsubaca0_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01110 cpsubacua0.h crqp,crpp (p0_1)
(dni cpsubacua0_h_P0S "cpsubacua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacua0_h") (CPTYPE V4HI))
"cpsubacua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsubacua0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 01111 cpsubacla0.h crqp,crpp (p0_1)
(dni cpsubacla0_h_P0S "cpsubacla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsubacla0_h") (CPTYPE V4HI))
"cpsubacla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsubacla0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10000 cpabsa0u.b crqp,crpp (p0_1)
(dni cpabsa0u_b_P0S "cpabsa0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0u_b") (CPTYPE V8UQI))
"cpabsa0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpabsa0u_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10001 cpabsa0.b crqp,crpp (p0_1)
(dni cpabsa0_b_P0S "cpabsa0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsa0_b") (CPTYPE V8QI))
"cpabsa0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpabsa0_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10010 cpabsua0.h crqp,crpp (p0_1)
(dni cpabsua0_h_P0S "cpabsua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsua0_h") (CPTYPE V4HI))
"cpabsua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpabsua0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10011 cpabsla0.h crqp,crpp (p0_1)
(dni cpabsla0_h_P0S "cpabsla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpabsla0_h") (CPTYPE V4HI))
"cpabsla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
(c-call "ivc2_cpabsla0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10100 cpsada0u.b crqp,crpp (p0_1)
(dni cpsada0u_b_P0S "cpsada0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0u_b") (CPTYPE V8UQI))
"cpsada0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsada0u_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10101 cpsada0.b crqp,crpp (p0_1)
(dni cpsada0_b_P0S "cpsada0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsada0_b") (CPTYPE V8QI))
"cpsada0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsada0_b" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10110 cpsadua0.h crqp,crpp (p0_1)
(dni cpsadua0_h_P0S "cpsadua0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadua0_h") (CPTYPE V4HI))
"cpsadua0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsadua0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 10111 cpsadla0.h crqp,crpp (p0_1)
(dni cpsadla0_h_P0S "cpsadla0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsadla0_h") (CPTYPE V4HI))
"cpsadla0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpsadla0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 11011 cpseta0.h crqp,crpp (p0_1)
(dni cpseta0_h_P0S "cpseta0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpseta0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpseta0_h") (CPTYPE V4HI))
"cpseta0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpseta0_h" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 11100 cpsetua0.w crqp,crpp (p0_1)
(dni cpsetua0_w_P0S "cpsetua0.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetua0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetua0_w") (CPTYPE V2SI))
"cpsetua0.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsetua0_w" pc crqp crpp) )
()
)
; 11000 qqqqq ppppp 11101 cpsetla0.w crqp,crpp (p0_1)
(dni cpsetla0_w_P0S "cpsetla0.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetla0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpsetla0_w") (CPTYPE V2SI))
"cpsetla0.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
(c-call "ivc2_cpsetla0_w" pc crqp crpp) )
()
)
; 11001 00000 00001 ooooo cpmova0.b =crop (p0_1)
(dni cpmova0_b_P0S "cpmova0.b $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmova0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmova0_b") (CPTYPE V8QI) (CRET FIRST))
"cpmova0.b $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4910,7 +5650,7 @@
; 11001 00000 00010 ooooo cpmovua0.h =crop (p0_1)
(dni cpmovua0_h_P0S "cpmovua0.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovua0_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovua0.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4921,7 +5661,7 @@
; 11001 00000 00011 ooooo cpmovla0.h =crop (p0_1)
(dni cpmovla0_h_P0S "cpmovla0.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovla0_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovla0.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4932,7 +5672,7 @@
; 11001 00000 00100 ooooo cpmovuua0.w =crop (p0_1)
(dni cpmovuua0_w_P0S "cpmovuua0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovuua0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovuua0_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovuua0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4943,7 +5683,7 @@
; 11001 00000 00101 ooooo cpmovula0.w =crop (p0_1)
(dni cpmovula0_w_P0S "cpmovula0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovula0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovula0_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovula0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4954,7 +5694,7 @@
; 11001 00000 00110 ooooo cpmovlua0.w =crop (p0_1)
(dni cpmovlua0_w_P0S "cpmovlua0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlua0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlua0_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovlua0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4965,7 +5705,7 @@
; 11001 00000 00111 ooooo cpmovlla0.w =crop (p0_1)
(dni cpmovlla0_w_P0S "cpmovlla0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlla0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovlla0_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovlla0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4976,7 +5716,7 @@
; 11001 00000 01000 ooooo cppacka0u.b =crop (p0_1)
(dni cppacka0u_b_P0S "cppacka0u.b $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0u_b") (CPTYPE V8UQI) (CRET FIRST))
"cppacka0u.b $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4987,7 +5727,7 @@
; 11001 00000 01001 ooooo cppacka0.b =crop (p0_1)
(dni cppacka0_b_P0S "cppacka0.b $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppacka0_b") (CPTYPE V8QI) (CRET FIRST))
"cppacka0.b $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
(sequence ()
@@ -4998,7 +5738,7 @@
; 11001 00000 01010 ooooo cppackua0.h =crop (p0_1)
(dni cppackua0_h_P0S "cppackua0.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_h") (CPTYPE V4HI) (CRET FIRST))
"cppackua0.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
(sequence ()
@@ -5009,7 +5749,7 @@
; 11001 00000 01011 ooooo cppackla0.h =crop (p0_1)
(dni cppackla0_h_P0S "cppackla0.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_h") (CPTYPE V4HI) (CRET FIRST))
"cppackla0.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
(sequence ()
@@ -5020,7 +5760,7 @@
; 11001 00000 01100 ooooo cppackua0.w =crop (p0_1)
(dni cppackua0_w_P0S "cppackua0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackua0_w") (CPTYPE V2SI) (CRET FIRST))
"cppackua0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0))
(sequence ()
@@ -5031,7 +5771,7 @@
; 11001 00000 01101 ooooo cppackla0.w =crop (p0_1)
(dni cppackla0_w_P0S "cppackla0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cppackla0_w") (CPTYPE V2SI) (CRET FIRST))
"cppackla0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
(sequence ()
@@ -5042,7 +5782,7 @@
; 11001 00000 01110 ooooo cpmovhua0.w =crop (p0_1)
(dni cpmovhua0_w_P0S "cpmovhua0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhua0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhua0_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovhua0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
(sequence ()
@@ -5053,7 +5793,7 @@
; 11001 00000 01111 ooooo cpmovhla0.w =crop (p0_1)
(dni cpmovhla0_w_P0S "cpmovhla0.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhla0_w"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpmovhla0_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovhla0.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
(sequence ()
@@ -5069,6 +5809,15 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpacsuma0" pc) )
()
)
@@ -5080,6 +5829,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpaccpa0" pc) )
()
)
@@ -5091,6 +5848,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsrla0" pc crqp) )
()
)
@@ -5102,6 +5867,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsraa0" pc crqp) )
()
)
@@ -5113,6 +5886,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpslla0" pc crqp) )
()
)
@@ -5124,6 +5905,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsrlia0" pc imm5p23) )
()
)
@@ -5135,6 +5924,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsraia0" pc imm5p23) )
()
)
@@ -5146,189 +5943,301 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpsllia0" pc imm5p23) )
()
)
; 11111 qqqqq ppppp 00000 cpfsftba0s0u.b crqp,crpp (p0_1)
(dni cpfsftba0s0u_b_P0S "cpfsftba0s0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0u_b") (CPTYPE V8UQI))
"cpfsftba0s0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpfsftba0s0u_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 00001 cpfsftba0s0.b crqp,crpp (p0_1)
(dni cpfsftba0s0_b_P0S "cpfsftba0s0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s0_b") (CPTYPE V8QI))
"cpfsftba0s0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpfsftba0s0_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 00010 cpfsftbua0s0.h crqp,crpp (p0_1)
(dni cpfsftbua0s0_h_P0S "cpfsftbua0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s0_h") (CPTYPE V4HI))
"cpfsftbua0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpfsftbua0s0_h" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 00011 cpfsftbla0s0.h crqp,crpp (p0_1)
(dni cpfsftbla0s0_h_P0S "cpfsftbla0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s0_h") (CPTYPE V4HI))
"cpfsftbla0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
(c-call "ivc2_cpfsftbla0s0_h" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 00100 cpfaca0s0u.b crqp,crpp (p0_1)
(dni cpfaca0s0u_b_P0S "cpfaca0s0u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0u_b") (CPTYPE V8UQI))
"cpfaca0s0u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfaca0s0u_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 00101 cpfaca0s0.b crqp,crpp (p0_1)
(dni cpfaca0s0_b_P0S "cpfaca0s0.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s0_b") (CPTYPE V8QI))
"cpfaca0s0.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfaca0s0_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 00110 cpfacua0s0.h crqp,crpp (p0_1)
(dni cpfacua0s0_h_P0S "cpfacua0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s0_h") (CPTYPE V4HI))
"cpfacua0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfacua0s0_h" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 00111 cpfacla0s0.h crqp,crpp (p0_1)
(dni cpfacla0s0_h_P0S "cpfacla0s0.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s0_h") (CPTYPE V4HI))
"cpfacla0s0.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfacla0s0_h" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01000 cpfsftba0s1u.b crqp,crpp (p0_1)
(dni cpfsftba0s1u_b_P0S "cpfsftba0s1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1u_b") (CPTYPE V8UQI))
"cpfsftba0s1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpfsftba0s1u_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01001 cpfsftba0s1.b crqp,crpp (p0_1)
(dni cpfsftba0s1_b_P0S "cpfsftba0s1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftba0s1_b") (CPTYPE V8QI))
"cpfsftba0s1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpfsftba0s1_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01010 cpfsftbua0s1.h crqp,crpp (p0_1)
(dni cpfsftbua0s1_h_P0S "cpfsftbua0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbua0s1_h") (CPTYPE V4HI))
"cpfsftbua0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
(c-call "ivc2_cpfsftbua0s1_h" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01011 cpfsftbla0s1.h crqp,crpp (p0_1)
(dni cpfsftbla0s1_h_P0S "cpfsftbla0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfsftbla0s1_h") (CPTYPE V4HI))
"cpfsftbla0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
(c-call "ivc2_cpfsftbla0s1_h" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01100 cpfaca0s1u.b crqp,crpp (p0_1)
(dni cpfaca0s1u_b_P0S "cpfaca0s1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1u_b") (CPTYPE V8UQI))
"cpfaca0s1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfaca0s1u_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01101 cpfaca0s1.b crqp,crpp (p0_1)
(dni cpfaca0s1_b_P0S "cpfaca0s1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfaca0s1_b") (CPTYPE V8QI))
"cpfaca0s1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfaca0s1_b" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01110 cpfacua0s1.h crqp,crpp (p0_1)
(dni cpfacua0s1_h_P0S "cpfacua0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacua0s1_h") (CPTYPE V4HI))
"cpfacua0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfacua0s1_h" pc crqp crpp) )
()
)
; 11111 qqqqq ppppp 01111 cpfacla0s1.h crqp,crpp (p0_1)
(dni cpfacla0s1_h_P0S "cpfacla0s1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p0s-isa (SLOTS P0S) (INTRINSIC "cpfacla0s1_h") (CPTYPE V4HI))
"cpfacla0s1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_cofa0 0)
(c-call "ivc2_cpfacla0s1_h" pc crqp crpp) )
()
)
; xxxxxiii 01000 qqqqq ppppp ooooo cpfsftbi =crop,crqp,crpp,imm3p5 (p0_1)
(dni cpfsftbi_P0_P1 "cpfsftbi $crop,$crqp,$crpp,imm3p5 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpfsftbi"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpfsftbi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cpfsftbi $crop,$crqp,$crpp,$imm3p5"
(+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x8) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5339,7 +6248,7 @@
; 00000000 10011 qqqqq ppppp 00001 cpacmpeq.b crqp,crpp (p0_1)
(dni cpacmpeq_b_P0_P1 "cpacmpeq.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_b") (CPTYPE V8QI))
"cpacmpeq.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
@@ -5350,7 +6259,7 @@
; 00000000 10011 qqqqq ppppp 00011 cpacmpeq.h crqp,crpp (p0_1)
(dni cpacmpeq_h_P0_P1 "cpacmpeq.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_h") (CPTYPE V4HI))
"cpacmpeq.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
@@ -5361,7 +6270,7 @@
; 00000000 10011 qqqqq ppppp 00101 cpacmpeq.w crqp,crpp (p0_1)
(dni cpacmpeq_w_P0_P1 "cpacmpeq.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpeq_w") (CPTYPE V2SI))
"cpacmpeq.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
@@ -5372,7 +6281,7 @@
; 00000000 10011 qqqqq ppppp 01001 cpacmpne.b crqp,crpp (p0_1)
(dni cpacmpne_b_P0_P1 "cpacmpne.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_b") (CPTYPE V8QI))
"cpacmpne.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
@@ -5383,7 +6292,7 @@
; 00000000 10011 qqqqq ppppp 01011 cpacmpne.h crqp,crpp (p0_1)
(dni cpacmpne_h_P0_P1 "cpacmpne.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_h") (CPTYPE V4HI))
"cpacmpne.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
@@ -5394,7 +6303,7 @@
; 00000000 10011 qqqqq ppppp 01101 cpacmpne.w crqp,crpp (p0_1)
(dni cpacmpne_w_P0_P1 "cpacmpne.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpne_w") (CPTYPE V2SI))
"cpacmpne.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
@@ -5405,7 +6314,7 @@
; 00000000 10011 qqqqq ppppp 10000 cpacmpgtu.b crqp,crpp (p0_1)
(dni cpacmpgtu_b_P0_P1 "cpacmpgtu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_b") (CPTYPE V8UQI))
"cpacmpgtu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
@@ -5416,7 +6325,7 @@
; 00000000 10011 qqqqq ppppp 10001 cpacmpgt.b crqp,crpp (p0_1)
(dni cpacmpgt_b_P0_P1 "cpacmpgt.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_b") (CPTYPE V8QI))
"cpacmpgt.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
@@ -5427,7 +6336,7 @@
; 00000000 10011 qqqqq ppppp 10011 cpacmpgt.h crqp,crpp (p0_1)
(dni cpacmpgt_h_P0_P1 "cpacmpgt.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_h") (CPTYPE V4HI))
"cpacmpgt.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
@@ -5438,7 +6347,7 @@
; 00000000 10011 qqqqq ppppp 10100 cpacmpgtu.w crqp,crpp (p0_1)
(dni cpacmpgtu_w_P0_P1 "cpacmpgtu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgtu_w") (CPTYPE V2USI))
"cpacmpgtu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
@@ -5449,7 +6358,7 @@
; 00000000 10011 qqqqq ppppp 10101 cpacmpgt.w crqp,crpp (p0_1)
(dni cpacmpgt_w_P0_P1 "cpacmpgt.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgt_w") (CPTYPE V2SI))
"cpacmpgt.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
@@ -5460,7 +6369,7 @@
; 00000000 10011 qqqqq ppppp 11000 cpacmpgeu.b crqp,crpp (p0_1)
(dni cpacmpgeu_b_P0_P1 "cpacmpgeu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_b") (CPTYPE V8UQI))
"cpacmpgeu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0))
(sequence ()
@@ -5471,7 +6380,7 @@
; 00000000 10011 qqqqq ppppp 11001 cpacmpge.b crqp,crpp (p0_1)
(dni cpacmpge_b_P0_P1 "cpacmpge.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_b") (CPTYPE V8QI))
"cpacmpge.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0))
(sequence ()
@@ -5482,7 +6391,7 @@
; 00000000 10011 qqqqq ppppp 11011 cpacmpge.h crqp,crpp (p0_1)
(dni cpacmpge_h_P0_P1 "cpacmpge.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_h") (CPTYPE V4HI))
"cpacmpge.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
@@ -5493,7 +6402,7 @@
; 00000000 10011 qqqqq ppppp 11100 cpacmpgeu.w crqp,crpp (p0_1)
(dni cpacmpgeu_w_P0_P1 "cpacmpgeu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpgeu_w") (CPTYPE V2USI))
"cpacmpgeu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
@@ -5504,7 +6413,7 @@
; 00000000 10011 qqqqq ppppp 11101 cpacmpge.w crqp,crpp (p0_1)
(dni cpacmpge_w_P0_P1 "cpacmpge.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpacmpge_w") (CPTYPE V2SI))
"cpacmpge.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
@@ -5515,7 +6424,7 @@
; 00000001 10011 qqqqq ppppp 00001 cpocmpeq.b crqp,crpp (p0_1)
(dni cpocmpeq_b_P0_P1 "cpocmpeq.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_b") (CPTYPE V8QI))
"cpocmpeq.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
@@ -5526,7 +6435,7 @@
; 00000001 10011 qqqqq ppppp 00011 cpocmpeq.h crqp,crpp (p0_1)
(dni cpocmpeq_h_P0_P1 "cpocmpeq.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_h") (CPTYPE V4HI))
"cpocmpeq.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
@@ -5537,7 +6446,7 @@
; 00000001 10011 qqqqq ppppp 00101 cpocmpeq.w crqp,crpp (p0_1)
(dni cpocmpeq_w_P0_P1 "cpocmpeq.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpeq_w") (CPTYPE V2SI))
"cpocmpeq.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
@@ -5548,7 +6457,7 @@
; 00000001 10011 qqqqq ppppp 01001 cpocmpne.b crqp,crpp (p0_1)
(dni cpocmpne_b_P0_P1 "cpocmpne.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_b") (CPTYPE V8QI))
"cpocmpne.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
@@ -5559,7 +6468,7 @@
; 00000001 10011 qqqqq ppppp 01011 cpocmpne.h crqp,crpp (p0_1)
(dni cpocmpne_h_P0_P1 "cpocmpne.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_h") (CPTYPE V4HI))
"cpocmpne.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
@@ -5570,7 +6479,7 @@
; 00000001 10011 qqqqq ppppp 01101 cpocmpne.w crqp,crpp (p0_1)
(dni cpocmpne_w_P0_P1 "cpocmpne.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpne_w") (CPTYPE V2SI))
"cpocmpne.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
@@ -5581,7 +6490,7 @@
; 00000001 10011 qqqqq ppppp 10000 cpocmpgtu.b crqp,crpp (p0_1)
(dni cpocmpgtu_b_P0_P1 "cpocmpgtu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_b") (CPTYPE V8UQI))
"cpocmpgtu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
@@ -5592,7 +6501,7 @@
; 00000001 10011 qqqqq ppppp 10001 cpocmpgt.b crqp,crpp (p0_1)
(dni cpocmpgt_b_P0_P1 "cpocmpgt.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_b") (CPTYPE V8QI))
"cpocmpgt.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
@@ -5603,7 +6512,7 @@
; 00000001 10011 qqqqq ppppp 10011 cpocmpgt.h crqp,crpp (p0_1)
(dni cpocmpgt_h_P0_P1 "cpocmpgt.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_h") (CPTYPE V4HI))
"cpocmpgt.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
@@ -5614,7 +6523,7 @@
; 00000001 10011 qqqqq ppppp 10100 cpocmpgtu.w crqp,crpp (p0_1)
(dni cpocmpgtu_w_P0_P1 "cpocmpgtu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgtu_w") (CPTYPE V2USI))
"cpocmpgtu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
@@ -5625,7 +6534,7 @@
; 00000001 10011 qqqqq ppppp 10101 cpocmpgt.w crqp,crpp (p0_1)
(dni cpocmpgt_w_P0_P1 "cpocmpgt.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgt_w") (CPTYPE V2SI))
"cpocmpgt.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
@@ -5636,7 +6545,7 @@
; 00000001 10011 qqqqq ppppp 11000 cpocmpgeu.b crqp,crpp (p0_1)
(dni cpocmpgeu_b_P0_P1 "cpocmpgeu.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_b") (CPTYPE V8UQI))
"cpocmpgeu.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x18) (f-ivc2-4u28 0))
(sequence ()
@@ -5647,7 +6556,7 @@
; 00000001 10011 qqqqq ppppp 11001 cpocmpge.b crqp,crpp (p0_1)
(dni cpocmpge_b_P0_P1 "cpocmpge.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_b") (CPTYPE V8QI))
"cpocmpge.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x19) (f-ivc2-4u28 0))
(sequence ()
@@ -5658,7 +6567,7 @@
; 00000001 10011 qqqqq ppppp 11011 cpocmpge.h crqp,crpp (p0_1)
(dni cpocmpge_h_P0_P1 "cpocmpge.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_h") (CPTYPE V4HI))
"cpocmpge.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
@@ -5669,7 +6578,7 @@
; 00000001 10011 qqqqq ppppp 11100 cpocmpgeu.w crqp,crpp (p0_1)
(dni cpocmpgeu_w_P0_P1 "cpocmpgeu.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpgeu_w") (CPTYPE V2USI))
"cpocmpgeu.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
@@ -5680,7 +6589,7 @@
; 00000001 10011 qqqqq ppppp 11101 cpocmpge.w crqp,crpp (p0_1)
(dni cpocmpge_w_P0_P1 "cpocmpge.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpocmpge_w") (CPTYPE V2SI))
"cpocmpge.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x13) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
@@ -5691,7 +6600,7 @@
; 00000011 10100 qqqqq ppppp ooooo cdadd3 =crop,crqp,crpp (p0_1)
(dni cdadd3_P0_P1 "cdadd3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdadd3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdadd3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdadd3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5702,7 +6611,7 @@
; 00000100 10100 qqqqq ppppp ooooo cpsub3.b =crop,crqp,crpp (p0_1)
(dni cpsub3_b_P0_P1 "cpsub3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsub3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x4) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5713,7 +6622,7 @@
; 00000101 10100 qqqqq ppppp ooooo cpsub3.h =crop,crqp,crpp (p0_1)
(dni cpsub3_h_P0_P1 "cpsub3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsub3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x5) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5724,7 +6633,7 @@
; 00000110 10100 qqqqq ppppp ooooo cpsub3.w =crop,crqp,crpp (p0_1)
(dni cpsub3_w_P0_P1 "cpsub3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsub3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsub3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x6) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5735,7 +6644,7 @@
; 00000111 10100 qqqqq ppppp ooooo cdsub3 =crop,crqp,crpp (p0_1)
(dni cdsub3_P0_P1 "cdsub3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsub3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsub3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsub3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x7) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5746,7 +6655,7 @@
; 00001010 10100 qqqqq ppppp ooooo cpsadd3.h =crop,crqp,crpp (p0_1)
(dni cpsadd3_h_P0_P1 "cpsadd3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsadd3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #xa) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5757,7 +6666,7 @@
; 00001011 10100 qqqqq ppppp ooooo cpsadd3.w =crop,crqp,crpp (p0_1)
(dni cpsadd3_w_P0_P1 "cpsadd3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsadd3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsadd3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #xb) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5768,29 +6677,31 @@
; 00001110 10100 qqqqq ppppp ooooo cpssub3.h =crop,crqp,crpp (p0_1)
(dni cpssub3_h_P0_P1 "cpssub3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssub3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #xe) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
(set crop (c-call DI "ivc2_cpssub3_h" pc crqp crpp)) )
()
)
; 00001111 10100 qqqqq ppppp ooooo cpssub3.w =crop,crqp,crpp (p0_1)
(dni cpssub3_w_P0_P1 "cpssub3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssub3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssub3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #xf) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_cofr0 0)
(set crop (c-call DI "ivc2_cpssub3_w" pc crqp crpp)) )
()
)
; 00010000 10100 qqqqq ppppp ooooo cpextuaddu3.b =crop,crqp,crpp (p0_1)
(dni cpextuaddu3_b_P0_P1 "cpextuaddu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuaddu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuaddu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextuaddu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x10) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5801,7 +6712,7 @@
; 00010001 10100 qqqqq ppppp ooooo cpextuadd3.b =crop,crqp,crpp (p0_1)
(dni cpextuadd3_b_P0_P1 "cpextuadd3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuadd3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextuadd3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextuadd3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x11) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5812,7 +6723,7 @@
; 00010010 10100 qqqqq ppppp ooooo cpextladdu3.b =crop,crqp,crpp (p0_1)
(dni cpextladdu3_b_P0_P1 "cpextladdu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladdu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladdu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextladdu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x12) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5823,7 +6734,7 @@
; 00010011 10100 qqqqq ppppp ooooo cpextladd3.b =crop,crqp,crpp (p0_1)
(dni cpextladd3_b_P0_P1 "cpextladd3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladd3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextladd3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextladd3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x13) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5834,7 +6745,7 @@
; 00010100 10100 qqqqq ppppp ooooo cpextusubu3.b =crop,crqp,crpp (p0_1)
(dni cpextusubu3_b_P0_P1 "cpextusubu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusubu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusubu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextusubu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x14) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5845,7 +6756,7 @@
; 00010101 10100 qqqqq ppppp ooooo cpextusub3.b =crop,crqp,crpp (p0_1)
(dni cpextusub3_b_P0_P1 "cpextusub3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusub3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextusub3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextusub3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x15) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5856,7 +6767,7 @@
; 00010110 10100 qqqqq ppppp ooooo cpextlsubu3.b =crop,crqp,crpp (p0_1)
(dni cpextlsubu3_b_P0_P1 "cpextlsubu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsubu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsubu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextlsubu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x16) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5867,7 +6778,7 @@
; 00010111 10100 qqqqq ppppp ooooo cpextlsub3.b =crop,crqp,crpp (p0_1)
(dni cpextlsub3_b_P0_P1 "cpextlsub3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsub3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpextlsub3_b") (CPTYPE V8QI) (CRET FIRST))
"cpextlsub3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x17) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5878,7 +6789,7 @@
; 00011000 10100 qqqqq ppppp ooooo cpaveu3.b =crop,crqp,crpp (p0_1)
(dni cpaveu3_b_P0_P1 "cpaveu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaveu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaveu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpaveu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x18) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5889,7 +6800,7 @@
; 00011001 10100 qqqqq ppppp ooooo cpave3.b =crop,crqp,crpp (p0_1)
(dni cpave3_b_P0_P1 "cpave3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_b") (CPTYPE V8QI) (CRET FIRST))
"cpave3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x19) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5900,7 +6811,7 @@
; 00011010 10100 qqqqq ppppp ooooo cpave3.h =crop,crqp,crpp (p0_1)
(dni cpave3_h_P0_P1 "cpave3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_h") (CPTYPE V4HI) (CRET FIRST))
"cpave3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x1a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5911,7 +6822,7 @@
; 00011011 10100 qqqqq ppppp ooooo cpave3.w =crop,crqp,crpp (p0_1)
(dni cpave3_w_P0_P1 "cpave3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpave3_w") (CPTYPE V2SI) (CRET FIRST))
"cpave3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x1b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5922,7 +6833,7 @@
; 00011100 10100 qqqqq ppppp ooooo cpaddsru3.b =crop,crqp,crpp (p0_1)
(dni cpaddsru3_b_P0_P1 "cpaddsru3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsru3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsru3_b") (CPTYPE V8QI) (CRET FIRST))
"cpaddsru3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x1c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5933,7 +6844,7 @@
; 00011101 10100 qqqqq ppppp ooooo cpaddsr3.b =crop,crqp,crpp (p0_1)
(dni cpaddsr3_b_P0_P1 "cpaddsr3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_b") (CPTYPE V8QI) (CRET FIRST))
"cpaddsr3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x1d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5944,7 +6855,7 @@
; 00011110 10100 qqqqq ppppp ooooo cpaddsr3.h =crop,crqp,crpp (p0_1)
(dni cpaddsr3_h_P0_P1 "cpaddsr3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_h") (CPTYPE V4HI) (CRET FIRST))
"cpaddsr3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x1e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5955,7 +6866,7 @@
; 00011111 10100 qqqqq ppppp ooooo cpaddsr3.w =crop,crqp,crpp (p0_1)
(dni cpaddsr3_w_P0_P1 "cpaddsr3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpaddsr3_w") (CPTYPE V2SI) (CRET FIRST))
"cpaddsr3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x1f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5966,7 +6877,7 @@
; 00100000 10100 qqqqq ppppp ooooo cpabsu3.b =crop,crqp,crpp (p0_1)
(dni cpabsu3_b_P0_P1 "cpabsu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabsu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabsu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpabsu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x20) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5977,7 +6888,7 @@
; 00100001 10100 qqqqq ppppp ooooo cpabs3.b =crop,crqp,crpp (p0_1)
(dni cpabs3_b_P0_P1 "cpabs3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_b") (CPTYPE V8QI) (CRET FIRST))
"cpabs3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x21) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5988,7 +6899,7 @@
; 00100010 10100 qqqqq ppppp ooooo cpabs3.h =crop,crqp,crpp (p0_1)
(dni cpabs3_h_P0_P1 "cpabs3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpabs3_h") (CPTYPE V4HI) (CRET FIRST))
"cpabs3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x22) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -5999,7 +6910,7 @@
; 00100100 10100 qqqqq ppppp ooooo cpand3 =crop,crqp,crpp (p0_1)
(dni cpand3_P0_P1 "cpand3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpand3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpand3") (CPTYPE VECT) (CRET FIRST))
"cpand3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x24) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6010,7 +6921,7 @@
; 00100101 10100 qqqqq ppppp ooooo cpor3 =crop,crqp,crpp (p0_1)
(dni cpor3_P0_P1 "cpor3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpor3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpor3") (CPTYPE VECT) (CRET FIRST))
"cpor3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x25) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6021,7 +6932,7 @@
; 00100110 10100 qqqqq ppppp ooooo cpnor3 =crop,crqp,crpp (p0_1)
(dni cpnor3_P0_P1 "cpnor3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpnor3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpnor3") (CPTYPE VECT) (CRET FIRST))
"cpnor3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x26) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6032,7 +6943,7 @@
; 00100111 10100 qqqqq ppppp ooooo cpxor3 =crop,crqp,crpp (p0_1)
(dni cpxor3_P0_P1 "cpxor3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpxor3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpxor3") (CPTYPE VECT) (CRET FIRST))
"cpxor3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x27) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6043,7 +6954,7 @@
; 00101100 10100 qqqqq ppppp ooooo cppacku.b =crop,crqp,crpp (p0_1)
(dni cppacku_b_P0_P1 "cppacku.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppacku_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppacku_b") (CPTYPE V8UQI) (CRET FIRST))
"cppacku.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x2c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6054,7 +6965,7 @@
; 00101101 10100 qqqqq ppppp ooooo cppack.b =crop,crqp,crpp (p0_1)
(dni cppack_b_P0_P1 "cppack.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_b") (CPTYPE V8QI) (CRET FIRST))
"cppack.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x2d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6065,7 +6976,7 @@
; 00101111 10100 qqqqq ppppp ooooo cppack.h =crop,crqp,crpp (p0_1)
(dni cppack_h_P0_P1 "cppack.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cppack_h") (CPTYPE V4HI) (CRET FIRST))
"cppack.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x2f) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6076,7 +6987,7 @@
; 00110000 10100 qqqqq ppppp ooooo cpmaxu3.b =crop,crqp,crpp (p0_1)
(dni cpmaxu3_b_P0_P1 "cpmaxu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpmaxu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x30) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6087,7 +6998,7 @@
; 00110001 10100 qqqqq ppppp ooooo cpmax3.b =crop,crqp,crpp (p0_1)
(dni cpmax3_b_P0_P1 "cpmax3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_b") (CPTYPE V8QI) (CRET FIRST))
"cpmax3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x31) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6098,7 +7009,7 @@
; 00110011 10100 qqqqq ppppp ooooo cpmax3.h =crop,crqp,crpp (p0_1)
(dni cpmax3_h_P0_P1 "cpmax3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_h") (CPTYPE V4HI) (CRET FIRST))
"cpmax3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x33) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6109,7 +7020,7 @@
; 00110100 10100 qqqqq ppppp ooooo cpmaxu3.w =crop,crqp,crpp (p0_1)
(dni cpmaxu3_w_P0_P1 "cpmaxu3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmaxu3_w") (CPTYPE V2SI) (CRET FIRST))
"cpmaxu3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x34) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6120,7 +7031,7 @@
; 00110101 10100 qqqqq ppppp ooooo cpmax3.w =crop,crqp,crpp (p0_1)
(dni cpmax3_w_P0_P1 "cpmax3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmax3_w") (CPTYPE V2SI) (CRET FIRST))
"cpmax3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x35) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6131,7 +7042,7 @@
; 00111000 10100 qqqqq ppppp ooooo cpminu3.b =crop,crqp,crpp (p0_1)
(dni cpminu3_b_P0_P1 "cpminu3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_b") (CPTYPE V8QI) (CRET FIRST))
"cpminu3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x38) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6142,7 +7053,7 @@
; 00111001 10100 qqqqq ppppp ooooo cpmin3.b =crop,crqp,crpp (p0_1)
(dni cpmin3_b_P0_P1 "cpmin3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_b") (CPTYPE V8QI) (CRET FIRST))
"cpmin3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x39) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6153,7 +7064,7 @@
; 00111011 10100 qqqqq ppppp ooooo cpmin3.h =crop,crqp,crpp (p0_1)
(dni cpmin3_h_P0_P1 "cpmin3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_h") (CPTYPE V4HI) (CRET FIRST))
"cpmin3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x3b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6164,7 +7075,7 @@
; 00111100 10100 qqqqq ppppp ooooo cpminu3.w =crop,crqp,crpp (p0_1)
(dni cpminu3_w_P0_P1 "cpminu3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpminu3_w") (CPTYPE V2SI) (CRET FIRST))
"cpminu3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x3c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6175,7 +7086,7 @@
; 00111101 10100 qqqqq ppppp ooooo cpmin3.w =crop,crqp,crpp (p0_1)
(dni cpmin3_w_P0_P1 "cpmin3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmin3_w") (CPTYPE V2SI) (CRET FIRST))
"cpmin3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x3d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6186,7 +7097,7 @@
; 01000000 10100 qqqqq ppppp ooooo cpsrl3.b =crop,crqp,crpp (p0_1)
(dni cpsrl3_b_P0_P1 "cpsrl3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsrl3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x40) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6197,7 +7108,7 @@
; 01000001 10100 qqqqq ppppp ooooo cpssrl3.b =crop,crqp,crpp (p0_1)
(dni cpssrl3_b_P0_P1 "cpssrl3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_b") (CPTYPE V8QI) (CRET FIRST))
"cpssrl3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x41) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6208,7 +7119,7 @@
; 01000010 10100 qqqqq ppppp ooooo cpsrl3.h =crop,crqp,crpp (p0_1)
(dni cpsrl3_h_P0_P1 "cpsrl3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsrl3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x42) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6219,7 +7130,7 @@
; 01000011 10100 qqqqq ppppp ooooo cpssrl3.h =crop,crqp,crpp (p0_1)
(dni cpssrl3_h_P0_P1 "cpssrl3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssrl3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x43) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6230,7 +7141,7 @@
; 01000100 10100 qqqqq ppppp ooooo cpsrl3.w =crop,crqp,crpp (p0_1)
(dni cpsrl3_w_P0_P1 "cpsrl3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrl3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsrl3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x44) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6241,7 +7152,7 @@
; 01000101 10100 qqqqq ppppp ooooo cpssrl3.w =crop,crqp,crpp (p0_1)
(dni cpssrl3_w_P0_P1 "cpssrl3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssrl3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssrl3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x45) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6252,7 +7163,7 @@
; 01000110 10100 qqqqq ppppp ooooo cdsrl3 =crop,crqp,crpp (p0_1)
(dni cdsrl3_P0_P1 "cdsrl3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrl3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrl3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsrl3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x46) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6263,7 +7174,7 @@
; 01001000 10100 qqqqq ppppp ooooo cpsra3.b =crop,crqp,crpp (p0_1)
(dni cpsra3_b_P0_P1 "cpsra3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsra3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x48) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6274,7 +7185,7 @@
; 01001001 10100 qqqqq ppppp ooooo cpssra3.b =crop,crqp,crpp (p0_1)
(dni cpssra3_b_P0_P1 "cpssra3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_b") (CPTYPE V8QI) (CRET FIRST))
"cpssra3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x49) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6285,7 +7196,7 @@
; 01001010 10100 qqqqq ppppp ooooo cpsra3.h =crop,crqp,crpp (p0_1)
(dni cpsra3_h_P0_P1 "cpsra3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsra3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x4a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6296,7 +7207,7 @@
; 01001011 10100 qqqqq ppppp ooooo cpssra3.h =crop,crqp,crpp (p0_1)
(dni cpssra3_h_P0_P1 "cpssra3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssra3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x4b) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6307,7 +7218,7 @@
; 01001100 10100 qqqqq ppppp ooooo cpsra3.w =crop,crqp,crpp (p0_1)
(dni cpsra3_w_P0_P1 "cpsra3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsra3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsra3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x4c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6318,7 +7229,7 @@
; 01001101 10100 qqqqq ppppp ooooo cpssra3.w =crop,crqp,crpp (p0_1)
(dni cpssra3_w_P0_P1 "cpssra3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssra3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssra3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x4d) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6329,7 +7240,7 @@
; 01001110 10100 qqqqq ppppp ooooo cdsra3 =crop,crqp,crpp (p0_1)
(dni cdsra3_P0_P1 "cdsra3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsra3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsra3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsra3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x4e) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6340,7 +7251,7 @@
; 01010000 10100 qqqqq ppppp ooooo cpsll3.b =crop,crqp,crpp (p0_1)
(dni cpsll3_b_P0_P1 "cpsll3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsll3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x50) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6351,7 +7262,7 @@
; 01010001 10100 qqqqq ppppp ooooo cpssll3.b =crop,crqp,crpp (p0_1)
(dni cpssll3_b_P0_P1 "cpssll3.b $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_b") (CPTYPE V8QI) (CRET FIRST))
"cpssll3.b $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x51) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6362,7 +7273,7 @@
; 01010010 10100 qqqqq ppppp ooooo cpsll3.h =crop,crqp,crpp (p0_1)
(dni cpsll3_h_P0_P1 "cpsll3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsll3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x52) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6373,7 +7284,7 @@
; 01010011 10100 qqqqq ppppp ooooo cpssll3.h =crop,crqp,crpp (p0_1)
(dni cpssll3_h_P0_P1 "cpssll3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_h") (CPTYPE V4HI) (CRET FIRST))
"cpssll3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x53) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6384,7 +7295,7 @@
; 01010100 10100 qqqqq ppppp ooooo cpsll3.w =crop,crqp,crpp (p0_1)
(dni cpsll3_w_P0_P1 "cpsll3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsll3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsll3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x54) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6395,7 +7306,7 @@
; 01010101 10100 qqqqq ppppp ooooo cpssll3.w =crop,crqp,crpp (p0_1)
(dni cpssll3_w_P0_P1 "cpssll3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpssll3_w") (CPTYPE V2SI) (CRET FIRST))
"cpssll3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x55) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6406,7 +7317,7 @@
; 01010110 10100 qqqqq ppppp ooooo cdsll3 =crop,crqp,crpp (p0_1)
(dni cdsll3_P0_P1 "cdsll3 $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsll3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsll3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsll3 $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x56) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6417,7 +7328,7 @@
; 01011010 10100 qqqqq ppppp ooooo cpsla3.h =crop,crqp,crpp (p0_1)
(dni cpsla3_h_P0_P1 "cpsla3.h $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsla3.h $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x5a) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6428,7 +7339,7 @@
; 01011100 10100 qqqqq ppppp ooooo cpsla3.w =crop,crqp,crpp (p0_1)
(dni cpsla3_w_P0_P1 "cpsla3.w $crop,$crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsla3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsla3.w $crop,$crqp,$crpp"
(+ (f-ivc2-8u0 #x5c) (f-ivc2-5u8 #x14) crqp crpp crop (f-ivc2-4u28 0))
(sequence ()
@@ -6439,7 +7350,7 @@
; xxxxxiii 10101 qqqqq 00000 ooooo cpsrli3.b =crop,crqp,imm3p5 (p0_1)
(dni cpsrli3_b_P0_P1 "cpsrli3.b $crop,$crqp,imm3p5 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsrli3.b $crop,$crqp,$imm3p5"
(+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x0) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6450,7 +7361,7 @@
; xxxxiiii 10101 qqqqq 00001 ooooo cpsrli3.h =crop,crqp,imm4p4 (p0_1)
(dni cpsrli3_h_P0_P1 "cpsrli3.h $crop,$crqp,imm4p4 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsrli3.h $crop,$crqp,$imm4p4"
(+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6461,7 +7372,7 @@
; xxxiiiii 10101 qqqqq 00010 ooooo cpsrli3.w =crop,crqp,imm5p3 (p0_1)
(dni cpsrli3_w_P0_P1 "cpsrli3.w $crop,$crqp,imm5p3 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrli3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsrli3.w $crop,$crqp,$imm5p3"
(+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6472,7 +7383,7 @@
; xxiiiiii 10101 qqqqq 00011 ooooo cdsrli3 =crop,crqp,imm6p2 (p0_1)
(dni cdsrli3_P0_P1 "cdsrli3 $crop,$crqp,imm6p2 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrli3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsrli3 $crop,$crqp,$imm6p2"
(+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6483,7 +7394,7 @@
; xxxxxiii 10101 qqqqq 00100 ooooo cpsrai3.b =crop,crqp,imm3p5 (p0_1)
(dni cpsrai3_b_P0_P1 "cpsrai3.b $crop,$crqp,imm3p5 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_b") (CPTYPE V8QI) (CRET FIRST))
"cpsrai3.b $crop,$crqp,$imm3p5"
(+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6494,7 +7405,7 @@
; xxxxiiii 10101 qqqqq 00101 ooooo cpsrai3.h =crop,crqp,imm4p4 (p0_1)
(dni cpsrai3_h_P0_P1 "cpsrai3.h $crop,$crqp,imm4p4 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_h") (CPTYPE V4HI) (CRET FIRST))
"cpsrai3.h $crop,$crqp,$imm4p4"
(+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6505,7 +7416,7 @@
; xxxiiiii 10101 qqqqq 00110 ooooo cpsrai3.w =crop,crqp,imm5p3 (p0_1)
(dni cpsrai3_w_P0_P1 "cpsrai3.w $crop,$crqp,imm5p3 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpsrai3_w") (CPTYPE V2SI) (CRET FIRST))
"cpsrai3.w $crop,$crqp,$imm5p3"
(+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6516,7 +7427,7 @@
; xxiiiiii 10101 qqqqq 00111 ooooo cdsrai3 =crop,crqp,imm6p2 (p0_1)
(dni cdsrai3_P0_P1 "cdsrai3 $crop,$crqp,imm6p2 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrai3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdsrai3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdsrai3 $crop,$crqp,$imm6p2"
(+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6527,7 +7438,7 @@
; xxxxxiii 10101 qqqqq 01000 ooooo cpslli3.b =crop,crqp,imm3p5 (p0_1)
(dni cpslli3_b_P0_P1 "cpslli3.b $crop,$crqp,imm3p5 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_b"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_b") (CPTYPE V8QI) (CRET FIRST))
"cpslli3.b $crop,$crqp,$imm3p5"
(+ ivc-x-0-5 imm3p5 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6538,7 +7449,7 @@
; xxxxiiii 10101 qqqqq 01001 ooooo cpslli3.h =crop,crqp,imm4p4 (p0_1)
(dni cpslli3_h_P0_P1 "cpslli3.h $crop,$crqp,imm4p4 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_h") (CPTYPE V4HI) (CRET FIRST))
"cpslli3.h $crop,$crqp,$imm4p4"
(+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6549,7 +7460,7 @@
; xxxiiiii 10101 qqqqq 01010 ooooo cpslli3.w =crop,crqp,imm5p3 (p0_1)
(dni cpslli3_w_P0_P1 "cpslli3.w $crop,$crqp,imm5p3 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslli3_w") (CPTYPE V2SI) (CRET FIRST))
"cpslli3.w $crop,$crqp,$imm5p3"
(+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6560,7 +7471,7 @@
; xxiiiiii 10101 qqqqq 01011 ooooo cdslli3 =crop,crqp,imm6p2 (p0_1)
(dni cdslli3_P0_P1 "cdslli3 $crop,$crqp,imm6p2 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdslli3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdslli3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdslli3 $crop,$crqp,$imm6p2"
(+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6571,7 +7482,7 @@
; xxxxiiii 10101 qqqqq 01101 ooooo cpslai3.h =crop,crqp,imm4p4 (p0_1)
(dni cpslai3_h_P0_P1 "cpslai3.h $crop,$crqp,imm4p4 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_h") (CPTYPE V4HI) (CRET FIRST))
"cpslai3.h $crop,$crqp,$imm4p4"
(+ ivc-x-0-4 imm4p4 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6582,7 +7493,7 @@
; xxxiiiii 10101 qqqqq 01110 ooooo cpslai3.w =crop,crqp,imm5p3 (p0_1)
(dni cpslai3_w_P0_P1 "cpslai3.w $crop,$crqp,imm5p3 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpslai3_w") (CPTYPE V2SI) (CRET FIRST))
"cpslai3.w $crop,$crqp,$imm5p3"
(+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6593,7 +7504,7 @@
; xxxiiiii 10101 qqqqq 10000 ooooo cpclipiu3.w =crop,crqp,imm5p3 (p0_1)
(dni cpclipiu3_w_P0_P1 "cpclipiu3.w $crop,$crqp,imm5p3 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipiu3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipiu3_w") (CPTYPE V2SI) (CRET FIRST))
"cpclipiu3.w $crop,$crqp,$imm5p3"
(+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x10) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6604,7 +7515,7 @@
; xxxiiiii 10101 qqqqq 10001 ooooo cpclipi3.w =crop,crqp,imm5p3 (p0_1)
(dni cpclipi3_w_P0_P1 "cpclipi3.w $crop,$crqp,imm5p3 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipi3_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpclipi3_w") (CPTYPE V2SI) (CRET FIRST))
"cpclipi3.w $crop,$crqp,$imm5p3"
(+ ivc-x-0-3 imm5p3 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x11) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6615,7 +7526,7 @@
; xxiiiiii 10101 qqqqq 10010 ooooo cdclipiu3 =crop,crqp,imm6p2 (p0_1)
(dni cdclipiu3_P0_P1 "cdclipiu3 $crop,$crqp,imm6p2 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipiu3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipiu3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdclipiu3 $crop,$crqp,$imm6p2"
(+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x12) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6626,7 +7537,7 @@
; xxiiiiii 10101 qqqqq 10011 ooooo cdclipi3 =crop,crqp,imm6p2 (p0_1)
(dni cdclipi3_P0_P1 "cdclipi3 $crop,$crqp,imm6p2 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipi3"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdclipi3") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdclipi3 $crop,$crqp,$imm6p2"
(+ ivc-x-0-2 imm6p2 (f-ivc2-5u8 #x15) crqp (f-ivc2-5u18 #x13) crop (f-ivc2-4u28 0))
(sequence ()
@@ -6637,7 +7548,7 @@
; iiiiiiii 10110 qqqqq 01iii iiiii cpmovi.h =crqp,simm16p0 (p0_i)
(dni cpmovi_h_P0_P1 "cpmovi.h $crqp,simm16p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_h"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovi.h $crqp,$simm16p0"
(+ (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0))
(sequence ()
@@ -6648,7 +7559,7 @@
; iiiiiiii 10111 qqqqq 00iii iiiii cpmoviu.w =crqp,imm16p0 (p0_i)
(dni cpmoviu_w_P0_P1 "cpmoviu.w $crqp,imm16p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmoviu_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmoviu_w") (CPTYPE V2USI) (CRET FIRST))
"cpmoviu.w $crqp,$imm16p0"
(+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x0) imm16p0(f-ivc2-4u28 0))
(sequence ()
@@ -6659,7 +7570,7 @@
; iiiiiiii 10111 qqqqq 01iii iiiii cpmovi.w =crqp,simm16p0 (p0_i)
(dni cpmovi_w_P0_P1 "cpmovi.w $crqp,simm16p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_w"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cpmovi_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovi.w $crqp,$simm16p0"
(+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x1) simm16p0(f-ivc2-4u28 0))
(sequence ()
@@ -6670,7 +7581,7 @@
; iiiiiiii 10111 qqqqq 10iii iiiii cdmoviu =crqp,imm16p0 (p0_i)
(dni cdmoviu_P0_P1 "cdmoviu $crqp,imm16p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmoviu"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmoviu") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdmoviu $crqp,$imm16p0"
(+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x2) imm16p0(f-ivc2-4u28 0))
(sequence ()
@@ -6681,7 +7592,7 @@
; iiiiiiii 10111 qqqqq 11iii iiiii cdmovi =crqp,simm16p0 (p0_i)
(dni cdmovi_P0_P1 "cdmovi $crqp,simm16p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmovi"))
+ (OPTIONAL_CP_INSN ivc2-p0-p1-isa (SLOTS P0,P1) (INTRINSIC "cdmovi") (CPTYPE CP_DATA_BUS_INT) (CRET FIRST))
"cdmovi $crqp,$simm16p0"
(+ (f-ivc2-5u8 #x17) crqp (f-ivc2-2u18 #x3) simm16p0(f-ivc2-4u28 0))
(sequence ()
@@ -6703,7 +7614,7 @@
; 00000000 10110 qqqqq 00iii iiiii cpmovi.b =crqp,simm8p20 (p0_i)
(dni cpmovi_b_P0S_P1 "cpmovi.b $crqp,simm8p20 Pn"
- (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovi_b"))
+ (OPTIONAL_CP_INSN ivc2-p0s-p1-isa (SLOTS P0S,P1) (INTRINSIC "cpmovi_b") (CPTYPE V8QI) (CRET FIRST))
"cpmovi.b $crqp,$simm8p20"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x16) crqp (f-ivc2-2u18 #x0) imm8p20(f-ivc2-4u28 0))
(sequence ()
@@ -6714,304 +7625,476 @@
; 00000000 11000 qqqqq ppppp 00000 cpadda1u.b crqp,crpp (p0_1)
(dni cpadda1u_b_P1 "cpadda1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1u_b") (CPTYPE V8UQI))
"cpadda1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpadda1u_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 00001 cpadda1.b crqp,crpp (p0_1)
(dni cpadda1_b_P1 "cpadda1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpadda1_b") (CPTYPE V8QI))
"cpadda1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpadda1_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 00010 cpaddua1.h crqp,crpp (p0_1)
(dni cpaddua1_h_P1 "cpaddua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddua1_h") (CPTYPE V4HI))
"cpaddua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpaddua1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 00011 cpaddla1.h crqp,crpp (p0_1)
(dni cpaddla1_h_P1 "cpaddla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddla1_h") (CPTYPE V4HI))
"cpaddla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpaddla1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 00100 cpaddaca1u.b crqp,crpp (p0_1)
(dni cpaddaca1u_b_P1 "cpaddaca1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1u_b") (CPTYPE V8UQI))
"cpaddaca1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddaca1u_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 00101 cpaddaca1.b crqp,crpp (p0_1)
(dni cpaddaca1_b_P1 "cpaddaca1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddaca1_b") (CPTYPE V8QI))
"cpaddaca1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddaca1_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 00110 cpaddacua1.h crqp,crpp (p0_1)
(dni cpaddacua1_h_P1 "cpaddacua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacua1_h") (CPTYPE V4HI))
"cpaddacua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddacua1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 00111 cpaddacla1.h crqp,crpp (p0_1)
(dni cpaddacla1_h_P1 "cpaddacla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpaddacla1_h") (CPTYPE V4HI))
"cpaddacla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpaddacla1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01000 cpsuba1u.b crqp,crpp (p0_1)
(dni cpsuba1u_b_P1 "cpsuba1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1u_b") (CPTYPE V8UQI))
"cpsuba1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsuba1u_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01001 cpsuba1.b crqp,crpp (p0_1)
(dni cpsuba1_b_P1 "cpsuba1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsuba1_b") (CPTYPE V8QI))
"cpsuba1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsuba1_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01010 cpsubua1.h crqp,crpp (p0_1)
(dni cpsubua1_h_P1 "cpsubua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubua1_h") (CPTYPE V4HI))
"cpsubua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsubua1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01011 cpsubla1.h crqp,crpp (p0_1)
(dni cpsubla1_h_P1 "cpsubla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubla1_h") (CPTYPE V4HI))
"cpsubla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpsubla1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01100 cpsubaca1u.b crqp,crpp (p0_1)
(dni cpsubaca1u_b_P1 "cpsubaca1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1u_b") (CPTYPE V8UQI))
"cpsubaca1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubaca1u_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01101 cpsubaca1.b crqp,crpp (p0_1)
(dni cpsubaca1_b_P1 "cpsubaca1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubaca1_b") (CPTYPE V8QI))
"cpsubaca1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubaca1_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01110 cpsubacua1.h crqp,crpp (p0_1)
(dni cpsubacua1_h_P1 "cpsubacua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacua1_h") (CPTYPE V4HI))
"cpsubacua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubacua1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 01111 cpsubacla1.h crqp,crpp (p0_1)
(dni cpsubacla1_h_P1 "cpsubacla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsubacla1_h") (CPTYPE V4HI))
"cpsubacla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsubacla1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10000 cpabsa1u.b crqp,crpp (p0_1)
(dni cpabsa1u_b_P1 "cpabsa1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1u_b") (CPTYPE V8UQI))
"cpabsa1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpabsa1u_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10001 cpabsa1.b crqp,crpp (p0_1)
(dni cpabsa1_b_P1 "cpabsa1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsa1_b") (CPTYPE V8QI))
"cpabsa1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpabsa1_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10010 cpabsua1.h crqp,crpp (p0_1)
(dni cpabsua1_h_P1 "cpabsua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsua1_h") (CPTYPE V4HI))
"cpabsua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpabsua1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10011 cpabsla1.h crqp,crpp (p0_1)
(dni cpabsla1_h_P1 "cpabsla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpabsla1_h") (CPTYPE V4HI))
"cpabsla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpabsla1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10100 cpsada1u.b crqp,crpp (p0_1)
(dni cpsada1u_b_P1 "cpsada1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1u_b") (CPTYPE V8UQI))
"cpsada1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsada1u_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10101 cpsada1.b crqp,crpp (p0_1)
(dni cpsada1_b_P1 "cpsada1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsada1_b") (CPTYPE V8QI))
"cpsada1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsada1_b" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10110 cpsadua1.h crqp,crpp (p0_1)
(dni cpsadua1_h_P1 "cpsadua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadua1_h") (CPTYPE V4HI))
"cpsadua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsadua1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 10111 cpsadla1.h crqp,crpp (p0_1)
(dni cpsadla1_h_P1 "cpsadla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsadla1_h") (CPTYPE V4HI))
"cpsadla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsadla1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 11011 cpseta1.h crqp,crpp (p0_1)
(dni cpseta1_h_P1 "cpseta1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpseta1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpseta1_h") (CPTYPE V4HI))
"cpseta1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpseta1_h" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 11100 cpsetua1.w crqp,crpp (p0_1)
(dni cpsetua1_w_P1 "cpsetua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetua1_w") (CPTYPE V2SI))
"cpsetua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsetua1_w" pc crqp crpp) )
()
)
; 00000000 11000 qqqqq ppppp 11101 cpsetla1.w crqp,crpp (p0_1)
(dni cpsetla1_w_P1 "cpsetla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsetla1_w") (CPTYPE V2SI))
"cpsetla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x18) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpsetla1_w" pc crqp crpp) )
()
)
; 00000000 11001 00000 00001 ooooo cpmova1.b =crop (p0_1)
(dni cpmova1_b_P1 "cpmova1.b $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmova1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmova1_b") (CPTYPE V8QI) (CRET FIRST))
"cpmova1.b $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7022,7 +8105,7 @@
; 00000000 11001 00000 00010 ooooo cpmovua1.h =crop (p0_1)
(dni cpmovua1_h_P1 "cpmovua1.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovua1_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovua1.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x2) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7033,7 +8116,7 @@
; 00000000 11001 00000 00011 ooooo cpmovla1.h =crop (p0_1)
(dni cpmovla1_h_P1 "cpmovla1.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovla1_h") (CPTYPE V4HI) (CRET FIRST))
"cpmovla1.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x3) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7044,7 +8127,7 @@
; 00000000 11001 00000 00100 ooooo cpmovuua1.w =crop (p0_1)
(dni cpmovuua1_w_P1 "cpmovuua1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovuua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovuua1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovuua1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x4) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7055,7 +8138,7 @@
; 00000000 11001 00000 00101 ooooo cpmovula1.w =crop (p0_1)
(dni cpmovula1_w_P1 "cpmovula1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovula1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovula1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovula1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x5) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7066,7 +8149,7 @@
; 00000000 11001 00000 00110 ooooo cpmovlua1.w =crop (p0_1)
(dni cpmovlua1_w_P1 "cpmovlua1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlua1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovlua1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x6) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7077,7 +8160,7 @@
; 00000000 11001 00000 00111 ooooo cpmovlla1.w =crop (p0_1)
(dni cpmovlla1_w_P1 "cpmovlla1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovlla1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovlla1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x7) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7088,7 +8171,7 @@
; 00000000 11001 00000 01000 ooooo cppacka1u.b =crop (p0_1)
(dni cppacka1u_b_P1 "cppacka1u.b $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1u_b") (CPTYPE V8UQI) (CRET FIRST))
"cppacka1u.b $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x8) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7099,7 +8182,7 @@
; 00000000 11001 00000 01001 ooooo cppacka1.b =crop (p0_1)
(dni cppacka1_b_P1 "cppacka1.b $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppacka1_b") (CPTYPE V8QI) (CRET FIRST))
"cppacka1.b $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x9) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7110,7 +8193,7 @@
; 00000000 11001 00000 01010 ooooo cppackua1.h =crop (p0_1)
(dni cppackua1_h_P1 "cppackua1.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_h") (CPTYPE V4HI) (CRET FIRST))
"cppackua1.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xa) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7121,7 +8204,7 @@
; 00000000 11001 00000 01011 ooooo cppackla1.h =crop (p0_1)
(dni cppackla1_h_P1 "cppackla1.h $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_h") (CPTYPE V4HI) (CRET FIRST))
"cppackla1.h $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xb) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7132,7 +8215,7 @@
; 00000000 11001 00000 01100 ooooo cppackua1.w =crop (p0_1)
(dni cppackua1_w_P1 "cppackua1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackua1_w") (CPTYPE V2SI) (CRET FIRST))
"cppackua1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xc) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7143,7 +8226,7 @@
; 00000000 11001 00000 01101 ooooo cppackla1.w =crop (p0_1)
(dni cppackla1_w_P1 "cppackla1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cppackla1_w") (CPTYPE V2SI) (CRET FIRST))
"cppackla1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xd) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7154,7 +8237,7 @@
; 00000000 11001 00000 01110 ooooo cpmovhua1.w =crop (p0_1)
(dni cpmovhua1_w_P1 "cpmovhua1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhua1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovhua1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xe) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7165,7 +8248,7 @@
; 00000000 11001 00000 01111 ooooo cpmovhla1.w =crop (p0_1)
(dni cpmovhla1_w_P1 "cpmovhla1.w $crop Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmovhla1_w") (CPTYPE V2SI) (CRET FIRST))
"cpmovhla1.w $crop"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #xf) crop (f-ivc2-4u28 0))
(sequence ()
@@ -7181,6 +8264,15 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x10) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpacsuma1" pc) )
()
)
@@ -7192,17 +8284,41 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x11) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpaccpa1" pc) )
()
)
; 00000000 11001 00000 10010 00000 cpacswp (p0_1)
(dni cpacswp_P1 "cpacswp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacswp"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpacswp") VOLATILE)
"cpacswp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x12) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc0_0 0)
+ (set ivc2_acc0_1 0)
+ (set ivc2_acc0_2 0)
+ (set ivc2_acc0_3 0)
+ (set ivc2_acc0_4 0)
+ (set ivc2_acc0_5 0)
+ (set ivc2_acc0_6 0)
+ (set ivc2_acc0_7 0)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpacswp" pc) )
()
)
@@ -7214,6 +8330,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x18) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsrla1" pc crqp) )
()
)
@@ -7225,6 +8349,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x19) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsraa1" pc crqp) )
()
)
@@ -7236,6 +8368,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) crqp (f-ivc2-5u18 #x1a) (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpslla1" pc crqp) )
()
)
@@ -7247,6 +8387,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1c) imm5p23 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsrlia1" pc imm5p23) )
()
)
@@ -7258,6 +8406,14 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1d) imm5p23 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsraia1" pc imm5p23) )
()
)
@@ -7269,864 +8425,1330 @@
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x19) (f-ivc2-5u13 #x0) (f-ivc2-5u18 #x1e) imm5p23 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpsllia1" pc imm5p23) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00000 cpfmulia1s0u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s0u_b_P1 "cpfmulia1s0u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0u_b") (CPTYPE V8UQI))
"cpfmulia1s0u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmulia1s0u_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00001 cpfmulia1s0.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s0_b_P1 "cpfmulia1s0.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s0_b") (CPTYPE V8QI))
"cpfmulia1s0.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmulia1s0_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00010 cpfmuliua1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmuliua1s0_h_P1 "cpfmuliua1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s0_h") (CPTYPE V4HI))
"cpfmuliua1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x2) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmuliua1s0_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00011 cpfmulila1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmulila1s0_h_P1 "cpfmulila1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s0_h") (CPTYPE V4HI))
"cpfmulila1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x3) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpfmulila1s0_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00100 cpfmadia1s0u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s0u_b_P1 "cpfmadia1s0u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0u_b") (CPTYPE V8UQI))
"cpfmadia1s0u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadia1s0u_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00101 cpfmadia1s0.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s0_b_P1 "cpfmadia1s0.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s0_b") (CPTYPE V8QI))
"cpfmadia1s0.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadia1s0_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00110 cpfmadiua1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadiua1s0_h_P1 "cpfmadiua1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s0_h") (CPTYPE V4HI))
"cpfmadiua1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x6) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadiua1s0_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 00111 cpfmadila1s0.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadila1s0_h_P1 "cpfmadila1s0.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s0_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s0_h") (CPTYPE V4HI))
"cpfmadila1s0.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x7) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadila1s0_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01000 cpfmulia1s1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s1u_b_P1 "cpfmulia1s1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1u_b") (CPTYPE V8UQI))
"cpfmulia1s1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmulia1s1u_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01001 cpfmulia1s1.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmulia1s1_b_P1 "cpfmulia1s1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1s1_b") (CPTYPE V8QI))
"cpfmulia1s1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmulia1s1_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01010 cpfmuliua1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmuliua1s1_h_P1 "cpfmuliua1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1s1_h") (CPTYPE V4HI))
"cpfmuliua1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmuliua1s1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01011 cpfmulila1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmulila1s1_h_P1 "cpfmulila1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1s1_h") (CPTYPE V4HI))
"cpfmulila1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpfmulila1s1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01100 cpfmadia1s1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s1u_b_P1 "cpfmadia1s1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1u_b") (CPTYPE V8UQI))
"cpfmadia1s1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadia1s1u_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01101 cpfmadia1s1.b crqp,crpp,simm8p0 (p0_1)
(dni cpfmadia1s1_b_P1 "cpfmadia1s1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1s1_b") (CPTYPE V8QI))
"cpfmadia1s1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadia1s1_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01110 cpfmadiua1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadiua1s1_h_P1 "cpfmadiua1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1s1_h") (CPTYPE V4HI))
"cpfmadiua1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadiua1s1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 01111 cpfmadila1s1.h crqp,crpp,simm8p0 (p0_1)
(dni cpfmadila1s1_h_P1 "cpfmadila1s1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1s1_h") (CPTYPE V4HI))
"cpfmadila1s1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadila1s1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10000 cpamulia1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpamulia1u_b_P1 "cpamulia1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1u_b") (CPTYPE V8UQI))
"cpamulia1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpamulia1u_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10001 cpamulia1.b crqp,crpp,simm8p0 (p0_1)
(dni cpamulia1_b_P1 "cpamulia1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulia1_b") (CPTYPE V8QI))
"cpamulia1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpamulia1_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10010 cpamuliua1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamuliua1_h_P1 "cpamuliua1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamuliua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamuliua1_h") (CPTYPE V4HI))
"cpamuliua1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpamuliua1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10011 cpamulila1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamulila1_h_P1 "cpamulila1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulila1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamulila1_h") (CPTYPE V4HI))
"cpamulila1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpamulila1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10100 cpamadia1u.b crqp,crpp,simm8p0 (p0_1)
(dni cpamadia1u_b_P1 "cpamadia1u.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1u_b") (CPTYPE V8UQI))
"cpamadia1u.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpamadia1u_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10101 cpamadia1.b crqp,crpp,simm8p0 (p0_1)
(dni cpamadia1_b_P1 "cpamadia1.b $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadia1_b") (CPTYPE V8QI))
"cpamadia1.b $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpamadia1_b" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10110 cpamadiua1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamadiua1_h_P1 "cpamadiua1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadiua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadiua1_h") (CPTYPE V4HI))
"cpamadiua1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpamadiua1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11111 qqqqq ppppp 10111 cpamadila1.h crqp,crpp,simm8p0 (p0_1)
(dni cpamadila1_h_P1 "cpamadila1.h $crqp,$crpp,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadila1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpamadila1_h") (CPTYPE V4HI))
"cpamadila1.h $crqp,$crpp,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1f) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpamadila1_h" pc crqp crpp simm8p0) )
()
)
; iiiiiiii 11100 qqqqq ppppp 00 III cpfmulia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmulia1u_b_P1 "cpfmulia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1u_b") (CPTYPE V8UQI))
"cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmulia1u_b" pc crqp crpp imm3p25 simm8p0) )
()
)
; iiiiiiii 11100 qqqqq ppppp 01 III cpfmulia1.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmulia1_b_P1 "cpfmulia1.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulia1_b") (CPTYPE V8QI))
"cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmulia1_b" pc crqp crpp imm3p25 simm8p0) )
()
)
; iiiiiiii 11100 qqqqq ppppp 10 III cpfmuliua1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmuliua1_h_P1 "cpfmuliua1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmuliua1_h") (CPTYPE V4HI))
"cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpfmuliua1_h" pc crqp crpp imm3p25 simm8p0) )
()
)
; iiiiiiii 11100 qqqqq ppppp 11 III cpfmulila1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmulila1_h_P1 "cpfmulila1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmulila1_h") (CPTYPE V4HI))
"cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1c) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpfmulila1_h" pc crqp crpp imm3p25 simm8p0) )
()
)
; iiiiiiii 11101 qqqqq ppppp 00 III cpfmadia1u.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadia1u_b_P1 "cpfmadia1u.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1u_b") (CPTYPE V8UQI))
"cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x0) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadia1u_b" pc crqp crpp imm3p25 simm8p0) )
()
)
; iiiiiiii 11101 qqqqq ppppp 01 III cpfmadia1.b crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadia1_b_P1 "cpfmadia1.b $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadia1_b") (CPTYPE V8QI))
"cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x1) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadia1_b" pc crqp crpp imm3p25 simm8p0) )
()
)
; iiiiiiii 11101 qqqqq ppppp 10 III cpfmadiua1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadiua1_h_P1 "cpfmadiua1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadiua1_h") (CPTYPE V4HI))
"cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x2) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadiua1_h" pc crqp crpp imm3p25 simm8p0) )
()
)
; iiiiiiii 11101 qqqqq ppppp 11 III cpfmadila1.h crqp,crpp,imm3p25,simm8p0 (cpfm)
(dni cpfmadila1_h_P1 "cpfmadila1.h $crqp,$crpp,imm3p25,simm8p0 Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpfmadila1_h") (CPTYPE V4HI))
"cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0"
(+ simm8p0 (f-ivc2-5u8 #x1d) crqp crpp (f-ivc2-2u23 #x3) imm3p25 (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpfmadila1_h" pc crqp crpp imm3p25 simm8p0) )
()
)
; 00000000 11110 qqqqq ppppp 00000 cpssqa1u.b crqp,crpp (p0_1)
(dni cpssqa1u_b_P1 "cpssqa1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1u_b") (CPTYPE V8UQI))
"cpssqa1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x0) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpssqa1u_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 00001 cpssqa1.b crqp,crpp (p0_1)
(dni cpssqa1_b_P1 "cpssqa1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssqa1_b") (CPTYPE V8QI))
"cpssqa1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpssqa1_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 00100 cpssda1u.b crqp,crpp (p0_1)
(dni cpssda1u_b_P1 "cpssda1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1u_b") (CPTYPE V8UQI))
"cpssda1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x4) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpssda1u_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 00101 cpssda1.b crqp,crpp (p0_1)
(dni cpssda1_b_P1 "cpssda1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpssda1_b") (CPTYPE V8QI))
"cpssda1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x5) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpssda1_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01000 cpmula1u.b crqp,crpp (p0_1)
(dni cpmula1u_b_P1 "cpmula1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1u_b") (CPTYPE V8UQI))
"cpmula1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x8) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmula1u_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01001 cpmula1.b crqp,crpp (p0_1)
(dni cpmula1_b_P1 "cpmula1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmula1_b") (CPTYPE V8QI))
"cpmula1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x9) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmula1_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01010 cpmulua1.h crqp,crpp (p0_1)
(dni cpmulua1_h_P1 "cpmulua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_h") (CPTYPE V4HI))
"cpmulua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmulua1_h" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01011 cpmulla1.h crqp,crpp (p0_1)
(dni cpmulla1_h_P1 "cpmulla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_h") (CPTYPE V4HI))
"cpmulla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpmulla1_h" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01100 cpmulua1u.w crqp,crpp (p0_1)
(dni cpmulua1u_w_P1 "cpmulua1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1u_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1u_w") (CPTYPE V2USI))
"cpmulua1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xc) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmulua1u_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01101 cpmulla1u.w crqp,crpp (p0_1)
(dni cpmulla1u_w_P1 "cpmulla1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1u_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1u_w") (CPTYPE V2USI))
"cpmulla1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xd) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpmulla1u_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01110 cpmulua1.w crqp,crpp (p0_1)
(dni cpmulua1_w_P1 "cpmulua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulua1_w") (CPTYPE V2SI))
"cpmulua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
(c-call "ivc2_cpmulua1_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 01111 cpmulla1.w crqp,crpp (p0_1)
(dni cpmulla1_w_P1 "cpmulla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulla1_w") (CPTYPE V2SI))
"cpmulla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
(c-call "ivc2_cpmulla1_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10000 cpmada1u.b crqp,crpp (p0_1)
(dni cpmada1u_b_P1 "cpmada1u.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1u_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1u_b") (CPTYPE V8UQI))
"cpmada1u.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x10) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmada1u_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10001 cpmada1.b crqp,crpp (p0_1)
(dni cpmada1_b_P1 "cpmada1.b $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1_b"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmada1_b") (CPTYPE V8QI))
"cpmada1.b $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x11) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmada1_b" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10010 cpmadua1.h crqp,crpp (p0_1)
(dni cpmadua1_h_P1 "cpmadua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_h") (CPTYPE V4HI))
"cpmadua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadua1_h" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10011 cpmadla1.h crqp,crpp (p0_1)
(dni cpmadla1_h_P1 "cpmadla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_h") (CPTYPE V4HI))
"cpmadla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadla1_h" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10100 cpmadua1u.w crqp,crpp (p0_1)
(dni cpmadua1u_w_P1 "cpmadua1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1u_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1u_w") (CPTYPE V2USI))
"cpmadua1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x14) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadua1u_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10101 cpmadla1u.w crqp,crpp (p0_1)
(dni cpmadla1u_w_P1 "cpmadla1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1u_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1u_w") (CPTYPE V2USI))
"cpmadla1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x15) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadla1u_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10110 cpmadua1.w crqp,crpp (p0_1)
(dni cpmadua1_w_P1 "cpmadua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadua1_w") (CPTYPE V2SI))
"cpmadua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadua1_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 10111 cpmadla1.w crqp,crpp (p0_1)
(dni cpmadla1_w_P1 "cpmadla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmadla1_w") (CPTYPE V2SI))
"cpmadla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmadla1_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 11010 cpmsbua1.h crqp,crpp (p0_1)
(dni cpmsbua1_h_P1 "cpmsbua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_h") (CPTYPE V4HI))
"cpmsbua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbua1_h" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 11011 cpmsbla1.h crqp,crpp (p0_1)
(dni cpmsbla1_h_P1 "cpmsbla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_h") (CPTYPE V4HI))
"cpmsbla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbla1_h" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 11100 cpmsbua1u.w crqp,crpp (p0_1)
(dni cpmsbua1u_w_P1 "cpmsbua1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1u_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1u_w") (CPTYPE V2USI))
"cpmsbua1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1c) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbua1u_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 11101 cpmsbla1u.w crqp,crpp (p0_1)
(dni cpmsbla1u_w_P1 "cpmsbla1u.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1u_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1u_w") (CPTYPE V2USI))
"cpmsbla1u.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1d) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbla1u_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 11110 cpmsbua1.w crqp,crpp (p0_1)
(dni cpmsbua1_w_P1 "cpmsbua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbua1_w") (CPTYPE V2SI))
"cpmsbua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbua1_w" pc crqp crpp) )
()
)
; 00000000 11110 qqqqq ppppp 11111 cpmsbla1.w crqp,crpp (p0_1)
(dni cpmsbla1_w_P1 "cpmsbla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmsbla1_w") (CPTYPE V2SI))
"cpmsbla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x0) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmsbla1_w" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 10010 cpsmadua1.h crqp,crpp (p0_1)
(dni cpsmadua1_h_P1 "cpsmadua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_h") (CPTYPE V4HI))
"cpsmadua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadua1_h" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 10011 cpsmadla1.h crqp,crpp (p0_1)
(dni cpsmadla1_h_P1 "cpsmadla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_h") (CPTYPE V4HI))
"cpsmadla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadla1_h" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 10110 cpsmadua1.w crqp,crpp (p0_1)
(dni cpsmadua1_w_P1 "cpsmadua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadua1_w") (CPTYPE V2SI))
"cpsmadua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadua1_w" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 10111 cpsmadla1.w crqp,crpp (p0_1)
(dni cpsmadla1_w_P1 "cpsmadla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadla1_w") (CPTYPE V2SI))
"cpsmadla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadla1_w" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 11010 cpsmsbua1.h crqp,crpp (p0_1)
(dni cpsmsbua1_h_P1 "cpsmsbua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_h") (CPTYPE V4HI))
"cpsmsbua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbua1_h" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 11011 cpsmsbla1.h crqp,crpp (p0_1)
(dni cpsmsbla1_h_P1 "cpsmsbla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_h") (CPTYPE V4HI))
"cpsmsbla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbla1_h" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 11110 cpsmsbua1.w crqp,crpp (p0_1)
(dni cpsmsbua1_w_P1 "cpsmsbua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbua1_w") (CPTYPE V2SI))
"cpsmsbua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbua1_w" pc crqp crpp) )
()
)
; 00000001 11110 qqqqq ppppp 11111 cpsmsbla1.w crqp,crpp (p0_1)
(dni cpsmsbla1_w_P1 "cpsmsbla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbla1_w") (CPTYPE V2SI))
"cpsmsbla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x1) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbla1_w" pc crqp crpp) )
()
)
; 00000010 11110 qqqqq ppppp 01010 cpmulslua1.h crqp,crpp (p0_1)
(dni cpmulslua1_h_P1 "cpmulslua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_h") (CPTYPE V4HI))
"cpmulslua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xa) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslua1_h" pc crqp crpp) )
()
)
; 00000010 11110 qqqqq ppppp 01011 cpmulslla1.h crqp,crpp (p0_1)
(dni cpmulslla1_h_P1 "cpmulslla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_h") (CPTYPE V4HI))
"cpmulslla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xb) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslla1_h" pc crqp crpp) )
()
)
; 00000010 11110 qqqqq ppppp 01110 cpmulslua1.w crqp,crpp (p0_1)
(dni cpmulslua1_w_P1 "cpmulslua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslua1_w") (CPTYPE V2SI))
"cpmulslua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xe) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslua1_w" pc crqp crpp) )
()
)
; 00000010 11110 qqqqq ppppp 01111 cpmulslla1.w crqp,crpp (p0_1)
(dni cpmulslla1_w_P1 "cpmulslla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpmulslla1_w") (CPTYPE V2SI))
"cpmulslla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x2) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #xf) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpmulslla1_w" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 10010 cpsmadslua1.h crqp,crpp (p0_1)
(dni cpsmadslua1_h_P1 "cpsmadslua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_h") (CPTYPE V4HI))
"cpsmadslua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x12) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslua1_h" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 10011 cpsmadslla1.h crqp,crpp (p0_1)
(dni cpsmadslla1_h_P1 "cpsmadslla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_h") (CPTYPE V4HI))
"cpsmadslla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x13) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslla1_h" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 10110 cpsmadslua1.w crqp,crpp (p0_1)
(dni cpsmadslua1_w_P1 "cpsmadslua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslua1_w") (CPTYPE V2SI))
"cpsmadslua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x16) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslua1_w" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 10111 cpsmadslla1.w crqp,crpp (p0_1)
(dni cpsmadslla1_w_P1 "cpsmadslla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmadslla1_w") (CPTYPE V2SI))
"cpsmadslla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x17) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmadslla1_w" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 11010 cpsmsbslua1.h crqp,crpp (p0_1)
(dni cpsmsbslua1_h_P1 "cpsmsbslua1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_h") (CPTYPE V4HI))
"cpsmsbslua1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1a) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslua1_h" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 11011 cpsmsbslla1.h crqp,crpp (p0_1)
(dni cpsmsbslla1_h_P1 "cpsmsbslla1.h $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_h"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_h") (CPTYPE V4HI))
"cpsmsbslla1.h $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1b) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslla1_h" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 11110 cpsmsbslua1.w crqp,crpp (p0_1)
(dni cpsmsbslua1_w_P1 "cpsmsbslua1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslua1_w") (CPTYPE V2SI))
"cpsmsbslua1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1e) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_4 0)
+ (set ivc2_acc1_5 0)
+ (set ivc2_acc1_6 0)
+ (set ivc2_acc1_7 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslua1_w" pc crqp crpp) )
()
)
; 00000011 11110 qqqqq ppppp 11111 cpsmsbslla1.w crqp,crpp (p0_1)
(dni cpsmsbslla1_w_P1 "cpsmsbslla1.w $crqp,$crpp Pn"
- (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_w"))
+ (OPTIONAL_CP_INSN ivc2-p1-isa (SLOTS P1) (INTRINSIC "cpsmsbslla1_w") (CPTYPE V2SI))
"cpsmsbslla1.w $crqp,$crpp"
(+ (f-ivc2-8u0 #x3) (f-ivc2-5u8 #x1e) crqp crpp (f-ivc2-5u23 #x1f) (f-ivc2-4u28 0))
(sequence ()
(c-call "check_option_cp" pc)
+ (set ivc2_acc1_0 0)
+ (set ivc2_acc1_1 0)
+ (set ivc2_acc1_2 0)
+ (set ivc2_acc1_3 0)
+ (set ivc2_cofa1 0)
(c-call "ivc2_cpsmsbslla1_w" pc crqp crpp) )
()
)
Index: opcodes/mep-asm.c
===================================================================
RCS file: /cvs/src/src/opcodes/mep-asm.c,v
retrieving revision 1.11
diff -p -U3 -r1.11 mep-asm.c
--- opcodes/mep-asm.c 24 Jun 2009 01:44:53 -0000 1.11
+++ opcodes/mep-asm.c 24 Jun 2009 02:59:28 -0000
@@ -1023,6 +1023,75 @@ mep_cgen_parse_operand (CGEN_CPU_DESC cd
case MEP_OPERAND_IVC_X_6_3 :
errmsg = cgen_parse_unsigned_integer (cd, strp, MEP_OPERAND_IVC_X_6_3, (unsigned long *) (& fields->f_ivc2_3u6));
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & junk);
+ break;
case MEP_OPERAND_IVC2C3CCRN :
errmsg = cgen_parse_keyword (cd, strp, & mep_cgen_opval_h_ccr_ivc2, & fields->f_ivc2_ccrn_c3);
break;
Index: opcodes/mep-desc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mep-desc.c,v
retrieving revision 1.10
diff -p -U3 -r1.10 mep-desc.c
--- opcodes/mep-desc.c 28 May 2009 22:53:08 -0000 1.10
+++ opcodes/mep-desc.c 24 Jun 2009 02:59:28 -0000
@@ -82,6 +82,27 @@ static const CGEN_ATTR_ENTRY CDATA_attr[
{ 0, 0 }
};
+static const CGEN_ATTR_ENTRY CPTYPE_attr[] ATTRIBUTE_UNUSED =
+{
+ { "CP_DATA_BUS_INT", CPTYPE_CP_DATA_BUS_INT },
+ { "VECT", CPTYPE_VECT },
+ { "V2SI", CPTYPE_V2SI },
+ { "V4HI", CPTYPE_V4HI },
+ { "V8QI", CPTYPE_V8QI },
+ { "V2USI", CPTYPE_V2USI },
+ { "V4UHI", CPTYPE_V4UHI },
+ { "V8UQI", CPTYPE_V8UQI },
+ { 0, 0 }
+};
+
+static const CGEN_ATTR_ENTRY CRET_attr[] ATTRIBUTE_UNUSED =
+{
+ { "VOID", CRET_VOID },
+ { "FIRST", CRET_FIRST },
+ { "FIRSTCOPY", CRET_FIRSTCOPY },
+ { 0, 0 }
+};
+
static const CGEN_ATTR_ENTRY ALIGN_attr [] ATTRIBUTE_UNUSED =
{
{"integer", 1},
@@ -103,11 +124,11 @@ static const CGEN_ATTR_ENTRY CONFIG_attr
static const CGEN_ATTR_ENTRY SLOTS_attr[] ATTRIBUTE_UNUSED =
{
- { "core", SLOTS_CORE },
- { "c3", SLOTS_C3 },
- { "p0s", SLOTS_P0S },
- { "p0", SLOTS_P0 },
- { "p1", SLOTS_P1 },
+ { "CORE", SLOTS_CORE },
+ { "C3", SLOTS_C3 },
+ { "P0S", SLOTS_P0S },
+ { "P0", SLOTS_P0 },
+ { "P1", SLOTS_P1 },
{ 0, 0 }
};
@@ -158,6 +179,8 @@ const CGEN_ATTR_TABLE mep_cgen_insn_attr
{
{ "MACH", & MACH_attr[0], & MACH_attr[0] },
{ "ISA", & ISA_attr[0], & ISA_attr[0] },
+ { "CPTYPE", & CPTYPE_attr[0], & CPTYPE_attr[0] },
+ { "CRET", & CRET_attr[0], & CRET_attr[0] },
{ "LATENCY", & LATENCY_attr[0], & LATENCY_attr[0] },
{ "CONFIG", & CONFIG_attr[0], & CONFIG_attr[0] },
{ "SLOTS", & SLOTS_attr[0], & SLOTS_attr[0] },
@@ -1203,18 +1226,110 @@ const CGEN_OPERAND mep_cgen_operand_tabl
{ "cp_flag", MEP_OPERAND_CP_FLAG, HW_H_CCR, 0, 0,
{ 0, { (const PTR) 0 } },
{ 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_csar0: ivc2_csar0 */
+ { "ivc2_csar0", MEP_OPERAND_IVC2_CSAR0, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_cc: ivc2_cc */
+ { "ivc2_cc", MEP_OPERAND_IVC2_CC, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_cofr0: ivc2_cofr0 */
+ { "ivc2_cofr0", MEP_OPERAND_IVC2_COFR0, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_cofr1: ivc2_cofr1 */
+ { "ivc2_cofr1", MEP_OPERAND_IVC2_COFR1, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_cofa0: ivc2_cofa0 */
+ { "ivc2_cofa0", MEP_OPERAND_IVC2_COFA0, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_cofa1: ivc2_cofa1 */
+ { "ivc2_cofa1", MEP_OPERAND_IVC2_COFA1, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_csar1: ivc2_csar1 */
+ { "ivc2_csar1", MEP_OPERAND_IVC2_CSAR1, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_0: acc0_0 */
+ { "ivc2_acc0_0", MEP_OPERAND_IVC2_ACC0_0, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_1: acc0_1 */
+ { "ivc2_acc0_1", MEP_OPERAND_IVC2_ACC0_1, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_2: acc0_2 */
+ { "ivc2_acc0_2", MEP_OPERAND_IVC2_ACC0_2, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_3: acc0_3 */
+ { "ivc2_acc0_3", MEP_OPERAND_IVC2_ACC0_3, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_4: acc0_4 */
+ { "ivc2_acc0_4", MEP_OPERAND_IVC2_ACC0_4, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_5: acc0_5 */
+ { "ivc2_acc0_5", MEP_OPERAND_IVC2_ACC0_5, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_6: acc0_6 */
+ { "ivc2_acc0_6", MEP_OPERAND_IVC2_ACC0_6, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc0_7: acc0_7 */
+ { "ivc2_acc0_7", MEP_OPERAND_IVC2_ACC0_7, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_0: acc1_0 */
+ { "ivc2_acc1_0", MEP_OPERAND_IVC2_ACC1_0, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_1: acc1_1 */
+ { "ivc2_acc1_1", MEP_OPERAND_IVC2_ACC1_1, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_2: acc1_2 */
+ { "ivc2_acc1_2", MEP_OPERAND_IVC2_ACC1_2, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_3: acc1_3 */
+ { "ivc2_acc1_3", MEP_OPERAND_IVC2_ACC1_3, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_4: acc1_4 */
+ { "ivc2_acc1_4", MEP_OPERAND_IVC2_ACC1_4, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_5: acc1_5 */
+ { "ivc2_acc1_5", MEP_OPERAND_IVC2_ACC1_5, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_6: acc1_6 */
+ { "ivc2_acc1_6", MEP_OPERAND_IVC2_ACC1_6, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+/* ivc2_acc1_7: acc1_7 */
+ { "ivc2_acc1_7", MEP_OPERAND_IVC2_ACC1_7, HW_H_CCR_IVC2, 0, 0,
+ { 0, { (const PTR) 0 } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x7c" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
/* croc: $CRo C3 */
{ "croc", MEP_OPERAND_CROC, HW_H_CR64, 7, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U7] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crqc: $CRq C3 */
{ "crqc", MEP_OPERAND_CRQC, HW_H_CR64, 21, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U21] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crpc: $CRp C3 */
{ "crpc", MEP_OPERAND_CRPC, HW_H_CR64, 26, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U26] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc-x-6-1: filler */
{ "ivc-x-6-1", MEP_OPERAND_IVC_X_6_1, HW_H_UINT, 6, 1,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_1U6] } },
@@ -1310,15 +1425,15 @@ const CGEN_OPERAND mep_cgen_operand_tabl
/* crop: $CRo Pn */
{ "crop", MEP_OPERAND_CROP, HW_H_CR64, 23, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U23] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crqp: $CRq Pn */
{ "crqp", MEP_OPERAND_CRQP, HW_H_CR64, 13, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U13] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* crpp: $CRp Pn */
{ "crpp", MEP_OPERAND_CRPP, HW_H_CR64, 18, 5,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_5U18] } },
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_LONG, 0 } }, { { 1, 0 } } } } },
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xfc" } }, { { CDATA_CP_DATA_BUS_INT, 0 } }, { { 1, 0 } } } } },
/* ivc-x-0-2: filler */
{ "ivc-x-0-2", MEP_OPERAND_IVC_X_0_2, HW_H_UINT, 0, 2,
{ 0, { (const PTR) &mep_cgen_ifld_table[MEP_F_IVC2_2U0] } },
@@ -1382,4571 +1497,4571 @@ static const CGEN_IBASE mep_cgen_insn_ta
/* Special null first entry.
A `num' value of zero is thus invalid.
Also, the special `invalid' insn resides here. */
- { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } } },
+ { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } } },
/* stcb $rn,($rma) */
{
MEP_INSN_STCB_R, "stcb_r", "stcb", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ldcb $rn,($rma) */
{
MEP_INSN_LDCB_R, "ldcb_r", "ldcb", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* pref $cimm4,($rma) */
{
MEP_INSN_PREF, "pref", "pref", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* pref $cimm4,$sdisp16($rma) */
{
MEP_INSN_PREFD, "prefd", "pref", 32,
- { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* casb3 $rl5,$rn,($rm) */
{
MEP_INSN_CASB3, "casb3", "casb3", 32,
- { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* cash3 $rl5,$rn,($rm) */
{
MEP_INSN_CASH3, "cash3", "cash3", 32,
- { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* casw3 $rl5,$rn,($rm) */
{
MEP_INSN_CASW3, "casw3", "casw3", 32,
- { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sbcp $crn,$cdisp12($rma) */
{
MEP_INSN_SBCP, "sbcp", "sbcp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbcp $crn,$cdisp12($rma) */
{
MEP_INSN_LBCP, "lbcp", "lbcp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbucp $crn,$cdisp12($rma) */
{
MEP_INSN_LBUCP, "lbucp", "lbucp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* shcp $crn,$cdisp12($rma) */
{
MEP_INSN_SHCP, "shcp", "shcp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhcp $crn,$cdisp12($rma) */
{
MEP_INSN_LHCP, "lhcp", "lhcp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhucp $crn,$cdisp12($rma) */
{
MEP_INSN_LHUCP, "lhucp", "lhucp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbucpa $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBUCPA, "lbucpa", "lbucpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhucpa $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHUCPA, "lhucpa", "lhucpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbucpm0 $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBUCPM0, "lbucpm0", "lbucpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhucpm0 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHUCPM0, "lhucpm0", "lhucpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbucpm1 $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBUCPM1, "lbucpm1", "lbucpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhucpm1 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHUCPM1, "lhucpm1", "lhucpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* uci $rn,$rm,$uimm16 */
{
MEP_INSN_UCI, "uci", "uci", 32,
- { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* dsp $rn,$rm,$uimm16 */
{
MEP_INSN_DSP, "dsp", "dsp", 32,
- { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* dsp0 $c5rnmuimm24 */
{
-1, "dsp0", "dsp0", 32,
- { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* dsp1 $rn,$c5rmuimm20 */
{
-1, "dsp1", "dsp1", 32,
- { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(ALIAS)|A(NO_DIS)|A(VOLATILE), { { { (1<<MACH_C5), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sb $rnc,($rma) */
{
MEP_INSN_SB, "sb", "sb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sh $rns,($rma) */
{
MEP_INSN_SH, "sh", "sh", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rnl,($rma) */
{
MEP_INSN_SW, "sw", "sw", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lb $rnc,($rma) */
{
MEP_INSN_LB, "lb", "lb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lh $rns,($rma) */
{
MEP_INSN_LH, "lh", "lh", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rnl,($rma) */
{
MEP_INSN_LW, "lw", "lw", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbu $rnuc,($rma) */
{
MEP_INSN_LBU, "lbu", "lbu", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhu $rnus,($rma) */
{
MEP_INSN_LHU, "lhu", "lhu", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rnl,$udisp7a4($spr) */
{
MEP_INSN_SW_SP, "sw-sp", "sw", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rnl,$udisp7a4($spr) */
{
MEP_INSN_LW_SP, "lw-sp", "lw", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sb $rn3c,$udisp7($tpr) */
{
MEP_INSN_SB_TP, "sb-tp", "sb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sh $rn3s,$udisp7a2($tpr) */
{
MEP_INSN_SH_TP, "sh-tp", "sh", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rn3l,$udisp7a4($tpr) */
{
MEP_INSN_SW_TP, "sw-tp", "sw", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lb $rn3c,$udisp7($tpr) */
{
MEP_INSN_LB_TP, "lb-tp", "lb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lh $rn3s,$udisp7a2($tpr) */
{
MEP_INSN_LH_TP, "lh-tp", "lh", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rn3l,$udisp7a4($tpr) */
{
MEP_INSN_LW_TP, "lw-tp", "lw", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbu $rn3uc,$udisp7($tpr) */
{
MEP_INSN_LBU_TP, "lbu-tp", "lbu", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhu $rn3us,$udisp7a2($tpr) */
{
MEP_INSN_LHU_TP, "lhu-tp", "lhu", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sb $rnc,$sdisp16($rma) */
{
MEP_INSN_SB16, "sb16", "sb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sh $rns,$sdisp16($rma) */
{
MEP_INSN_SH16, "sh16", "sh", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rnl,$sdisp16($rma) */
{
MEP_INSN_SW16, "sw16", "sw", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lb $rnc,$sdisp16($rma) */
{
MEP_INSN_LB16, "lb16", "lb", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lh $rns,$sdisp16($rma) */
{
MEP_INSN_LH16, "lh16", "lh", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rnl,$sdisp16($rma) */
{
MEP_INSN_LW16, "lw16", "lw", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbu $rnuc,$sdisp16($rma) */
{
MEP_INSN_LBU16, "lbu16", "lbu", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhu $rnus,$sdisp16($rma) */
{
MEP_INSN_LHU16, "lhu16", "lhu", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rnl,($addr24a4) */
{
MEP_INSN_SW24, "sw24", "sw", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rnl,($addr24a4) */
{
MEP_INSN_LW24, "lw24", "lw", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* extb $rn */
{
MEP_INSN_EXTB, "extb", "extb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* exth $rn */
{
MEP_INSN_EXTH, "exth", "exth", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* extub $rn */
{
MEP_INSN_EXTUB, "extub", "extub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* extuh $rn */
{
MEP_INSN_EXTUH, "extuh", "extuh", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ssarb $udisp2($rm) */
{
MEP_INSN_SSARB, "ssarb", "ssarb", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* mov $rn,$rm */
{
MEP_INSN_MOV, "mov", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* mov $rn,$simm8 */
{
MEP_INSN_MOVI8, "movi8", "mov", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* mov $rn,$simm16 */
{
MEP_INSN_MOVI16, "movi16", "mov", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* movu $rn3,$uimm24 */
{
MEP_INSN_MOVU24, "movu24", "movu", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* movu $rn,$uimm16 */
{
MEP_INSN_MOVU16, "movu16", "movu", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* movh $rn,$uimm16 */
{
MEP_INSN_MOVH, "movh", "movh", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* add3 $rl,$rn,$rm */
{
MEP_INSN_ADD3, "add3", "add3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* add $rn,$simm6 */
{
MEP_INSN_ADD, "add", "add", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* add3 $rn,$spr,$uimm7a4 */
{
MEP_INSN_ADD3I, "add3i", "add3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* advck3 \$0,$rn,$rm */
{
MEP_INSN_ADVCK3, "advck3", "advck3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sub $rn,$rm */
{
MEP_INSN_SUB, "sub", "sub", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sbvck3 \$0,$rn,$rm */
{
MEP_INSN_SBVCK3, "sbvck3", "sbvck3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* neg $rn,$rm */
{
MEP_INSN_NEG, "neg", "neg", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* slt3 \$0,$rn,$rm */
{
MEP_INSN_SLT3, "slt3", "slt3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sltu3 \$0,$rn,$rm */
{
MEP_INSN_SLTU3, "sltu3", "sltu3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* slt3 \$0,$rn,$uimm5 */
{
MEP_INSN_SLT3I, "slt3i", "slt3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sltu3 \$0,$rn,$uimm5 */
{
MEP_INSN_SLTU3I, "sltu3i", "sltu3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sl1ad3 \$0,$rn,$rm */
{
MEP_INSN_SL1AD3, "sl1ad3", "sl1ad3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sl2ad3 \$0,$rn,$rm */
{
MEP_INSN_SL2AD3, "sl2ad3", "sl2ad3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* add3 $rn,$rm,$simm16 */
{
MEP_INSN_ADD3X, "add3x", "add3", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* slt3 $rn,$rm,$simm16 */
{
MEP_INSN_SLT3X, "slt3x", "slt3", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sltu3 $rn,$rm,$uimm16 */
{
MEP_INSN_SLTU3X, "sltu3x", "sltu3", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* or $rn,$rm */
{
MEP_INSN_OR, "or", "or", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* and $rn,$rm */
{
MEP_INSN_AND, "and", "and", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* xor $rn,$rm */
{
MEP_INSN_XOR, "xor", "xor", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* nor $rn,$rm */
{
MEP_INSN_NOR, "nor", "nor", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* or3 $rn,$rm,$uimm16 */
{
MEP_INSN_OR3, "or3", "or3", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* and3 $rn,$rm,$uimm16 */
{
MEP_INSN_AND3, "and3", "and3", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* xor3 $rn,$rm,$uimm16 */
{
MEP_INSN_XOR3, "xor3", "xor3", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sra $rn,$rm */
{
MEP_INSN_SRA, "sra", "sra", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* srl $rn,$rm */
{
MEP_INSN_SRL, "srl", "srl", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sll $rn,$rm */
{
MEP_INSN_SLL, "sll", "sll", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sra $rn,$uimm5 */
{
MEP_INSN_SRAI, "srai", "sra", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* srl $rn,$uimm5 */
{
MEP_INSN_SRLI, "srli", "srl", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sll $rn,$uimm5 */
{
MEP_INSN_SLLI, "slli", "sll", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sll3 \$0,$rn,$uimm5 */
{
MEP_INSN_SLL3, "sll3", "sll3", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* fsft $rn,$rm */
{
MEP_INSN_FSFT, "fsft", "fsft", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bra $pcrel12a2 */
{
MEP_INSN_BRA, "bra", "bra", 16,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* beqz $rn,$pcrel8a2 */
{
MEP_INSN_BEQZ, "beqz", "beqz", 16,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bnez $rn,$pcrel8a2 */
{
MEP_INSN_BNEZ, "bnez", "bnez", 16,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* beqi $rn,$uimm4,$pcrel17a2 */
{
MEP_INSN_BEQI, "beqi", "beqi", 32,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bnei $rn,$uimm4,$pcrel17a2 */
{
MEP_INSN_BNEI, "bnei", "bnei", 32,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* blti $rn,$uimm4,$pcrel17a2 */
{
MEP_INSN_BLTI, "blti", "blti", 32,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bgei $rn,$uimm4,$pcrel17a2 */
{
MEP_INSN_BGEI, "bgei", "bgei", 32,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* beq $rn,$rm,$pcrel17a2 */
{
MEP_INSN_BEQ, "beq", "beq", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bne $rn,$rm,$pcrel17a2 */
{
MEP_INSN_BNE, "bne", "bne", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bsr $pcrel12a2 */
{
MEP_INSN_BSR12, "bsr12", "bsr", 16,
- { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bsr $pcrel24a2 */
{
MEP_INSN_BSR24, "bsr24", "bsr", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* jmp $rm */
{
MEP_INSN_JMP, "jmp", "jmp", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* jmp $pcabs24a2 */
{
MEP_INSN_JMP24, "jmp24", "jmp", 32,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* jsr $rm */
{
MEP_INSN_JSR, "jsr", "jsr", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ret */
{
MEP_INSN_RET, "ret", "ret", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* repeat $rn,$pcrel17a2 */
{
MEP_INSN_REPEAT, "repeat", "repeat", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* erepeat $pcrel17a2 */
{
MEP_INSN_EREPEAT, "erepeat", "erepeat", 32,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* stc $rn,\$lp */
{
MEP_INSN_STC_LP, "stc_lp", "stc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* stc $rn,\$hi */
{
MEP_INSN_STC_HI, "stc_hi", "stc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* stc $rn,\$lo */
{
MEP_INSN_STC_LO, "stc_lo", "stc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* stc $rn,$csrn */
{
MEP_INSN_STC, "stc", "stc", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ldc $rn,\$lp */
{
MEP_INSN_LDC_LP, "ldc_lp", "ldc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ldc $rn,\$hi */
{
MEP_INSN_LDC_HI, "ldc_hi", "ldc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ldc $rn,\$lo */
{
MEP_INSN_LDC_LO, "ldc_lo", "ldc", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ldc $rn,$csrn */
{
MEP_INSN_LDC, "ldc", "ldc", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 2, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* di */
{
MEP_INSN_DI, "di", "di", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ei */
{
MEP_INSN_EI, "ei", "ei", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* reti */
{
MEP_INSN_RETI, "reti", "reti", 16,
- { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* halt */
{
MEP_INSN_HALT, "halt", "halt", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sleep */
{
MEP_INSN_SLEEP, "sleep", "sleep", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swi $uimm2 */
{
MEP_INSN_SWI, "swi", "swi", 16,
- { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE)|A(MAY_TRAP), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* break */
{
MEP_INSN_BREAK, "break", "break", 16,
- { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE)|A(MAY_TRAP)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* syncm */
{
MEP_INSN_SYNCM, "syncm", "syncm", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* stcb $rn,$uimm16 */
{
MEP_INSN_STCB, "stcb", "stcb", 32,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ldcb $rn,$uimm16 */
{
MEP_INSN_LDCB, "ldcb", "ldcb", 32,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bsetm ($rma),$uimm3 */
{
MEP_INSN_BSETM, "bsetm", "bsetm", 16,
- { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bclrm ($rma),$uimm3 */
{
MEP_INSN_BCLRM, "bclrm", "bclrm", 16,
- { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bnotm ($rma),$uimm3 */
{
MEP_INSN_BNOTM, "bnotm", "bnotm", 16,
- { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* btstm \$0,($rma),$uimm3 */
{
MEP_INSN_BTSTM, "btstm", "btstm", 16,
- { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* tas $rn,($rma) */
{
MEP_INSN_TAS, "tas", "tas", 16,
- { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_BIT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* cache $cimm4,($rma) */
{
MEP_INSN_CACHE, "cache", "cache", 16,
- { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* mul $rn,$rm */
{
MEP_INSN_MUL, "mul", "mul", 16,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* mulu $rn,$rm */
{
MEP_INSN_MULU, "mulu", "mulu", 16,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* mulr $rn,$rm */
{
MEP_INSN_MULR, "mulr", "mulr", 16,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* mulru $rn,$rm */
{
MEP_INSN_MULRU, "mulru", "mulru", 16,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* madd $rn,$rm */
{
MEP_INSN_MADD, "madd", "madd", 32,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* maddu $rn,$rm */
{
MEP_INSN_MADDU, "maddu", "maddu", 32,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* maddr $rn,$rm */
{
MEP_INSN_MADDR, "maddr", "maddr", 32,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* maddru $rn,$rm */
{
MEP_INSN_MADDRU, "maddru", "maddru", 32,
- { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MUL_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 3, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* div $rn,$rm */
{
MEP_INSN_DIV, "div", "div", 16,
- { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* divu $rn,$rm */
{
MEP_INSN_DIVU, "divu", "divu", 16,
- { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(MAY_TRAP)|A(OPTIONAL_DIV_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 34, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* dret */
{
MEP_INSN_DRET, "dret", "dret", 16,
- { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_DEBUG_INSN)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* dbreak */
{
MEP_INSN_DBREAK, "dbreak", "dbreak", 16,
- { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(VOLATILE)|A(MAY_TRAP)|A(OPTIONAL_DEBUG_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ldz $rn,$rm */
{
MEP_INSN_LDZ, "ldz", "ldz", 32,
- { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_LDZ_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* abs $rn,$rm */
{
MEP_INSN_ABS, "abs", "abs", 32,
- { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_ABS_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ave $rn,$rm */
{
MEP_INSN_AVE, "ave", "ave", 32,
- { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_AVE_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* min $rn,$rm */
{
MEP_INSN_MIN, "min", "min", 32,
- { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* max $rn,$rm */
{
MEP_INSN_MAX, "max", "max", 32,
- { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* minu $rn,$rm */
{
MEP_INSN_MINU, "minu", "minu", 32,
- { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* maxu $rn,$rm */
{
MEP_INSN_MAXU, "maxu", "maxu", 32,
- { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_MINMAX_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* clip $rn,$cimm5 */
{
MEP_INSN_CLIP, "clip", "clip", 32,
- { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* clipu $rn,$cimm5 */
{
MEP_INSN_CLIPU, "clipu", "clipu", 32,
- { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CLIP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sadd $rn,$rm */
{
MEP_INSN_SADD, "sadd", "sadd", 32,
- { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ssub $rn,$rm */
{
MEP_INSN_SSUB, "ssub", "ssub", 32,
- { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* saddu $rn,$rm */
{
MEP_INSN_SADDU, "saddu", "saddu", 32,
- { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* ssubu $rn,$rm */
{
MEP_INSN_SSUBU, "ssubu", "ssubu", 32,
- { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_SAT_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcp $crn,($rma) */
{
MEP_INSN_SWCP, "swcp", "swcp", 16,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcp $crn,($rma) */
{
MEP_INSN_LWCP, "lwcp", "lwcp", 16,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcp $crn64,($rma) */
{
MEP_INSN_SMCP, "smcp", "smcp", 16,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcp $crn64,($rma) */
{
MEP_INSN_LMCP, "lmcp", "lmcp", 16,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcpi $crn,($rma+) */
{
MEP_INSN_SWCPI, "swcpi", "swcpi", 16,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcpi $crn,($rma+) */
{
MEP_INSN_LWCPI, "lwcpi", "lwcpi", 16,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcpi $crn64,($rma+) */
{
MEP_INSN_SMCPI, "smcpi", "smcpi", 16,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcpi $crn64,($rma+) */
{
MEP_INSN_LMCPI, "lmcpi", "lmcpi", 16,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcp $crn,$sdisp16($rma) */
{
MEP_INSN_SWCP16, "swcp16", "swcp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcp $crn,$sdisp16($rma) */
{
MEP_INSN_LWCP16, "lwcp16", "lwcp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcp $crn64,$sdisp16($rma) */
{
MEP_INSN_SMCP16, "smcp16", "smcp", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcp $crn64,$sdisp16($rma) */
{
MEP_INSN_LMCP16, "lmcp16", "lmcp", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sbcpa $crn,($rma+),$cdisp10 */
{
MEP_INSN_SBCPA, "sbcpa", "sbcpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbcpa $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBCPA, "lbcpa", "lbcpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* shcpa $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_SHCPA, "shcpa", "shcpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhcpa $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHCPA, "lhcpa", "lhcpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcpa $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_SWCPA, "swcpa", "swcpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcpa $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_LWCPA, "lwcpa", "lwcpa", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcpa $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_SMCPA, "smcpa", "smcpa", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcpa $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_LMCPA, "lmcpa", "lmcpa", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sbcpm0 $crn,($rma+),$cdisp10 */
{
MEP_INSN_SBCPM0, "sbcpm0", "sbcpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbcpm0 $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBCPM0, "lbcpm0", "lbcpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* shcpm0 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_SHCPM0, "shcpm0", "shcpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhcpm0 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHCPM0, "lhcpm0", "lhcpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcpm0 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_SWCPM0, "swcpm0", "swcpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcpm0 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_LWCPM0, "lwcpm0", "lwcpm0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcpm0 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_SMCPM0, "smcpm0", "smcpm0", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcpm0 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_LMCPM0, "lmcpm0", "lmcpm0", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sbcpm1 $crn,($rma+),$cdisp10 */
{
MEP_INSN_SBCPM1, "sbcpm1", "sbcpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbcpm1 $crn,($rma+),$cdisp10 */
{
MEP_INSN_LBCPM1, "lbcpm1", "lbcpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* shcpm1 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_SHCPM1, "shcpm1", "shcpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhcpm1 $crn,($rma+),$cdisp10a2 */
{
MEP_INSN_LHCPM1, "lhcpm1", "lhcpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcpm1 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_SWCPM1, "swcpm1", "swcpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcpm1 $crn,($rma+),$cdisp10a4 */
{
MEP_INSN_LWCPM1, "lwcpm1", "lwcpm1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcpm1 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_SMCPM1, "smcpm1", "smcpm1", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcpm1 $crn64,($rma+),$cdisp10a8 */
{
MEP_INSN_LMCPM1, "lmcpm1", "lmcpm1", 32,
- { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bcpeq $cccc,$pcrel17a2 */
{
MEP_INSN_BCPEQ, "bcpeq", "bcpeq", 32,
- { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bcpne $cccc,$pcrel17a2 */
{
MEP_INSN_BCPNE, "bcpne", "bcpne", 32,
- { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bcpat $cccc,$pcrel17a2 */
{
MEP_INSN_BCPAT, "bcpat", "bcpat", 32,
- { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bcpaf $cccc,$pcrel17a2 */
{
MEP_INSN_BCPAF, "bcpaf", "bcpaf", 32,
- { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(RELAXABLE)|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* synccp */
{
MEP_INSN_SYNCCP, "synccp", "synccp", 16,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* jsrv $rm */
{
MEP_INSN_JSRV, "jsrv", "jsrv", 16,
- { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* bsrv $pcrel24a2 */
{
MEP_INSN_BSRV, "bsrv", "bsrv", 32,
- { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --syscall-- */
{
MEP_INSN_SIM_SYSCALL, "sim-syscall", "--syscall--", 16,
- { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_0, "ri-0", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_1, "ri-1", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_2, "ri-2", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_3, "ri-3", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_4, "ri-4", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_5, "ri-5", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_6, "ri-6", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_7, "ri-7", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_8, "ri-8", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_9, "ri-9", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_10, "ri-10", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_11, "ri-11", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_12, "ri-12", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_13, "ri-13", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_14, "ri-14", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_15, "ri-15", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_17, "ri-17", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_20, "ri-20", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_21, "ri-21", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_22, "ri-22", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_23, "ri-23", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* --reserved-- */
{
MEP_INSN_RI_26, "ri-26", "--reserved--", 16,
- { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* cmov $crnx64,$rm */
{
MEP_INSN_CMOV_CRN_RM, "cmov-crn-rm", "cmov", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cmov $rm,$crnx64 */
{
MEP_INSN_CMOV_RN_CRM, "cmov-rn-crm", "cmov", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cmovc $ivc2c3ccrn,$rm */
{
MEP_INSN_CMOVC_CCRN_RM, "cmovc-ccrn-rm", "cmovc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cmovc $rm,$ivc2c3ccrn */
{
MEP_INSN_CMOVC_RN_CCRM, "cmovc-rn-ccrm", "cmovc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cmovh $crnx64,$rm */
{
MEP_INSN_CMOVH_CRN_RM, "cmovh-crn-rm", "cmovh", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cmovh $rm,$crnx64 */
{
MEP_INSN_CMOVH_RN_CRM, "cmovh-rn-crm", "cmovh", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cmov $ivc2crn,$ivc2rm */
{
MEP_INSN_CMOV_CRN_RM_P0, "cmov-crn-rm-p0", "cmov", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
},
/* cmov $ivc2rm,$ivc2crn */
{
MEP_INSN_CMOV_RN_CRM_P0, "cmov-rn-crm-p0", "cmov", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
},
/* cmovc $ivc2ccrn,$ivc2rm */
{
MEP_INSN_CMOVC_CCRN_RM_P0, "cmovc-ccrn-rm-p0", "cmovc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
},
/* cmovc $ivc2rm,$ivc2ccrn */
{
MEP_INSN_CMOVC_RN_CCRM_P0, "cmovc-rn-ccrm-p0", "cmovc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
},
/* cmovh $ivc2crn,$ivc2rm */
{
MEP_INSN_CMOVH_CRN_RM_P0, "cmovh-crn-rm-p0", "cmovh", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
},
/* cmovh $ivc2rm,$ivc2crn */
{
MEP_INSN_CMOVH_RN_CRM_P0, "cmovh-rn-crm-p0", "cmovh", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x8" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0), 0 } } } }
},
/* cpadd3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPADD3_B_C3, "cpadd3_b_C3", "cpadd3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpadd3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPADD3_H_C3, "cpadd3_h_C3", "cpadd3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpadd3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPADD3_W_C3, "cpadd3_w_C3", "cpadd3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdadd3 $croc,$crqc,$crpc */
{
MEP_INSN_CDADD3_C3, "cdadd3_C3", "cdadd3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsub3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPSUB3_B_C3, "cpsub3_b_C3", "cpsub3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsub3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSUB3_H_C3, "cpsub3_h_C3", "cpsub3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsub3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSUB3_W_C3, "cpsub3_w_C3", "cpsub3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdsub3 $croc,$crqc,$crpc */
{
MEP_INSN_CDSUB3_C3, "cdsub3_C3", "cdsub3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpand3 $croc,$crqc,$crpc */
{
MEP_INSN_CPAND3_C3, "cpand3_C3", "cpand3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpor3 $croc,$crqc,$crpc */
{
MEP_INSN_CPOR3_C3, "cpor3_C3", "cpor3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpnor3 $croc,$crqc,$crpc */
{
MEP_INSN_CPNOR3_C3, "cpnor3_C3", "cpnor3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpxor3 $croc,$crqc,$crpc */
{
MEP_INSN_CPXOR3_C3, "cpxor3_C3", "cpxor3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsel $croc,$crqc,$crpc */
{
MEP_INSN_CPSEL_C3, "cpsel_C3", "cpsel", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpfsftbi $croc,$crqc,$crpc,$imm3p4 */
{
MEP_INSN_CPFSFTBI_C3, "cpfsftbi_C3", "cpfsftbi", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpfsftbs0 $croc,$crqc,$crpc */
{
MEP_INSN_CPFSFTBS0_C3, "cpfsftbs0_C3", "cpfsftbs0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpfsftbs1 $croc,$crqc,$crpc */
{
MEP_INSN_CPFSFTBS1_C3, "cpfsftbs1_C3", "cpfsftbs1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpunpacku.b $croc,$crqc,$crpc */
{
MEP_INSN_CPUNPACKU_B_C3, "cpunpacku_b_C3", "cpunpacku.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpunpacku.h $croc,$crqc,$crpc */
{
MEP_INSN_CPUNPACKU_H_C3, "cpunpacku_h_C3", "cpunpacku.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpunpacku.w $croc,$crqc,$crpc */
{
MEP_INSN_CPUNPACKU_W_C3, "cpunpacku_w_C3", "cpunpacku.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpunpackl.b $croc,$crqc,$crpc */
{
MEP_INSN_CPUNPACKL_B_C3, "cpunpackl_b_C3", "cpunpackl.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpunpackl.h $croc,$crqc,$crpc */
{
MEP_INSN_CPUNPACKL_H_C3, "cpunpackl_h_C3", "cpunpackl.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpunpackl.w $croc,$crqc,$crpc */
{
MEP_INSN_CPUNPACKL_W_C3, "cpunpackl_w_C3", "cpunpackl.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppacku.b $croc,$crqc,$crpc */
{
MEP_INSN_CPPACKU_B_C3, "cppacku_b_C3", "cppacku.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppack.b $croc,$crqc,$crpc */
{
MEP_INSN_CPPACK_B_C3, "cppack_b_C3", "cppack.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppack.h $croc,$crqc,$crpc */
{
MEP_INSN_CPPACK_H_C3, "cppack_h_C3", "cppack.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrl3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPSRL3_B_C3, "cpsrl3_b_C3", "cpsrl3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssrl3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPSSRL3_B_C3, "cpssrl3_b_C3", "cpssrl3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrl3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSRL3_H_C3, "cpsrl3_h_C3", "cpsrl3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssrl3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSSRL3_H_C3, "cpssrl3_h_C3", "cpssrl3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrl3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSRL3_W_C3, "cpsrl3_w_C3", "cpsrl3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssrl3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSSRL3_W_C3, "cpssrl3_w_C3", "cpssrl3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdsrl3 $croc,$crqc,$crpc */
{
MEP_INSN_CDSRL3_C3, "cdsrl3_C3", "cdsrl3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsra3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPSRA3_B_C3, "cpsra3_b_C3", "cpsra3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssra3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPSSRA3_B_C3, "cpssra3_b_C3", "cpssra3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsra3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSRA3_H_C3, "cpsra3_h_C3", "cpsra3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssra3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSSRA3_H_C3, "cpssra3_h_C3", "cpssra3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsra3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSRA3_W_C3, "cpsra3_w_C3", "cpsra3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssra3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSSRA3_W_C3, "cpssra3_w_C3", "cpssra3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdsra3 $croc,$crqc,$crpc */
{
MEP_INSN_CDSRA3_C3, "cdsra3_C3", "cdsra3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsll3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPSLL3_B_C3, "cpsll3_b_C3", "cpsll3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssll3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPSSLL3_B_C3, "cpssll3_b_C3", "cpssll3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsll3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSLL3_H_C3, "cpsll3_h_C3", "cpsll3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssll3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSSLL3_H_C3, "cpssll3_h_C3", "cpssll3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsll3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSLL3_W_C3, "cpsll3_w_C3", "cpsll3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssll3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSSLL3_W_C3, "cpssll3_w_C3", "cpssll3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdsll3 $croc,$crqc,$crpc */
{
MEP_INSN_CDSLL3_C3, "cdsll3_C3", "cdsll3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsla3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSLA3_H_C3, "cpsla3_h_C3", "cpsla3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsla3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSLA3_W_C3, "cpsla3_w_C3", "cpsla3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsadd3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSADD3_H_C3, "cpsadd3_h_C3", "cpsadd3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsadd3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSADD3_W_C3, "cpsadd3_w_C3", "cpsadd3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssub3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPSSUB3_H_C3, "cpssub3_h_C3", "cpssub3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssub3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPSSUB3_W_C3, "cpssub3_w_C3", "cpssub3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextuaddu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTUADDU3_B_C3, "cpextuaddu3_b_C3", "cpextuaddu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextuadd3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTUADD3_B_C3, "cpextuadd3_b_C3", "cpextuadd3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextladdu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTLADDU3_B_C3, "cpextladdu3_b_C3", "cpextladdu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextladd3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTLADD3_B_C3, "cpextladd3_b_C3", "cpextladd3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextusubu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTUSUBU3_B_C3, "cpextusubu3_b_C3", "cpextusubu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextusub3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTUSUB3_B_C3, "cpextusub3_b_C3", "cpextusub3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextlsubu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTLSUBU3_B_C3, "cpextlsubu3_b_C3", "cpextlsubu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextlsub3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPEXTLSUB3_B_C3, "cpextlsub3_b_C3", "cpextlsub3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaveu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPAVEU3_B_C3, "cpaveu3_b_C3", "cpaveu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpave3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPAVE3_B_C3, "cpave3_b_C3", "cpave3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpave3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPAVE3_H_C3, "cpave3_h_C3", "cpave3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpave3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPAVE3_W_C3, "cpave3_w_C3", "cpave3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddsru3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPADDSRU3_B_C3, "cpaddsru3_b_C3", "cpaddsru3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddsr3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPADDSR3_B_C3, "cpaddsr3_b_C3", "cpaddsr3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddsr3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPADDSR3_H_C3, "cpaddsr3_h_C3", "cpaddsr3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddsr3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPADDSR3_W_C3, "cpaddsr3_w_C3", "cpaddsr3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPABSU3_B_C3, "cpabsu3_b_C3", "cpabsu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabs3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPABS3_B_C3, "cpabs3_b_C3", "cpabs3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabs3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPABS3_H_C3, "cpabs3_h_C3", "cpabs3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmaxu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPMAXU3_B_C3, "cpmaxu3_b_C3", "cpmaxu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmax3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPMAX3_B_C3, "cpmax3_b_C3", "cpmax3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmax3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPMAX3_H_C3, "cpmax3_h_C3", "cpmax3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmaxu3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPMAXU3_W_C3, "cpmaxu3_w_C3", "cpmaxu3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmax3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPMAX3_W_C3, "cpmax3_w_C3", "cpmax3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpminu3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPMINU3_B_C3, "cpminu3_b_C3", "cpminu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmin3.b $croc,$crqc,$crpc */
{
MEP_INSN_CPMIN3_B_C3, "cpmin3_b_C3", "cpmin3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmin3.h $croc,$crqc,$crpc */
{
MEP_INSN_CPMIN3_H_C3, "cpmin3_h_C3", "cpmin3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpminu3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPMINU3_W_C3, "cpminu3_w_C3", "cpminu3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmin3.w $croc,$crqc,$crpc */
{
MEP_INSN_CPMIN3_W_C3, "cpmin3_w_C3", "cpmin3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovfrcsar0 $croc */
{
MEP_INSN_CPMOVFRCSAR0_C3, "cpmovfrcsar0_C3", "cpmovfrcsar0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovfrcsar1 $croc */
{
MEP_INSN_CPMOVFRCSAR1_C3, "cpmovfrcsar1_C3", "cpmovfrcsar1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovfrcc $croc */
{
MEP_INSN_CPMOVFRCC_C3, "cpmovfrcc_C3", "cpmovfrcc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovtocsar0 $crqc */
{
MEP_INSN_CPMOVTOCSAR0_C3, "cpmovtocsar0_C3", "cpmovtocsar0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovtocsar1 $crqc */
{
MEP_INSN_CPMOVTOCSAR1_C3, "cpmovtocsar1_C3", "cpmovtocsar1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovtocc $crqc */
{
MEP_INSN_CPMOVTOCC_C3, "cpmovtocc_C3", "cpmovtocc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmov $croc,$crqc */
{
MEP_INSN_CPMOV_C3, "cpmov_C3", "cpmov", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsz.b $croc,$crqc */
{
MEP_INSN_CPABSZ_B_C3, "cpabsz_b_C3", "cpabsz.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsz.h $croc,$crqc */
{
MEP_INSN_CPABSZ_H_C3, "cpabsz_h_C3", "cpabsz.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsz.w $croc,$crqc */
{
MEP_INSN_CPABSZ_W_C3, "cpabsz_w_C3", "cpabsz.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpldz.h $croc,$crqc */
{
MEP_INSN_CPLDZ_H_C3, "cpldz_h_C3", "cpldz.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpldz.w $croc,$crqc */
{
MEP_INSN_CPLDZ_W_C3, "cpldz_w_C3", "cpldz.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpnorm.h $croc,$crqc */
{
MEP_INSN_CPNORM_H_C3, "cpnorm_h_C3", "cpnorm.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpnorm.w $croc,$crqc */
{
MEP_INSN_CPNORM_W_C3, "cpnorm_w_C3", "cpnorm.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cphaddu.b $croc,$crqc */
{
MEP_INSN_CPHADDU_B_C3, "cphaddu_b_C3", "cphaddu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cphadd.b $croc,$crqc */
{
MEP_INSN_CPHADD_B_C3, "cphadd_b_C3", "cphadd.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cphadd.h $croc,$crqc */
{
MEP_INSN_CPHADD_H_C3, "cphadd_h_C3", "cphadd.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cphadd.w $croc,$crqc */
{
MEP_INSN_CPHADD_W_C3, "cphadd_w_C3", "cphadd.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpccadd.b $crqc */
{
MEP_INSN_CPCCADD_B_C3, "cpccadd_b_C3", "cpccadd.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRSTCOPY, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpbcast.b $croc,$crqc */
{
MEP_INSN_CPBCAST_B_C3, "cpbcast_b_C3", "cpbcast.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpbcast.h $croc,$crqc */
{
MEP_INSN_CPBCAST_H_C3, "cpbcast_h_C3", "cpbcast.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpbcast.w $croc,$crqc */
{
MEP_INSN_CPBCAST_W_C3, "cpbcast_w_C3", "cpbcast.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextuu.b $croc,$crqc */
{
MEP_INSN_CPEXTUU_B_C3, "cpextuu_b_C3", "cpextuu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextu.b $croc,$crqc */
{
MEP_INSN_CPEXTU_B_C3, "cpextu_b_C3", "cpextu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextuu.h $croc,$crqc */
{
MEP_INSN_CPEXTUU_H_C3, "cpextuu_h_C3", "cpextuu.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextu.h $croc,$crqc */
{
MEP_INSN_CPEXTU_H_C3, "cpextu_h_C3", "cpextu.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextlu.b $croc,$crqc */
{
MEP_INSN_CPEXTLU_B_C3, "cpextlu_b_C3", "cpextlu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextl.b $croc,$crqc */
{
MEP_INSN_CPEXTL_B_C3, "cpextl_b_C3", "cpextl.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextlu.h $croc,$crqc */
{
MEP_INSN_CPEXTLU_H_C3, "cpextlu_h_C3", "cpextlu.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpextl.h $croc,$crqc */
{
MEP_INSN_CPEXTL_H_C3, "cpextl_h_C3", "cpextl.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcastub.h $croc,$crqc */
{
MEP_INSN_CPCASTUB_H_C3, "cpcastub_h_C3", "cpcastub.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcastb.h $croc,$crqc */
{
MEP_INSN_CPCASTB_H_C3, "cpcastb_h_C3", "cpcastb.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcastub.w $croc,$crqc */
{
MEP_INSN_CPCASTUB_W_C3, "cpcastub_w_C3", "cpcastub.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcastb.w $croc,$crqc */
{
MEP_INSN_CPCASTB_W_C3, "cpcastb_w_C3", "cpcastb.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcastuh.w $croc,$crqc */
{
MEP_INSN_CPCASTUH_W_C3, "cpcastuh_w_C3", "cpcastuh.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcasth.w $croc,$crqc */
{
MEP_INSN_CPCASTH_W_C3, "cpcasth_w_C3", "cpcasth.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdcastuw $croc,$crqc */
{
MEP_INSN_CDCASTUW_C3, "cdcastuw_C3", "cdcastuw", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdcastw $croc,$crqc */
{
MEP_INSN_CDCASTW_C3, "cdcastw_C3", "cdcastw", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpeqz.b $crqc,$crpc */
{
MEP_INSN_CPCMPEQZ_B_C3, "cpcmpeqz_b_C3", "cpcmpeqz.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpeq.b $crqc,$crpc */
{
MEP_INSN_CPCMPEQ_B_C3, "cpcmpeq_b_C3", "cpcmpeq.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpeq.h $crqc,$crpc */
{
MEP_INSN_CPCMPEQ_H_C3, "cpcmpeq_h_C3", "cpcmpeq.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpeq.w $crqc,$crpc */
{
MEP_INSN_CPCMPEQ_W_C3, "cpcmpeq_w_C3", "cpcmpeq.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpne.b $crqc,$crpc */
{
MEP_INSN_CPCMPNE_B_C3, "cpcmpne_b_C3", "cpcmpne.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpne.h $crqc,$crpc */
{
MEP_INSN_CPCMPNE_H_C3, "cpcmpne_h_C3", "cpcmpne.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpne.w $crqc,$crpc */
{
MEP_INSN_CPCMPNE_W_C3, "cpcmpne_w_C3", "cpcmpne.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpgtu.b $crqc,$crpc */
{
MEP_INSN_CPCMPGTU_B_C3, "cpcmpgtu_b_C3", "cpcmpgtu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpgt.b $crqc,$crpc */
{
MEP_INSN_CPCMPGT_B_C3, "cpcmpgt_b_C3", "cpcmpgt.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpgt.h $crqc,$crpc */
{
MEP_INSN_CPCMPGT_H_C3, "cpcmpgt_h_C3", "cpcmpgt.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpgtu.w $crqc,$crpc */
{
MEP_INSN_CPCMPGTU_W_C3, "cpcmpgtu_w_C3", "cpcmpgtu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpgt.w $crqc,$crpc */
{
MEP_INSN_CPCMPGT_W_C3, "cpcmpgt_w_C3", "cpcmpgt.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpgeu.b $crqc,$crpc */
{
MEP_INSN_CPCMPGEU_B_C3, "cpcmpgeu_b_C3", "cpcmpgeu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpge.b $crqc,$crpc */
{
MEP_INSN_CPCMPGE_B_C3, "cpcmpge_b_C3", "cpcmpge.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpge.h $crqc,$crpc */
{
MEP_INSN_CPCMPGE_H_C3, "cpcmpge_h_C3", "cpcmpge.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpgeu.w $crqc,$crpc */
{
MEP_INSN_CPCMPGEU_W_C3, "cpcmpgeu_w_C3", "cpcmpgeu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpcmpge.w $crqc,$crpc */
{
MEP_INSN_CPCMPGE_W_C3, "cpcmpge_w_C3", "cpcmpge.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpeq.b $crqc,$crpc */
{
MEP_INSN_CPACMPEQ_B_C3, "cpacmpeq_b_C3", "cpacmpeq.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpeq.h $crqc,$crpc */
{
MEP_INSN_CPACMPEQ_H_C3, "cpacmpeq_h_C3", "cpacmpeq.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpeq.w $crqc,$crpc */
{
MEP_INSN_CPACMPEQ_W_C3, "cpacmpeq_w_C3", "cpacmpeq.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpne.b $crqc,$crpc */
{
MEP_INSN_CPACMPNE_B_C3, "cpacmpne_b_C3", "cpacmpne.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpne.h $crqc,$crpc */
{
MEP_INSN_CPACMPNE_H_C3, "cpacmpne_h_C3", "cpacmpne.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpne.w $crqc,$crpc */
{
MEP_INSN_CPACMPNE_W_C3, "cpacmpne_w_C3", "cpacmpne.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpgtu.b $crqc,$crpc */
{
MEP_INSN_CPACMPGTU_B_C3, "cpacmpgtu_b_C3", "cpacmpgtu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpgt.b $crqc,$crpc */
{
MEP_INSN_CPACMPGT_B_C3, "cpacmpgt_b_C3", "cpacmpgt.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpgt.h $crqc,$crpc */
{
MEP_INSN_CPACMPGT_H_C3, "cpacmpgt_h_C3", "cpacmpgt.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpgtu.w $crqc,$crpc */
{
MEP_INSN_CPACMPGTU_W_C3, "cpacmpgtu_w_C3", "cpacmpgtu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpgt.w $crqc,$crpc */
{
MEP_INSN_CPACMPGT_W_C3, "cpacmpgt_w_C3", "cpacmpgt.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpgeu.b $crqc,$crpc */
{
MEP_INSN_CPACMPGEU_B_C3, "cpacmpgeu_b_C3", "cpacmpgeu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpge.b $crqc,$crpc */
{
MEP_INSN_CPACMPGE_B_C3, "cpacmpge_b_C3", "cpacmpge.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpge.h $crqc,$crpc */
{
MEP_INSN_CPACMPGE_H_C3, "cpacmpge_h_C3", "cpacmpge.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpgeu.w $crqc,$crpc */
{
MEP_INSN_CPACMPGEU_W_C3, "cpacmpgeu_w_C3", "cpacmpgeu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpacmpge.w $crqc,$crpc */
{
MEP_INSN_CPACMPGE_W_C3, "cpacmpge_w_C3", "cpacmpge.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpeq.b $crqc,$crpc */
{
MEP_INSN_CPOCMPEQ_B_C3, "cpocmpeq_b_C3", "cpocmpeq.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpeq.h $crqc,$crpc */
{
MEP_INSN_CPOCMPEQ_H_C3, "cpocmpeq_h_C3", "cpocmpeq.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpeq.w $crqc,$crpc */
{
MEP_INSN_CPOCMPEQ_W_C3, "cpocmpeq_w_C3", "cpocmpeq.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpne.b $crqc,$crpc */
{
MEP_INSN_CPOCMPNE_B_C3, "cpocmpne_b_C3", "cpocmpne.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpne.h $crqc,$crpc */
{
MEP_INSN_CPOCMPNE_H_C3, "cpocmpne_h_C3", "cpocmpne.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpne.w $crqc,$crpc */
{
MEP_INSN_CPOCMPNE_W_C3, "cpocmpne_w_C3", "cpocmpne.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpgtu.b $crqc,$crpc */
{
MEP_INSN_CPOCMPGTU_B_C3, "cpocmpgtu_b_C3", "cpocmpgtu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpgt.b $crqc,$crpc */
{
MEP_INSN_CPOCMPGT_B_C3, "cpocmpgt_b_C3", "cpocmpgt.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpgt.h $crqc,$crpc */
{
MEP_INSN_CPOCMPGT_H_C3, "cpocmpgt_h_C3", "cpocmpgt.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpgtu.w $crqc,$crpc */
{
MEP_INSN_CPOCMPGTU_W_C3, "cpocmpgtu_w_C3", "cpocmpgtu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpgt.w $crqc,$crpc */
{
MEP_INSN_CPOCMPGT_W_C3, "cpocmpgt_w_C3", "cpocmpgt.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpgeu.b $crqc,$crpc */
{
MEP_INSN_CPOCMPGEU_B_C3, "cpocmpgeu_b_C3", "cpocmpgeu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpge.b $crqc,$crpc */
{
MEP_INSN_CPOCMPGE_B_C3, "cpocmpge_b_C3", "cpocmpge.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpge.h $crqc,$crpc */
{
MEP_INSN_CPOCMPGE_H_C3, "cpocmpge_h_C3", "cpocmpge.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpgeu.w $crqc,$crpc */
{
MEP_INSN_CPOCMPGEU_W_C3, "cpocmpgeu_w_C3", "cpocmpgeu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpocmpge.w $crqc,$crpc */
{
MEP_INSN_CPOCMPGE_W_C3, "cpocmpge_w_C3", "cpocmpge.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrli3.b $crqc,$crpc,$imm3p9 */
{
MEP_INSN_CPSRLI3_B_C3, "cpsrli3_b_C3", "cpsrli3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrli3.h $crqc,$crpc,$imm4p8 */
{
MEP_INSN_CPSRLI3_H_C3, "cpsrli3_h_C3", "cpsrli3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrli3.w $crqc,$crpc,$imm5p7 */
{
MEP_INSN_CPSRLI3_W_C3, "cpsrli3_w_C3", "cpsrli3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdsrli3 $crqc,$crpc,$imm6p6 */
{
MEP_INSN_CDSRLI3_C3, "cdsrli3_C3", "cdsrli3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrai3.b $crqc,$crpc,$imm3p9 */
{
MEP_INSN_CPSRAI3_B_C3, "cpsrai3_b_C3", "cpsrai3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrai3.h $crqc,$crpc,$imm4p8 */
{
MEP_INSN_CPSRAI3_H_C3, "cpsrai3_h_C3", "cpsrai3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrai3.w $crqc,$crpc,$imm5p7 */
{
MEP_INSN_CPSRAI3_W_C3, "cpsrai3_w_C3", "cpsrai3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdsrai3 $crqc,$crpc,$imm6p6 */
{
MEP_INSN_CDSRAI3_C3, "cdsrai3_C3", "cdsrai3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpslli3.b $crqc,$crpc,$imm3p9 */
{
MEP_INSN_CPSLLI3_B_C3, "cpslli3_b_C3", "cpslli3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpslli3.h $crqc,$crpc,$imm4p8 */
{
MEP_INSN_CPSLLI3_H_C3, "cpslli3_h_C3", "cpslli3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpslli3.w $crqc,$crpc,$imm5p7 */
{
MEP_INSN_CPSLLI3_W_C3, "cpslli3_w_C3", "cpslli3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdslli3 $crqc,$crpc,$imm6p6 */
{
MEP_INSN_CDSLLI3_C3, "cdslli3_C3", "cdslli3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpslai3.h $crqc,$crpc,$imm4p8 */
{
MEP_INSN_CPSLAI3_H_C3, "cpslai3_h_C3", "cpslai3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpslai3.w $crqc,$crpc,$imm5p7 */
{
MEP_INSN_CPSLAI3_W_C3, "cpslai3_w_C3", "cpslai3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpclipiu3.w $crqc,$crpc,$imm5p7 */
{
MEP_INSN_CPCLIPIU3_W_C3, "cpclipiu3_w_C3", "cpclipiu3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpclipi3.w $crqc,$crpc,$imm5p7 */
{
MEP_INSN_CPCLIPI3_W_C3, "cpclipi3_w_C3", "cpclipi3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdclipiu3 $crqc,$crpc,$imm6p6 */
{
MEP_INSN_CDCLIPIU3_C3, "cdclipiu3_C3", "cdclipiu3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdclipi3 $crqc,$crpc,$imm6p6 */
{
MEP_INSN_CDCLIPI3_C3, "cdclipi3_C3", "cdclipi3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovi.b $crqc,$simm8p4 */
{
MEP_INSN_CPMOVI_B_C3, "cpmovi_b_C3", "cpmovi.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmoviu.h $crqc,$imm8p4 */
{
MEP_INSN_CPMOVIU_H_C3, "cpmoviu_h_C3", "cpmoviu.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovi.h $crqc,$simm8p4 */
{
MEP_INSN_CPMOVI_H_C3, "cpmovi_h_C3", "cpmovi.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmoviu.w $crqc,$imm8p4 */
{
MEP_INSN_CPMOVIU_W_C3, "cpmoviu_w_C3", "cpmoviu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovi.w $crqc,$simm8p4 */
{
MEP_INSN_CPMOVI_W_C3, "cpmovi_w_C3", "cpmovi.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdmoviu $crqc,$imm8p4 */
{
MEP_INSN_CDMOVIU_C3, "cdmoviu_C3", "cdmoviu", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cdmovi $crqc,$simm8p4 */
{
MEP_INSN_CDMOVI_C3, "cdmovi_C3", "cdmovi", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpadda1u.b $crqc,$crpc */
{
MEP_INSN_CPADDA1U_B_C3, "cpadda1u_b_C3", "cpadda1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpadda1.b $crqc,$crpc */
{
MEP_INSN_CPADDA1_B_C3, "cpadda1_b_C3", "cpadda1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddua1.h $crqc,$crpc */
{
MEP_INSN_CPADDUA1_H_C3, "cpaddua1_h_C3", "cpaddua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddla1.h $crqc,$crpc */
{
MEP_INSN_CPADDLA1_H_C3, "cpaddla1_h_C3", "cpaddla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddaca1u.b $crqc,$crpc */
{
MEP_INSN_CPADDACA1U_B_C3, "cpaddaca1u_b_C3", "cpaddaca1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddaca1.b $crqc,$crpc */
{
MEP_INSN_CPADDACA1_B_C3, "cpaddaca1_b_C3", "cpaddaca1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddacua1.h $crqc,$crpc */
{
MEP_INSN_CPADDACUA1_H_C3, "cpaddacua1_h_C3", "cpaddacua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpaddacla1.h $crqc,$crpc */
{
MEP_INSN_CPADDACLA1_H_C3, "cpaddacla1_h_C3", "cpaddacla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsuba1u.b $crqc,$crpc */
{
MEP_INSN_CPSUBA1U_B_C3, "cpsuba1u_b_C3", "cpsuba1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsuba1.b $crqc,$crpc */
{
MEP_INSN_CPSUBA1_B_C3, "cpsuba1_b_C3", "cpsuba1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsubua1.h $crqc,$crpc */
{
MEP_INSN_CPSUBUA1_H_C3, "cpsubua1_h_C3", "cpsubua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsubla1.h $crqc,$crpc */
{
MEP_INSN_CPSUBLA1_H_C3, "cpsubla1_h_C3", "cpsubla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsubaca1u.b $crqc,$crpc */
{
MEP_INSN_CPSUBACA1U_B_C3, "cpsubaca1u_b_C3", "cpsubaca1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsubaca1.b $crqc,$crpc */
{
MEP_INSN_CPSUBACA1_B_C3, "cpsubaca1_b_C3", "cpsubaca1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsubacua1.h $crqc,$crpc */
{
MEP_INSN_CPSUBACUA1_H_C3, "cpsubacua1_h_C3", "cpsubacua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsubacla1.h $crqc,$crpc */
{
MEP_INSN_CPSUBACLA1_H_C3, "cpsubacla1_h_C3", "cpsubacla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsa1u.b $crqc,$crpc */
{
MEP_INSN_CPABSA1U_B_C3, "cpabsa1u_b_C3", "cpabsa1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsa1.b $crqc,$crpc */
{
MEP_INSN_CPABSA1_B_C3, "cpabsa1_b_C3", "cpabsa1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsua1.h $crqc,$crpc */
{
MEP_INSN_CPABSUA1_H_C3, "cpabsua1_h_C3", "cpabsua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpabsla1.h $crqc,$crpc */
{
MEP_INSN_CPABSLA1_H_C3, "cpabsla1_h_C3", "cpabsla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsada1u.b $crqc,$crpc */
{
MEP_INSN_CPSADA1U_B_C3, "cpsada1u_b_C3", "cpsada1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsada1.b $crqc,$crpc */
{
MEP_INSN_CPSADA1_B_C3, "cpsada1_b_C3", "cpsada1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsadua1.h $crqc,$crpc */
{
MEP_INSN_CPSADUA1_H_C3, "cpsadua1_h_C3", "cpsadua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsadla1.h $crqc,$crpc */
{
MEP_INSN_CPSADLA1_H_C3, "cpsadla1_h_C3", "cpsadla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpseta1.h $crqc,$crpc */
{
MEP_INSN_CPSETA1_H_C3, "cpseta1_h_C3", "cpseta1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsetua1.w $crqc,$crpc */
{
MEP_INSN_CPSETUA1_W_C3, "cpsetua1_w_C3", "cpsetua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsetla1.w $crqc,$crpc */
{
MEP_INSN_CPSETLA1_W_C3, "cpsetla1_w_C3", "cpsetla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmova1.b $croc */
{
MEP_INSN_CPMOVA1_B_C3, "cpmova1_b_C3", "cpmova1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovua1.h $croc */
{
MEP_INSN_CPMOVUA1_H_C3, "cpmovua1_h_C3", "cpmovua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovla1.h $croc */
{
MEP_INSN_CPMOVLA1_H_C3, "cpmovla1_h_C3", "cpmovla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovuua1.w $croc */
{
MEP_INSN_CPMOVUUA1_W_C3, "cpmovuua1_w_C3", "cpmovuua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovula1.w $croc */
{
MEP_INSN_CPMOVULA1_W_C3, "cpmovula1_w_C3", "cpmovula1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovlua1.w $croc */
{
MEP_INSN_CPMOVLUA1_W_C3, "cpmovlua1_w_C3", "cpmovlua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovlla1.w $croc */
{
MEP_INSN_CPMOVLLA1_W_C3, "cpmovlla1_w_C3", "cpmovlla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppacka1u.b $croc */
{
MEP_INSN_CPPACKA1U_B_C3, "cppacka1u_b_C3", "cppacka1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppacka1.b $croc */
{
MEP_INSN_CPPACKA1_B_C3, "cppacka1_b_C3", "cppacka1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppackua1.h $croc */
{
MEP_INSN_CPPACKUA1_H_C3, "cppackua1_h_C3", "cppackua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppackla1.h $croc */
{
MEP_INSN_CPPACKLA1_H_C3, "cppackla1_h_C3", "cppackla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppackua1.w $croc */
{
MEP_INSN_CPPACKUA1_W_C3, "cppackua1_w_C3", "cppackua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cppackla1.w $croc */
{
MEP_INSN_CPPACKLA1_W_C3, "cppackla1_w_C3", "cppackla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovhua1.w $croc */
{
MEP_INSN_CPMOVHUA1_W_C3, "cpmovhua1_w_C3", "cpmovhua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmovhla1.w $croc */
{
MEP_INSN_CPMOVHLA1_W_C3, "cpmovhla1_w_C3", "cpmovhla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrla1 $crqc */
{
MEP_INSN_CPSRLA1_C3, "cpsrla1_C3", "cpsrla1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsraa1 $crqc */
{
MEP_INSN_CPSRAA1_C3, "cpsraa1_C3", "cpsraa1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpslla1 $crqc */
{
MEP_INSN_CPSLLA1_C3, "cpslla1_C3", "cpslla1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsrlia1 $imm5p7 */
{
MEP_INSN_CPSRLIA1_P1, "cpsrlia1_P1", "cpsrlia1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsraia1 $imm5p7 */
{
MEP_INSN_CPSRAIA1_P1, "cpsraia1_P1", "cpsraia1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsllia1 $imm5p7 */
{
MEP_INSN_CPSLLIA1_P1, "cpsllia1_P1", "cpsllia1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssqa1u.b $crqc,$crpc */
{
MEP_INSN_CPSSQA1U_B_C3, "cpssqa1u_b_C3", "cpssqa1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssqa1.b $crqc,$crpc */
{
MEP_INSN_CPSSQA1_B_C3, "cpssqa1_b_C3", "cpssqa1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssda1u.b $crqc,$crpc */
{
MEP_INSN_CPSSDA1U_B_C3, "cpssda1u_b_C3", "cpssda1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpssda1.b $crqc,$crpc */
{
MEP_INSN_CPSSDA1_B_C3, "cpssda1_b_C3", "cpssda1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmula1u.b $crqc,$crpc */
{
MEP_INSN_CPMULA1U_B_C3, "cpmula1u_b_C3", "cpmula1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmula1.b $crqc,$crpc */
{
MEP_INSN_CPMULA1_B_C3, "cpmula1_b_C3", "cpmula1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulua1.h $crqc,$crpc */
{
MEP_INSN_CPMULUA1_H_C3, "cpmulua1_h_C3", "cpmulua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulla1.h $crqc,$crpc */
{
MEP_INSN_CPMULLA1_H_C3, "cpmulla1_h_C3", "cpmulla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulua1u.w $crqc,$crpc */
{
MEP_INSN_CPMULUA1U_W_C3, "cpmulua1u_w_C3", "cpmulua1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulla1u.w $crqc,$crpc */
{
MEP_INSN_CPMULLA1U_W_C3, "cpmulla1u_w_C3", "cpmulla1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulua1.w $crqc,$crpc */
{
MEP_INSN_CPMULUA1_W_C3, "cpmulua1_w_C3", "cpmulua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulla1.w $crqc,$crpc */
{
MEP_INSN_CPMULLA1_W_C3, "cpmulla1_w_C3", "cpmulla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmada1u.b $crqc,$crpc */
{
MEP_INSN_CPMADA1U_B_C3, "cpmada1u_b_C3", "cpmada1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmada1.b $crqc,$crpc */
{
MEP_INSN_CPMADA1_B_C3, "cpmada1_b_C3", "cpmada1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmadua1.h $crqc,$crpc */
{
MEP_INSN_CPMADUA1_H_C3, "cpmadua1_h_C3", "cpmadua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmadla1.h $crqc,$crpc */
{
MEP_INSN_CPMADLA1_H_C3, "cpmadla1_h_C3", "cpmadla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmadua1u.w $crqc,$crpc */
{
MEP_INSN_CPMADUA1U_W_C3, "cpmadua1u_w_C3", "cpmadua1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmadla1u.w $crqc,$crpc */
{
MEP_INSN_CPMADLA1U_W_C3, "cpmadla1u_w_C3", "cpmadla1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmadua1.w $crqc,$crpc */
{
MEP_INSN_CPMADUA1_W_C3, "cpmadua1_w_C3", "cpmadua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmadla1.w $crqc,$crpc */
{
MEP_INSN_CPMADLA1_W_C3, "cpmadla1_w_C3", "cpmadla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmsbua1.h $crqc,$crpc */
{
MEP_INSN_CPMSBUA1_H_C3, "cpmsbua1_h_C3", "cpmsbua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmsbla1.h $crqc,$crpc */
{
MEP_INSN_CPMSBLA1_H_C3, "cpmsbla1_h_C3", "cpmsbla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmsbua1u.w $crqc,$crpc */
{
MEP_INSN_CPMSBUA1U_W_C3, "cpmsbua1u_w_C3", "cpmsbua1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmsbla1u.w $crqc,$crpc */
{
MEP_INSN_CPMSBLA1U_W_C3, "cpmsbla1u_w_C3", "cpmsbla1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmsbua1.w $crqc,$crpc */
{
MEP_INSN_CPMSBUA1_W_C3, "cpmsbua1_w_C3", "cpmsbua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmsbla1.w $crqc,$crpc */
{
MEP_INSN_CPMSBLA1_W_C3, "cpmsbla1_w_C3", "cpmsbla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadua1.h $crqc,$crpc */
{
MEP_INSN_CPSMADUA1_H_C3, "cpsmadua1_h_C3", "cpsmadua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadla1.h $crqc,$crpc */
{
MEP_INSN_CPSMADLA1_H_C3, "cpsmadla1_h_C3", "cpsmadla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadua1.w $crqc,$crpc */
{
MEP_INSN_CPSMADUA1_W_C3, "cpsmadua1_w_C3", "cpsmadua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadla1.w $crqc,$crpc */
{
MEP_INSN_CPSMADLA1_W_C3, "cpsmadla1_w_C3", "cpsmadla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbua1.h $crqc,$crpc */
{
MEP_INSN_CPSMSBUA1_H_C3, "cpsmsbua1_h_C3", "cpsmsbua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbla1.h $crqc,$crpc */
{
MEP_INSN_CPSMSBLA1_H_C3, "cpsmsbla1_h_C3", "cpsmsbla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbua1.w $crqc,$crpc */
{
MEP_INSN_CPSMSBUA1_W_C3, "cpsmsbua1_w_C3", "cpsmsbua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbla1.w $crqc,$crpc */
{
MEP_INSN_CPSMSBLA1_W_C3, "cpsmsbla1_w_C3", "cpsmsbla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulslua1.h $crqc,$crpc */
{
MEP_INSN_CPMULSLUA1_H_C3, "cpmulslua1_h_C3", "cpmulslua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulslla1.h $crqc,$crpc */
{
MEP_INSN_CPMULSLLA1_H_C3, "cpmulslla1_h_C3", "cpmulslla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulslua1.w $crqc,$crpc */
{
MEP_INSN_CPMULSLUA1_W_C3, "cpmulslua1_w_C3", "cpmulslua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpmulslla1.w $crqc,$crpc */
{
MEP_INSN_CPMULSLLA1_W_C3, "cpmulslla1_w_C3", "cpmulslla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadslua1.h $crqc,$crpc */
{
MEP_INSN_CPSMADSLUA1_H_C3, "cpsmadslua1_h_C3", "cpsmadslua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadslla1.h $crqc,$crpc */
{
MEP_INSN_CPSMADSLLA1_H_C3, "cpsmadslla1_h_C3", "cpsmadslla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadslua1.w $crqc,$crpc */
{
MEP_INSN_CPSMADSLUA1_W_C3, "cpsmadslua1_w_C3", "cpsmadslua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmadslla1.w $crqc,$crpc */
{
MEP_INSN_CPSMADSLLA1_W_C3, "cpsmadslla1_w_C3", "cpsmadslla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbslua1.h $crqc,$crpc */
{
MEP_INSN_CPSMSBSLUA1_H_C3, "cpsmsbslua1_h_C3", "cpsmsbslua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbslla1.h $crqc,$crpc */
{
MEP_INSN_CPSMSBSLLA1_H_C3, "cpsmsbslla1_h_C3", "cpsmsbslla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbslua1.w $crqc,$crpc */
{
MEP_INSN_CPSMSBSLUA1_W_C3, "cpsmsbslua1_w_C3", "cpsmsbslua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* cpsmsbslla1.w $crqc,$crpc */
{
MEP_INSN_CPSMSBSLLA1_W_C3, "cpsmsbslla1_w_C3", "cpsmsbslla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_C3), 0 } } } }
},
/* c0nop */
{
MEP_INSN_C0NOP_P0_P0S, "c0nop_P0_P0S", "c0nop", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x28" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x28" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P0S), 0 } } } }
},
/* cpadd3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPADD3_B_P0S_P1, "cpadd3_b_P0S_P1", "cpadd3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpadd3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPADD3_H_P0S_P1, "cpadd3_h_P0S_P1", "cpadd3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpadd3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPADD3_W_P0S_P1, "cpadd3_w_P0S_P1", "cpadd3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpunpacku.b $crop,$crqp,$crpp */
{
MEP_INSN_CPUNPACKU_B_P0S_P1, "cpunpacku_b_P0S_P1", "cpunpacku.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpunpacku.h $crop,$crqp,$crpp */
{
MEP_INSN_CPUNPACKU_H_P0S_P1, "cpunpacku_h_P0S_P1", "cpunpacku.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpunpacku.w $crop,$crqp,$crpp */
{
MEP_INSN_CPUNPACKU_W_P0S_P1, "cpunpacku_w_P0S_P1", "cpunpacku.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpunpackl.b $crop,$crqp,$crpp */
{
MEP_INSN_CPUNPACKL_B_P0S_P1, "cpunpackl_b_P0S_P1", "cpunpackl.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpunpackl.h $crop,$crqp,$crpp */
{
MEP_INSN_CPUNPACKL_H_P0S_P1, "cpunpackl_h_P0S_P1", "cpunpackl.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpunpackl.w $crop,$crqp,$crpp */
{
MEP_INSN_CPUNPACKL_W_P0S_P1, "cpunpackl_w_P0S_P1", "cpunpackl.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsel $crop,$crqp,$crpp */
{
MEP_INSN_CPSEL_P0S_P1, "cpsel_P0S_P1", "cpsel", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpfsftbs0 $crop,$crqp,$crpp */
{
MEP_INSN_CPFSFTBS0_P0S_P1, "cpfsftbs0_P0S_P1", "cpfsftbs0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpfsftbs1 $crop,$crqp,$crpp */
{
MEP_INSN_CPFSFTBS1_P0S_P1, "cpfsftbs1_P0S_P1", "cpfsftbs1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmov $crop,$crqp */
{
MEP_INSN_CPMOV_P0S_P1, "cpmov_P0S_P1", "cpmov", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpabsz.b $crop,$crqp */
{
MEP_INSN_CPABSZ_B_P0S_P1, "cpabsz_b_P0S_P1", "cpabsz.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpabsz.h $crop,$crqp */
{
MEP_INSN_CPABSZ_H_P0S_P1, "cpabsz_h_P0S_P1", "cpabsz.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpabsz.w $crop,$crqp */
{
MEP_INSN_CPABSZ_W_P0S_P1, "cpabsz_w_P0S_P1", "cpabsz.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpldz.h $crop,$crqp */
{
MEP_INSN_CPLDZ_H_P0S_P1, "cpldz_h_P0S_P1", "cpldz.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpldz.w $crop,$crqp */
{
MEP_INSN_CPLDZ_W_P0S_P1, "cpldz_w_P0S_P1", "cpldz.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpnorm.h $crop,$crqp */
{
MEP_INSN_CPNORM_H_P0S_P1, "cpnorm_h_P0S_P1", "cpnorm.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpnorm.w $crop,$crqp */
{
MEP_INSN_CPNORM_W_P0S_P1, "cpnorm_w_P0S_P1", "cpnorm.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cphaddu.b $crop,$crqp */
{
MEP_INSN_CPHADDU_B_P0S_P1, "cphaddu_b_P0S_P1", "cphaddu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cphadd.b $crop,$crqp */
{
MEP_INSN_CPHADD_B_P0S_P1, "cphadd_b_P0S_P1", "cphadd.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cphadd.h $crop,$crqp */
{
MEP_INSN_CPHADD_H_P0S_P1, "cphadd_h_P0S_P1", "cphadd.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cphadd.w $crop,$crqp */
{
MEP_INSN_CPHADD_W_P0S_P1, "cphadd_w_P0S_P1", "cphadd.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpccadd.b $crqp */
{
MEP_INSN_CPCCADD_B_P0S_P1, "cpccadd_b_P0S_P1", "cpccadd.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRSTCOPY, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpbcast.b $crop,$crqp */
{
MEP_INSN_CPBCAST_B_P0S_P1, "cpbcast_b_P0S_P1", "cpbcast.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpbcast.h $crop,$crqp */
{
MEP_INSN_CPBCAST_H_P0S_P1, "cpbcast_h_P0S_P1", "cpbcast.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpbcast.w $crop,$crqp */
{
MEP_INSN_CPBCAST_W_P0S_P1, "cpbcast_w_P0S_P1", "cpbcast.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextuu.b $crop,$crqp */
{
MEP_INSN_CPEXTUU_B_P0S_P1, "cpextuu_b_P0S_P1", "cpextuu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextu.b $crop,$crqp */
{
MEP_INSN_CPEXTU_B_P0S_P1, "cpextu_b_P0S_P1", "cpextu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextuu.h $crop,$crqp */
{
MEP_INSN_CPEXTUU_H_P0S_P1, "cpextuu_h_P0S_P1", "cpextuu.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextu.h $crop,$crqp */
{
MEP_INSN_CPEXTU_H_P0S_P1, "cpextu_h_P0S_P1", "cpextu.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextlu.b $crop,$crqp */
{
MEP_INSN_CPEXTLU_B_P0S_P1, "cpextlu_b_P0S_P1", "cpextlu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextl.b $crop,$crqp */
{
MEP_INSN_CPEXTL_B_P0S_P1, "cpextl_b_P0S_P1", "cpextl.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextlu.h $crop,$crqp */
{
MEP_INSN_CPEXTLU_H_P0S_P1, "cpextlu_h_P0S_P1", "cpextlu.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4UHI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextl.h $crop,$crqp */
{
MEP_INSN_CPEXTL_H_P0S_P1, "cpextl_h_P0S_P1", "cpextl.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcastub.h $crop,$crqp */
{
MEP_INSN_CPCASTUB_H_P0S_P1, "cpcastub_h_P0S_P1", "cpcastub.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcastb.h $crop,$crqp */
{
MEP_INSN_CPCASTB_H_P0S_P1, "cpcastb_h_P0S_P1", "cpcastb.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcastub.w $crop,$crqp */
{
MEP_INSN_CPCASTUB_W_P0S_P1, "cpcastub_w_P0S_P1", "cpcastub.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcastb.w $crop,$crqp */
{
MEP_INSN_CPCASTB_W_P0S_P1, "cpcastb_w_P0S_P1", "cpcastb.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcastuh.w $crop,$crqp */
{
MEP_INSN_CPCASTUH_W_P0S_P1, "cpcastuh_w_P0S_P1", "cpcastuh.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcasth.w $crop,$crqp */
{
MEP_INSN_CPCASTH_W_P0S_P1, "cpcasth_w_P0S_P1", "cpcasth.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cdcastuw $crop,$crqp */
{
MEP_INSN_CDCASTUW_P0S_P1, "cdcastuw_P0S_P1", "cdcastuw", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cdcastw $crop,$crqp */
{
MEP_INSN_CDCASTW_P0S_P1, "cdcastw_P0S_P1", "cdcastw", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovfrcsar0 $crop */
{
MEP_INSN_CPMOVFRCSAR0_P0S_P1, "cpmovfrcsar0_P0S_P1", "cpmovfrcsar0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovfrcsar1 $crop */
{
MEP_INSN_CPMOVFRCSAR1_P0S_P1, "cpmovfrcsar1_P0S_P1", "cpmovfrcsar1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovfrcc $crop */
{
MEP_INSN_CPMOVFRCC_P0S_P1, "cpmovfrcc_P0S_P1", "cpmovfrcc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovtocsar0 $crqp */
{
MEP_INSN_CPMOVTOCSAR0_P0S_P1, "cpmovtocsar0_P0S_P1", "cpmovtocsar0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovtocsar1 $crqp */
{
MEP_INSN_CPMOVTOCSAR1_P0S_P1, "cpmovtocsar1_P0S_P1", "cpmovtocsar1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovtocc $crqp */
{
MEP_INSN_CPMOVTOCC_P0S_P1, "cpmovtocc_P0S_P1", "cpmovtocc", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpeqz.b $crqp,$crpp */
{
MEP_INSN_CPCMPEQZ_B_P0S_P1, "cpcmpeqz_b_P0S_P1", "cpcmpeqz.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpeq.b $crqp,$crpp */
{
MEP_INSN_CPCMPEQ_B_P0S_P1, "cpcmpeq_b_P0S_P1", "cpcmpeq.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpeq.h $crqp,$crpp */
{
MEP_INSN_CPCMPEQ_H_P0S_P1, "cpcmpeq_h_P0S_P1", "cpcmpeq.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpeq.w $crqp,$crpp */
{
MEP_INSN_CPCMPEQ_W_P0S_P1, "cpcmpeq_w_P0S_P1", "cpcmpeq.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpne.b $crqp,$crpp */
{
MEP_INSN_CPCMPNE_B_P0S_P1, "cpcmpne_b_P0S_P1", "cpcmpne.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpne.h $crqp,$crpp */
{
MEP_INSN_CPCMPNE_H_P0S_P1, "cpcmpne_h_P0S_P1", "cpcmpne.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpne.w $crqp,$crpp */
{
MEP_INSN_CPCMPNE_W_P0S_P1, "cpcmpne_w_P0S_P1", "cpcmpne.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpgtu.b $crqp,$crpp */
{
MEP_INSN_CPCMPGTU_B_P0S_P1, "cpcmpgtu_b_P0S_P1", "cpcmpgtu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpgt.b $crqp,$crpp */
{
MEP_INSN_CPCMPGT_B_P0S_P1, "cpcmpgt_b_P0S_P1", "cpcmpgt.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpgt.h $crqp,$crpp */
{
MEP_INSN_CPCMPGT_H_P0S_P1, "cpcmpgt_h_P0S_P1", "cpcmpgt.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpgtu.w $crqp,$crpp */
{
MEP_INSN_CPCMPGTU_W_P0S_P1, "cpcmpgtu_w_P0S_P1", "cpcmpgtu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpgt.w $crqp,$crpp */
{
MEP_INSN_CPCMPGT_W_P0S_P1, "cpcmpgt_w_P0S_P1", "cpcmpgt.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpgeu.b $crqp,$crpp */
{
MEP_INSN_CPCMPGEU_B_P0S_P1, "cpcmpgeu_b_P0S_P1", "cpcmpgeu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpge.b $crqp,$crpp */
{
MEP_INSN_CPCMPGE_B_P0S_P1, "cpcmpge_b_P0S_P1", "cpcmpge.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpge.h $crqp,$crpp */
{
MEP_INSN_CPCMPGE_H_P0S_P1, "cpcmpge_h_P0S_P1", "cpcmpge.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpgeu.w $crqp,$crpp */
{
MEP_INSN_CPCMPGEU_W_P0S_P1, "cpcmpgeu_w_P0S_P1", "cpcmpgeu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpcmpge.w $crqp,$crpp */
{
MEP_INSN_CPCMPGE_W_P0S_P1, "cpcmpge_w_P0S_P1", "cpcmpge.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpadda0u.b $crqp,$crpp */
{
MEP_INSN_CPADDA0U_B_P0S, "cpadda0u_b_P0S", "cpadda0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpadda0.b $crqp,$crpp */
{
MEP_INSN_CPADDA0_B_P0S, "cpadda0_b_P0S", "cpadda0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpaddua0.h $crqp,$crpp */
{
MEP_INSN_CPADDUA0_H_P0S, "cpaddua0_h_P0S", "cpaddua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpaddla0.h $crqp,$crpp */
{
MEP_INSN_CPADDLA0_H_P0S, "cpaddla0_h_P0S", "cpaddla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpaddaca0u.b $crqp,$crpp */
{
MEP_INSN_CPADDACA0U_B_P0S, "cpaddaca0u_b_P0S", "cpaddaca0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpaddaca0.b $crqp,$crpp */
{
MEP_INSN_CPADDACA0_B_P0S, "cpaddaca0_b_P0S", "cpaddaca0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpaddacua0.h $crqp,$crpp */
{
MEP_INSN_CPADDACUA0_H_P0S, "cpaddacua0_h_P0S", "cpaddacua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpaddacla0.h $crqp,$crpp */
{
MEP_INSN_CPADDACLA0_H_P0S, "cpaddacla0_h_P0S", "cpaddacla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsuba0u.b $crqp,$crpp */
{
MEP_INSN_CPSUBA0U_B_P0S, "cpsuba0u_b_P0S", "cpsuba0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsuba0.b $crqp,$crpp */
{
MEP_INSN_CPSUBA0_B_P0S, "cpsuba0_b_P0S", "cpsuba0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsubua0.h $crqp,$crpp */
{
MEP_INSN_CPSUBUA0_H_P0S, "cpsubua0_h_P0S", "cpsubua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsubla0.h $crqp,$crpp */
{
MEP_INSN_CPSUBLA0_H_P0S, "cpsubla0_h_P0S", "cpsubla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsubaca0u.b $crqp,$crpp */
{
MEP_INSN_CPSUBACA0U_B_P0S, "cpsubaca0u_b_P0S", "cpsubaca0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsubaca0.b $crqp,$crpp */
{
MEP_INSN_CPSUBACA0_B_P0S, "cpsubaca0_b_P0S", "cpsubaca0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsubacua0.h $crqp,$crpp */
{
MEP_INSN_CPSUBACUA0_H_P0S, "cpsubacua0_h_P0S", "cpsubacua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsubacla0.h $crqp,$crpp */
{
MEP_INSN_CPSUBACLA0_H_P0S, "cpsubacla0_h_P0S", "cpsubacla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpabsa0u.b $crqp,$crpp */
{
MEP_INSN_CPABSA0U_B_P0S, "cpabsa0u_b_P0S", "cpabsa0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpabsa0.b $crqp,$crpp */
{
MEP_INSN_CPABSA0_B_P0S, "cpabsa0_b_P0S", "cpabsa0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpabsua0.h $crqp,$crpp */
{
MEP_INSN_CPABSUA0_H_P0S, "cpabsua0_h_P0S", "cpabsua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpabsla0.h $crqp,$crpp */
{
MEP_INSN_CPABSLA0_H_P0S, "cpabsla0_h_P0S", "cpabsla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsada0u.b $crqp,$crpp */
{
MEP_INSN_CPSADA0U_B_P0S, "cpsada0u_b_P0S", "cpsada0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsada0.b $crqp,$crpp */
{
MEP_INSN_CPSADA0_B_P0S, "cpsada0_b_P0S", "cpsada0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsadua0.h $crqp,$crpp */
{
MEP_INSN_CPSADUA0_H_P0S, "cpsadua0_h_P0S", "cpsadua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsadla0.h $crqp,$crpp */
{
MEP_INSN_CPSADLA0_H_P0S, "cpsadla0_h_P0S", "cpsadla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpseta0.h $crqp,$crpp */
{
MEP_INSN_CPSETA0_H_P0S, "cpseta0_h_P0S", "cpseta0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsetua0.w $crqp,$crpp */
{
MEP_INSN_CPSETUA0_W_P0S, "cpsetua0_w_P0S", "cpsetua0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsetla0.w $crqp,$crpp */
{
MEP_INSN_CPSETLA0_W_P0S, "cpsetla0_w_P0S", "cpsetla0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmova0.b $crop */
{
MEP_INSN_CPMOVA0_B_P0S, "cpmova0_b_P0S", "cpmova0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovua0.h $crop */
{
MEP_INSN_CPMOVUA0_H_P0S, "cpmovua0_h_P0S", "cpmovua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovla0.h $crop */
{
MEP_INSN_CPMOVLA0_H_P0S, "cpmovla0_h_P0S", "cpmovla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovuua0.w $crop */
{
MEP_INSN_CPMOVUUA0_W_P0S, "cpmovuua0_w_P0S", "cpmovuua0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovula0.w $crop */
{
MEP_INSN_CPMOVULA0_W_P0S, "cpmovula0_w_P0S", "cpmovula0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovlua0.w $crop */
{
MEP_INSN_CPMOVLUA0_W_P0S, "cpmovlua0_w_P0S", "cpmovlua0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovlla0.w $crop */
{
MEP_INSN_CPMOVLLA0_W_P0S, "cpmovlla0_w_P0S", "cpmovlla0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cppacka0u.b $crop */
{
MEP_INSN_CPPACKA0U_B_P0S, "cppacka0u_b_P0S", "cppacka0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cppacka0.b $crop */
{
MEP_INSN_CPPACKA0_B_P0S, "cppacka0_b_P0S", "cppacka0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cppackua0.h $crop */
{
MEP_INSN_CPPACKUA0_H_P0S, "cppackua0_h_P0S", "cppackua0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cppackla0.h $crop */
{
MEP_INSN_CPPACKLA0_H_P0S, "cppackla0_h_P0S", "cppackla0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cppackua0.w $crop */
{
MEP_INSN_CPPACKUA0_W_P0S, "cppackua0_w_P0S", "cppackua0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cppackla0.w $crop */
{
MEP_INSN_CPPACKLA0_W_P0S, "cppackla0_w_P0S", "cppackla0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovhua0.w $crop */
{
MEP_INSN_CPMOVHUA0_W_P0S, "cpmovhua0_w_P0S", "cpmovhua0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpmovhla0.w $crop */
{
MEP_INSN_CPMOVHLA0_W_P0S, "cpmovhla0_w_P0S", "cpmovhla0.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpacsuma0 */
{
MEP_INSN_CPACSUMA0_P0S, "cpacsuma0_P0S", "cpacsuma0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpaccpa0 */
{
MEP_INSN_CPACCPA0_P0S, "cpaccpa0_P0S", "cpaccpa0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsrla0 $crqp */
{
MEP_INSN_CPSRLA0_P0S, "cpsrla0_P0S", "cpsrla0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsraa0 $crqp */
{
MEP_INSN_CPSRAA0_P0S, "cpsraa0_P0S", "cpsraa0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpslla0 $crqp */
{
MEP_INSN_CPSLLA0_P0S, "cpslla0_P0S", "cpslla0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsrlia0 $imm5p23 */
{
MEP_INSN_CPSRLIA0_P0S, "cpsrlia0_P0S", "cpsrlia0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsraia0 $imm5p23 */
{
MEP_INSN_CPSRAIA0_P0S, "cpsraia0_P0S", "cpsraia0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpsllia0 $imm5p23 */
{
MEP_INSN_CPSLLIA0_P0S, "cpsllia0_P0S", "cpsllia0", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftba0s0u.b $crqp,$crpp */
{
MEP_INSN_CPFSFTBA0S0U_B_P0S, "cpfsftba0s0u_b_P0S", "cpfsftba0s0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftba0s0.b $crqp,$crpp */
{
MEP_INSN_CPFSFTBA0S0_B_P0S, "cpfsftba0s0_b_P0S", "cpfsftba0s0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftbua0s0.h $crqp,$crpp */
{
MEP_INSN_CPFSFTBUA0S0_H_P0S, "cpfsftbua0s0_h_P0S", "cpfsftbua0s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftbla0s0.h $crqp,$crpp */
{
MEP_INSN_CPFSFTBLA0S0_H_P0S, "cpfsftbla0s0_h_P0S", "cpfsftbla0s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfaca0s0u.b $crqp,$crpp */
{
MEP_INSN_CPFACA0S0U_B_P0S, "cpfaca0s0u_b_P0S", "cpfaca0s0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfaca0s0.b $crqp,$crpp */
{
MEP_INSN_CPFACA0S0_B_P0S, "cpfaca0s0_b_P0S", "cpfaca0s0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfacua0s0.h $crqp,$crpp */
{
MEP_INSN_CPFACUA0S0_H_P0S, "cpfacua0s0_h_P0S", "cpfacua0s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfacla0s0.h $crqp,$crpp */
{
MEP_INSN_CPFACLA0S0_H_P0S, "cpfacla0s0_h_P0S", "cpfacla0s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftba0s1u.b $crqp,$crpp */
{
MEP_INSN_CPFSFTBA0S1U_B_P0S, "cpfsftba0s1u_b_P0S", "cpfsftba0s1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftba0s1.b $crqp,$crpp */
{
MEP_INSN_CPFSFTBA0S1_B_P0S, "cpfsftba0s1_b_P0S", "cpfsftba0s1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftbua0s1.h $crqp,$crpp */
{
MEP_INSN_CPFSFTBUA0S1_H_P0S, "cpfsftbua0s1_h_P0S", "cpfsftbua0s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftbla0s1.h $crqp,$crpp */
{
MEP_INSN_CPFSFTBLA0S1_H_P0S, "cpfsftbla0s1_h_P0S", "cpfsftbla0s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfaca0s1u.b $crqp,$crpp */
{
MEP_INSN_CPFACA0S1U_B_P0S, "cpfaca0s1u_b_P0S", "cpfaca0s1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfaca0s1.b $crqp,$crpp */
{
MEP_INSN_CPFACA0S1_B_P0S, "cpfaca0s1_b_P0S", "cpfaca0s1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfacua0s1.h $crqp,$crpp */
{
MEP_INSN_CPFACUA0S1_H_P0S, "cpfacua0s1_h_P0S", "cpfacua0s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfacla0s1.h $crqp,$crpp */
{
MEP_INSN_CPFACLA0S1_H_P0S, "cpfacla0s1_h_P0S", "cpfacla0s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S), 0 } } } }
},
/* cpfsftbi $crop,$crqp,$crpp,$imm3p5 */
{
MEP_INSN_CPFSFTBI_P0_P1, "cpfsftbi_P0_P1", "cpfsftbi", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpeq.b $crqp,$crpp */
{
MEP_INSN_CPACMPEQ_B_P0_P1, "cpacmpeq_b_P0_P1", "cpacmpeq.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpeq.h $crqp,$crpp */
{
MEP_INSN_CPACMPEQ_H_P0_P1, "cpacmpeq_h_P0_P1", "cpacmpeq.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpeq.w $crqp,$crpp */
{
MEP_INSN_CPACMPEQ_W_P0_P1, "cpacmpeq_w_P0_P1", "cpacmpeq.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpne.b $crqp,$crpp */
{
MEP_INSN_CPACMPNE_B_P0_P1, "cpacmpne_b_P0_P1", "cpacmpne.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpne.h $crqp,$crpp */
{
MEP_INSN_CPACMPNE_H_P0_P1, "cpacmpne_h_P0_P1", "cpacmpne.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpne.w $crqp,$crpp */
{
MEP_INSN_CPACMPNE_W_P0_P1, "cpacmpne_w_P0_P1", "cpacmpne.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpgtu.b $crqp,$crpp */
{
MEP_INSN_CPACMPGTU_B_P0_P1, "cpacmpgtu_b_P0_P1", "cpacmpgtu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpgt.b $crqp,$crpp */
{
MEP_INSN_CPACMPGT_B_P0_P1, "cpacmpgt_b_P0_P1", "cpacmpgt.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpgt.h $crqp,$crpp */
{
MEP_INSN_CPACMPGT_H_P0_P1, "cpacmpgt_h_P0_P1", "cpacmpgt.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpgtu.w $crqp,$crpp */
{
MEP_INSN_CPACMPGTU_W_P0_P1, "cpacmpgtu_w_P0_P1", "cpacmpgtu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpgt.w $crqp,$crpp */
{
MEP_INSN_CPACMPGT_W_P0_P1, "cpacmpgt_w_P0_P1", "cpacmpgt.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpgeu.b $crqp,$crpp */
{
MEP_INSN_CPACMPGEU_B_P0_P1, "cpacmpgeu_b_P0_P1", "cpacmpgeu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpge.b $crqp,$crpp */
{
MEP_INSN_CPACMPGE_B_P0_P1, "cpacmpge_b_P0_P1", "cpacmpge.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpge.h $crqp,$crpp */
{
MEP_INSN_CPACMPGE_H_P0_P1, "cpacmpge_h_P0_P1", "cpacmpge.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpgeu.w $crqp,$crpp */
{
MEP_INSN_CPACMPGEU_W_P0_P1, "cpacmpgeu_w_P0_P1", "cpacmpgeu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpacmpge.w $crqp,$crpp */
{
MEP_INSN_CPACMPGE_W_P0_P1, "cpacmpge_w_P0_P1", "cpacmpge.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpeq.b $crqp,$crpp */
{
MEP_INSN_CPOCMPEQ_B_P0_P1, "cpocmpeq_b_P0_P1", "cpocmpeq.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpeq.h $crqp,$crpp */
{
MEP_INSN_CPOCMPEQ_H_P0_P1, "cpocmpeq_h_P0_P1", "cpocmpeq.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpeq.w $crqp,$crpp */
{
MEP_INSN_CPOCMPEQ_W_P0_P1, "cpocmpeq_w_P0_P1", "cpocmpeq.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpne.b $crqp,$crpp */
{
MEP_INSN_CPOCMPNE_B_P0_P1, "cpocmpne_b_P0_P1", "cpocmpne.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpne.h $crqp,$crpp */
{
MEP_INSN_CPOCMPNE_H_P0_P1, "cpocmpne_h_P0_P1", "cpocmpne.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpne.w $crqp,$crpp */
{
MEP_INSN_CPOCMPNE_W_P0_P1, "cpocmpne_w_P0_P1", "cpocmpne.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpgtu.b $crqp,$crpp */
{
MEP_INSN_CPOCMPGTU_B_P0_P1, "cpocmpgtu_b_P0_P1", "cpocmpgtu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpgt.b $crqp,$crpp */
{
MEP_INSN_CPOCMPGT_B_P0_P1, "cpocmpgt_b_P0_P1", "cpocmpgt.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpgt.h $crqp,$crpp */
{
MEP_INSN_CPOCMPGT_H_P0_P1, "cpocmpgt_h_P0_P1", "cpocmpgt.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpgtu.w $crqp,$crpp */
{
MEP_INSN_CPOCMPGTU_W_P0_P1, "cpocmpgtu_w_P0_P1", "cpocmpgtu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpgt.w $crqp,$crpp */
{
MEP_INSN_CPOCMPGT_W_P0_P1, "cpocmpgt_w_P0_P1", "cpocmpgt.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpgeu.b $crqp,$crpp */
{
MEP_INSN_CPOCMPGEU_B_P0_P1, "cpocmpgeu_b_P0_P1", "cpocmpgeu.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpge.b $crqp,$crpp */
{
MEP_INSN_CPOCMPGE_B_P0_P1, "cpocmpge_b_P0_P1", "cpocmpge.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpge.h $crqp,$crpp */
{
MEP_INSN_CPOCMPGE_H_P0_P1, "cpocmpge_h_P0_P1", "cpocmpge.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpgeu.w $crqp,$crpp */
{
MEP_INSN_CPOCMPGEU_W_P0_P1, "cpocmpgeu_w_P0_P1", "cpocmpgeu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpocmpge.w $crqp,$crpp */
{
MEP_INSN_CPOCMPGE_W_P0_P1, "cpocmpge_w_P0_P1", "cpocmpge.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdadd3 $crop,$crqp,$crpp */
{
MEP_INSN_CDADD3_P0_P1, "cdadd3_P0_P1", "cdadd3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsub3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPSUB3_B_P0_P1, "cpsub3_b_P0_P1", "cpsub3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsub3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSUB3_H_P0_P1, "cpsub3_h_P0_P1", "cpsub3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsub3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSUB3_W_P0_P1, "cpsub3_w_P0_P1", "cpsub3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdsub3 $crop,$crqp,$crpp */
{
MEP_INSN_CDSUB3_P0_P1, "cdsub3_P0_P1", "cdsub3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsadd3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSADD3_H_P0_P1, "cpsadd3_h_P0_P1", "cpsadd3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsadd3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSADD3_W_P0_P1, "cpsadd3_w_P0_P1", "cpsadd3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssub3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSSUB3_H_P0_P1, "cpssub3_h_P0_P1", "cpssub3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssub3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSSUB3_W_P0_P1, "cpssub3_w_P0_P1", "cpssub3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextuaddu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTUADDU3_B_P0_P1, "cpextuaddu3_b_P0_P1", "cpextuaddu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextuadd3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTUADD3_B_P0_P1, "cpextuadd3_b_P0_P1", "cpextuadd3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextladdu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTLADDU3_B_P0_P1, "cpextladdu3_b_P0_P1", "cpextladdu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextladd3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTLADD3_B_P0_P1, "cpextladd3_b_P0_P1", "cpextladd3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextusubu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTUSUBU3_B_P0_P1, "cpextusubu3_b_P0_P1", "cpextusubu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextusub3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTUSUB3_B_P0_P1, "cpextusub3_b_P0_P1", "cpextusub3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextlsubu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTLSUBU3_B_P0_P1, "cpextlsubu3_b_P0_P1", "cpextlsubu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpextlsub3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPEXTLSUB3_B_P0_P1, "cpextlsub3_b_P0_P1", "cpextlsub3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpaveu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPAVEU3_B_P0_P1, "cpaveu3_b_P0_P1", "cpaveu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpave3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPAVE3_B_P0_P1, "cpave3_b_P0_P1", "cpave3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpave3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPAVE3_H_P0_P1, "cpave3_h_P0_P1", "cpave3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpave3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPAVE3_W_P0_P1, "cpave3_w_P0_P1", "cpave3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpaddsru3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPADDSRU3_B_P0_P1, "cpaddsru3_b_P0_P1", "cpaddsru3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpaddsr3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPADDSR3_B_P0_P1, "cpaddsr3_b_P0_P1", "cpaddsr3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpaddsr3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPADDSR3_H_P0_P1, "cpaddsr3_h_P0_P1", "cpaddsr3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpaddsr3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPADDSR3_W_P0_P1, "cpaddsr3_w_P0_P1", "cpaddsr3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpabsu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPABSU3_B_P0_P1, "cpabsu3_b_P0_P1", "cpabsu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpabs3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPABS3_B_P0_P1, "cpabs3_b_P0_P1", "cpabs3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpabs3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPABS3_H_P0_P1, "cpabs3_h_P0_P1", "cpabs3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpand3 $crop,$crqp,$crpp */
{
MEP_INSN_CPAND3_P0_P1, "cpand3_P0_P1", "cpand3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpor3 $crop,$crqp,$crpp */
{
MEP_INSN_CPOR3_P0_P1, "cpor3_P0_P1", "cpor3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpnor3 $crop,$crqp,$crpp */
{
MEP_INSN_CPNOR3_P0_P1, "cpnor3_P0_P1", "cpnor3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpxor3 $crop,$crqp,$crpp */
{
MEP_INSN_CPXOR3_P0_P1, "cpxor3_P0_P1", "cpxor3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_VECT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cppacku.b $crop,$crqp,$crpp */
{
MEP_INSN_CPPACKU_B_P0_P1, "cppacku_b_P0_P1", "cppacku.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cppack.b $crop,$crqp,$crpp */
{
MEP_INSN_CPPACK_B_P0_P1, "cppack_b_P0_P1", "cppack.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cppack.h $crop,$crqp,$crpp */
{
MEP_INSN_CPPACK_H_P0_P1, "cppack_h_P0_P1", "cppack.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmaxu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPMAXU3_B_P0_P1, "cpmaxu3_b_P0_P1", "cpmaxu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmax3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPMAX3_B_P0_P1, "cpmax3_b_P0_P1", "cpmax3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmax3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPMAX3_H_P0_P1, "cpmax3_h_P0_P1", "cpmax3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmaxu3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPMAXU3_W_P0_P1, "cpmaxu3_w_P0_P1", "cpmaxu3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmax3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPMAX3_W_P0_P1, "cpmax3_w_P0_P1", "cpmax3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpminu3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPMINU3_B_P0_P1, "cpminu3_b_P0_P1", "cpminu3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmin3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPMIN3_B_P0_P1, "cpmin3_b_P0_P1", "cpmin3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmin3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPMIN3_H_P0_P1, "cpmin3_h_P0_P1", "cpmin3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpminu3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPMINU3_W_P0_P1, "cpminu3_w_P0_P1", "cpminu3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmin3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPMIN3_W_P0_P1, "cpmin3_w_P0_P1", "cpmin3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrl3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPSRL3_B_P0_P1, "cpsrl3_b_P0_P1", "cpsrl3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssrl3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPSSRL3_B_P0_P1, "cpssrl3_b_P0_P1", "cpssrl3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrl3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSRL3_H_P0_P1, "cpsrl3_h_P0_P1", "cpsrl3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssrl3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSSRL3_H_P0_P1, "cpssrl3_h_P0_P1", "cpssrl3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrl3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSRL3_W_P0_P1, "cpsrl3_w_P0_P1", "cpsrl3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssrl3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSSRL3_W_P0_P1, "cpssrl3_w_P0_P1", "cpssrl3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdsrl3 $crop,$crqp,$crpp */
{
MEP_INSN_CDSRL3_P0_P1, "cdsrl3_P0_P1", "cdsrl3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsra3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPSRA3_B_P0_P1, "cpsra3_b_P0_P1", "cpsra3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssra3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPSSRA3_B_P0_P1, "cpssra3_b_P0_P1", "cpssra3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsra3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSRA3_H_P0_P1, "cpsra3_h_P0_P1", "cpsra3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssra3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSSRA3_H_P0_P1, "cpssra3_h_P0_P1", "cpssra3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsra3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSRA3_W_P0_P1, "cpsra3_w_P0_P1", "cpsra3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssra3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSSRA3_W_P0_P1, "cpssra3_w_P0_P1", "cpssra3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdsra3 $crop,$crqp,$crpp */
{
MEP_INSN_CDSRA3_P0_P1, "cdsra3_P0_P1", "cdsra3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsll3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPSLL3_B_P0_P1, "cpsll3_b_P0_P1", "cpsll3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssll3.b $crop,$crqp,$crpp */
{
MEP_INSN_CPSSLL3_B_P0_P1, "cpssll3_b_P0_P1", "cpssll3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsll3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSLL3_H_P0_P1, "cpsll3_h_P0_P1", "cpsll3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssll3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSSLL3_H_P0_P1, "cpssll3_h_P0_P1", "cpssll3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsll3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSLL3_W_P0_P1, "cpsll3_w_P0_P1", "cpsll3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpssll3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSSLL3_W_P0_P1, "cpssll3_w_P0_P1", "cpssll3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdsll3 $crop,$crqp,$crpp */
{
MEP_INSN_CDSLL3_P0_P1, "cdsll3_P0_P1", "cdsll3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsla3.h $crop,$crqp,$crpp */
{
MEP_INSN_CPSLA3_H_P0_P1, "cpsla3_h_P0_P1", "cpsla3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsla3.w $crop,$crqp,$crpp */
{
MEP_INSN_CPSLA3_W_P0_P1, "cpsla3_w_P0_P1", "cpsla3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrli3.b $crop,$crqp,$imm3p5 */
{
MEP_INSN_CPSRLI3_B_P0_P1, "cpsrli3_b_P0_P1", "cpsrli3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrli3.h $crop,$crqp,$imm4p4 */
{
MEP_INSN_CPSRLI3_H_P0_P1, "cpsrli3_h_P0_P1", "cpsrli3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrli3.w $crop,$crqp,$imm5p3 */
{
MEP_INSN_CPSRLI3_W_P0_P1, "cpsrli3_w_P0_P1", "cpsrli3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdsrli3 $crop,$crqp,$imm6p2 */
{
MEP_INSN_CDSRLI3_P0_P1, "cdsrli3_P0_P1", "cdsrli3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrai3.b $crop,$crqp,$imm3p5 */
{
MEP_INSN_CPSRAI3_B_P0_P1, "cpsrai3_b_P0_P1", "cpsrai3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrai3.h $crop,$crqp,$imm4p4 */
{
MEP_INSN_CPSRAI3_H_P0_P1, "cpsrai3_h_P0_P1", "cpsrai3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpsrai3.w $crop,$crqp,$imm5p3 */
{
MEP_INSN_CPSRAI3_W_P0_P1, "cpsrai3_w_P0_P1", "cpsrai3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdsrai3 $crop,$crqp,$imm6p2 */
{
MEP_INSN_CDSRAI3_P0_P1, "cdsrai3_P0_P1", "cdsrai3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpslli3.b $crop,$crqp,$imm3p5 */
{
MEP_INSN_CPSLLI3_B_P0_P1, "cpslli3_b_P0_P1", "cpslli3.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpslli3.h $crop,$crqp,$imm4p4 */
{
MEP_INSN_CPSLLI3_H_P0_P1, "cpslli3_h_P0_P1", "cpslli3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpslli3.w $crop,$crqp,$imm5p3 */
{
MEP_INSN_CPSLLI3_W_P0_P1, "cpslli3_w_P0_P1", "cpslli3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdslli3 $crop,$crqp,$imm6p2 */
{
MEP_INSN_CDSLLI3_P0_P1, "cdslli3_P0_P1", "cdslli3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpslai3.h $crop,$crqp,$imm4p4 */
{
MEP_INSN_CPSLAI3_H_P0_P1, "cpslai3_h_P0_P1", "cpslai3.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpslai3.w $crop,$crqp,$imm5p3 */
{
MEP_INSN_CPSLAI3_W_P0_P1, "cpslai3_w_P0_P1", "cpslai3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpclipiu3.w $crop,$crqp,$imm5p3 */
{
MEP_INSN_CPCLIPIU3_W_P0_P1, "cpclipiu3_w_P0_P1", "cpclipiu3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpclipi3.w $crop,$crqp,$imm5p3 */
{
MEP_INSN_CPCLIPI3_W_P0_P1, "cpclipi3_w_P0_P1", "cpclipi3.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdclipiu3 $crop,$crqp,$imm6p2 */
{
MEP_INSN_CDCLIPIU3_P0_P1, "cdclipiu3_P0_P1", "cdclipiu3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdclipi3 $crop,$crqp,$imm6p2 */
{
MEP_INSN_CDCLIPI3_P0_P1, "cdclipi3_P0_P1", "cdclipi3", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovi.h $crqp,$simm16p0 */
{
MEP_INSN_CPMOVI_H_P0_P1, "cpmovi_h_P0_P1", "cpmovi.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmoviu.w $crqp,$imm16p0 */
{
MEP_INSN_CPMOVIU_W_P0_P1, "cpmoviu_w_P0_P1", "cpmoviu.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cpmovi.w $crqp,$simm16p0 */
{
MEP_INSN_CPMOVI_W_P0_P1, "cpmovi_w_P0_P1", "cpmovi.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdmoviu $crqp,$imm16p0 */
{
MEP_INSN_CDMOVIU_P0_P1, "cdmoviu_P0_P1", "cdmoviu", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* cdmovi $crqp,$simm16p0 */
{
MEP_INSN_CDMOVI_P0_P1, "cdmovi_P0_P1", "cdmovi", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0)|(1<<SLOTS_P1), 0 } } } }
},
/* c1nop */
{
MEP_INSN_C1NOP_P1, "c1nop_P1", "c1nop", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovi.b $crqp,$simm8p20 */
{
MEP_INSN_CPMOVI_B_P0S_P1, "cpmovi_b_P0S_P1", "cpmovi.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x24" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P0S)|(1<<SLOTS_P1), 0 } } } }
},
/* cpadda1u.b $crqp,$crpp */
{
MEP_INSN_CPADDA1U_B_P1, "cpadda1u_b_P1", "cpadda1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpadda1.b $crqp,$crpp */
{
MEP_INSN_CPADDA1_B_P1, "cpadda1_b_P1", "cpadda1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpaddua1.h $crqp,$crpp */
{
MEP_INSN_CPADDUA1_H_P1, "cpaddua1_h_P1", "cpaddua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpaddla1.h $crqp,$crpp */
{
MEP_INSN_CPADDLA1_H_P1, "cpaddla1_h_P1", "cpaddla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpaddaca1u.b $crqp,$crpp */
{
MEP_INSN_CPADDACA1U_B_P1, "cpaddaca1u_b_P1", "cpaddaca1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpaddaca1.b $crqp,$crpp */
{
MEP_INSN_CPADDACA1_B_P1, "cpaddaca1_b_P1", "cpaddaca1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpaddacua1.h $crqp,$crpp */
{
MEP_INSN_CPADDACUA1_H_P1, "cpaddacua1_h_P1", "cpaddacua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpaddacla1.h $crqp,$crpp */
{
MEP_INSN_CPADDACLA1_H_P1, "cpaddacla1_h_P1", "cpaddacla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsuba1u.b $crqp,$crpp */
{
MEP_INSN_CPSUBA1U_B_P1, "cpsuba1u_b_P1", "cpsuba1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsuba1.b $crqp,$crpp */
{
MEP_INSN_CPSUBA1_B_P1, "cpsuba1_b_P1", "cpsuba1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsubua1.h $crqp,$crpp */
{
MEP_INSN_CPSUBUA1_H_P1, "cpsubua1_h_P1", "cpsubua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsubla1.h $crqp,$crpp */
{
MEP_INSN_CPSUBLA1_H_P1, "cpsubla1_h_P1", "cpsubla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsubaca1u.b $crqp,$crpp */
{
MEP_INSN_CPSUBACA1U_B_P1, "cpsubaca1u_b_P1", "cpsubaca1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsubaca1.b $crqp,$crpp */
{
MEP_INSN_CPSUBACA1_B_P1, "cpsubaca1_b_P1", "cpsubaca1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsubacua1.h $crqp,$crpp */
{
MEP_INSN_CPSUBACUA1_H_P1, "cpsubacua1_h_P1", "cpsubacua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsubacla1.h $crqp,$crpp */
{
MEP_INSN_CPSUBACLA1_H_P1, "cpsubacla1_h_P1", "cpsubacla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpabsa1u.b $crqp,$crpp */
{
MEP_INSN_CPABSA1U_B_P1, "cpabsa1u_b_P1", "cpabsa1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpabsa1.b $crqp,$crpp */
{
MEP_INSN_CPABSA1_B_P1, "cpabsa1_b_P1", "cpabsa1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpabsua1.h $crqp,$crpp */
{
MEP_INSN_CPABSUA1_H_P1, "cpabsua1_h_P1", "cpabsua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpabsla1.h $crqp,$crpp */
{
MEP_INSN_CPABSLA1_H_P1, "cpabsla1_h_P1", "cpabsla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsada1u.b $crqp,$crpp */
{
MEP_INSN_CPSADA1U_B_P1, "cpsada1u_b_P1", "cpsada1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsada1.b $crqp,$crpp */
{
MEP_INSN_CPSADA1_B_P1, "cpsada1_b_P1", "cpsada1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsadua1.h $crqp,$crpp */
{
MEP_INSN_CPSADUA1_H_P1, "cpsadua1_h_P1", "cpsadua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsadla1.h $crqp,$crpp */
{
MEP_INSN_CPSADLA1_H_P1, "cpsadla1_h_P1", "cpsadla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpseta1.h $crqp,$crpp */
{
MEP_INSN_CPSETA1_H_P1, "cpseta1_h_P1", "cpseta1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsetua1.w $crqp,$crpp */
{
MEP_INSN_CPSETUA1_W_P1, "cpsetua1_w_P1", "cpsetua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsetla1.w $crqp,$crpp */
{
MEP_INSN_CPSETLA1_W_P1, "cpsetla1_w_P1", "cpsetla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmova1.b $crop */
{
MEP_INSN_CPMOVA1_B_P1, "cpmova1_b_P1", "cpmova1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovua1.h $crop */
{
MEP_INSN_CPMOVUA1_H_P1, "cpmovua1_h_P1", "cpmovua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovla1.h $crop */
{
MEP_INSN_CPMOVLA1_H_P1, "cpmovla1_h_P1", "cpmovla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovuua1.w $crop */
{
MEP_INSN_CPMOVUUA1_W_P1, "cpmovuua1_w_P1", "cpmovuua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovula1.w $crop */
{
MEP_INSN_CPMOVULA1_W_P1, "cpmovula1_w_P1", "cpmovula1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovlua1.w $crop */
{
MEP_INSN_CPMOVLUA1_W_P1, "cpmovlua1_w_P1", "cpmovlua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovlla1.w $crop */
{
MEP_INSN_CPMOVLLA1_W_P1, "cpmovlla1_w_P1", "cpmovlla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cppacka1u.b $crop */
{
MEP_INSN_CPPACKA1U_B_P1, "cppacka1u_b_P1", "cppacka1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cppacka1.b $crop */
{
MEP_INSN_CPPACKA1_B_P1, "cppacka1_b_P1", "cppacka1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cppackua1.h $crop */
{
MEP_INSN_CPPACKUA1_H_P1, "cppackua1_h_P1", "cppackua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cppackla1.h $crop */
{
MEP_INSN_CPPACKLA1_H_P1, "cppackla1_h_P1", "cppackla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cppackua1.w $crop */
{
MEP_INSN_CPPACKUA1_W_P1, "cppackua1_w_P1", "cppackua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cppackla1.w $crop */
{
MEP_INSN_CPPACKLA1_W_P1, "cppackla1_w_P1", "cppackla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovhua1.w $crop */
{
MEP_INSN_CPMOVHUA1_W_P1, "cpmovhua1_w_P1", "cpmovhua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmovhla1.w $crop */
{
MEP_INSN_CPMOVHLA1_W_P1, "cpmovhla1_w_P1", "cpmovhla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_FIRST, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpacsuma1 */
{
MEP_INSN_CPACSUMA1_P1, "cpacsuma1_P1", "cpacsuma1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpaccpa1 */
{
MEP_INSN_CPACCPA1_P1, "cpaccpa1_P1", "cpaccpa1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpacswp */
{
MEP_INSN_CPACSWP_P1, "cpacswp_P1", "cpacswp", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(VOLATILE)|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsrla1 $crqp */
{
MEP_INSN_CPSRLA1_P1, "cpsrla1_P1", "cpsrla1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsraa1 $crqp */
{
MEP_INSN_CPSRAA1_P1, "cpsraa1_P1", "cpsraa1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpslla1 $crqp */
{
MEP_INSN_CPSLLA1_P1, "cpslla1_P1", "cpslla1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsrlia1 $imm5p23 */
{
MEP_INSN_CPSRLIA1_1_P1, "cpsrlia1_1_p1", "cpsrlia1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsraia1 $imm5p23 */
{
MEP_INSN_CPSRAIA1_1_P1, "cpsraia1_1_p1", "cpsraia1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsllia1 $imm5p23 */
{
MEP_INSN_CPSLLIA1_1_P1, "cpsllia1_1_p1", "cpsllia1", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulia1s0u.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULIA1S0U_B_P1, "cpfmulia1s0u_b_P1", "cpfmulia1s0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulia1s0.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULIA1S0_B_P1, "cpfmulia1s0_b_P1", "cpfmulia1s0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmuliua1s0.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULIUA1S0_H_P1, "cpfmuliua1s0_h_P1", "cpfmuliua1s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulila1s0.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULILA1S0_H_P1, "cpfmulila1s0_h_P1", "cpfmulila1s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadia1s0u.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADIA1S0U_B_P1, "cpfmadia1s0u_b_P1", "cpfmadia1s0u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadia1s0.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADIA1S0_B_P1, "cpfmadia1s0_b_P1", "cpfmadia1s0.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadiua1s0.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADIUA1S0_H_P1, "cpfmadiua1s0_h_P1", "cpfmadiua1s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadila1s0.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADILA1S0_H_P1, "cpfmadila1s0_h_P1", "cpfmadila1s0.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulia1s1u.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULIA1S1U_B_P1, "cpfmulia1s1u_b_P1", "cpfmulia1s1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulia1s1.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULIA1S1_B_P1, "cpfmulia1s1_b_P1", "cpfmulia1s1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmuliua1s1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULIUA1S1_H_P1, "cpfmuliua1s1_h_P1", "cpfmuliua1s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulila1s1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMULILA1S1_H_P1, "cpfmulila1s1_h_P1", "cpfmulila1s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadia1s1u.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADIA1S1U_B_P1, "cpfmadia1s1u_b_P1", "cpfmadia1s1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadia1s1.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADIA1S1_B_P1, "cpfmadia1s1_b_P1", "cpfmadia1s1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadiua1s1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADIUA1S1_H_P1, "cpfmadiua1s1_h_P1", "cpfmadiua1s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadila1s1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPFMADILA1S1_H_P1, "cpfmadila1s1_h_P1", "cpfmadila1s1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamulia1u.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMULIA1U_B_P1, "cpamulia1u_b_P1", "cpamulia1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamulia1.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMULIA1_B_P1, "cpamulia1_b_P1", "cpamulia1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamuliua1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMULIUA1_H_P1, "cpamuliua1_h_P1", "cpamuliua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamulila1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMULILA1_H_P1, "cpamulila1_h_P1", "cpamulila1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamadia1u.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMADIA1U_B_P1, "cpamadia1u_b_P1", "cpamadia1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamadia1.b $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMADIA1_B_P1, "cpamadia1_b_P1", "cpamadia1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamadiua1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMADIUA1_H_P1, "cpamadiua1_h_P1", "cpamadiua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpamadila1.h $crqp,$crpp,$simm8p0 */
{
MEP_INSN_CPAMADILA1_H_P1, "cpamadila1_h_P1", "cpamadila1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMULIA1U_B_P1, "cpfmulia1u_b_P1", "cpfmulia1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMULIA1_B_P1, "cpfmulia1_b_P1", "cpfmulia1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmuliua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMULIUA1_H_P1, "cpfmuliua1_h_P1", "cpfmuliua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmulila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMULILA1_H_P1, "cpfmulila1_h_P1", "cpfmulila1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadia1u.b $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMADIA1U_B_P1, "cpfmadia1u_b_P1", "cpfmadia1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadia1.b $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMADIA1_B_P1, "cpfmadia1_b_P1", "cpfmadia1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadiua1.h $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMADIUA1_H_P1, "cpfmadiua1_h_P1", "cpfmadiua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpfmadila1.h $crqp,$crpp,$imm3p25,$simm8p0 */
{
MEP_INSN_CPFMADILA1_H_P1, "cpfmadila1_h_P1", "cpfmadila1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpssqa1u.b $crqp,$crpp */
{
MEP_INSN_CPSSQA1U_B_P1, "cpssqa1u_b_P1", "cpssqa1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpssqa1.b $crqp,$crpp */
{
MEP_INSN_CPSSQA1_B_P1, "cpssqa1_b_P1", "cpssqa1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpssda1u.b $crqp,$crpp */
{
MEP_INSN_CPSSDA1U_B_P1, "cpssda1u_b_P1", "cpssda1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpssda1.b $crqp,$crpp */
{
MEP_INSN_CPSSDA1_B_P1, "cpssda1_b_P1", "cpssda1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmula1u.b $crqp,$crpp */
{
MEP_INSN_CPMULA1U_B_P1, "cpmula1u_b_P1", "cpmula1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmula1.b $crqp,$crpp */
{
MEP_INSN_CPMULA1_B_P1, "cpmula1_b_P1", "cpmula1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulua1.h $crqp,$crpp */
{
MEP_INSN_CPMULUA1_H_P1, "cpmulua1_h_P1", "cpmulua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulla1.h $crqp,$crpp */
{
MEP_INSN_CPMULLA1_H_P1, "cpmulla1_h_P1", "cpmulla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulua1u.w $crqp,$crpp */
{
MEP_INSN_CPMULUA1U_W_P1, "cpmulua1u_w_P1", "cpmulua1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulla1u.w $crqp,$crpp */
{
MEP_INSN_CPMULLA1U_W_P1, "cpmulla1u_w_P1", "cpmulla1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulua1.w $crqp,$crpp */
{
MEP_INSN_CPMULUA1_W_P1, "cpmulua1_w_P1", "cpmulua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulla1.w $crqp,$crpp */
{
MEP_INSN_CPMULLA1_W_P1, "cpmulla1_w_P1", "cpmulla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmada1u.b $crqp,$crpp */
{
MEP_INSN_CPMADA1U_B_P1, "cpmada1u_b_P1", "cpmada1u.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8UQI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmada1.b $crqp,$crpp */
{
MEP_INSN_CPMADA1_B_P1, "cpmada1_b_P1", "cpmada1.b", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V8QI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmadua1.h $crqp,$crpp */
{
MEP_INSN_CPMADUA1_H_P1, "cpmadua1_h_P1", "cpmadua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmadla1.h $crqp,$crpp */
{
MEP_INSN_CPMADLA1_H_P1, "cpmadla1_h_P1", "cpmadla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmadua1u.w $crqp,$crpp */
{
MEP_INSN_CPMADUA1U_W_P1, "cpmadua1u_w_P1", "cpmadua1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmadla1u.w $crqp,$crpp */
{
MEP_INSN_CPMADLA1U_W_P1, "cpmadla1u_w_P1", "cpmadla1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmadua1.w $crqp,$crpp */
{
MEP_INSN_CPMADUA1_W_P1, "cpmadua1_w_P1", "cpmadua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmadla1.w $crqp,$crpp */
{
MEP_INSN_CPMADLA1_W_P1, "cpmadla1_w_P1", "cpmadla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmsbua1.h $crqp,$crpp */
{
MEP_INSN_CPMSBUA1_H_P1, "cpmsbua1_h_P1", "cpmsbua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmsbla1.h $crqp,$crpp */
{
MEP_INSN_CPMSBLA1_H_P1, "cpmsbla1_h_P1", "cpmsbla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmsbua1u.w $crqp,$crpp */
{
MEP_INSN_CPMSBUA1U_W_P1, "cpmsbua1u_w_P1", "cpmsbua1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmsbla1u.w $crqp,$crpp */
{
MEP_INSN_CPMSBLA1U_W_P1, "cpmsbla1u_w_P1", "cpmsbla1u.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2USI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmsbua1.w $crqp,$crpp */
{
MEP_INSN_CPMSBUA1_W_P1, "cpmsbua1_w_P1", "cpmsbua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmsbla1.w $crqp,$crpp */
{
MEP_INSN_CPMSBLA1_W_P1, "cpmsbla1_w_P1", "cpmsbla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadua1.h $crqp,$crpp */
{
MEP_INSN_CPSMADUA1_H_P1, "cpsmadua1_h_P1", "cpsmadua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadla1.h $crqp,$crpp */
{
MEP_INSN_CPSMADLA1_H_P1, "cpsmadla1_h_P1", "cpsmadla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadua1.w $crqp,$crpp */
{
MEP_INSN_CPSMADUA1_W_P1, "cpsmadua1_w_P1", "cpsmadua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadla1.w $crqp,$crpp */
{
MEP_INSN_CPSMADLA1_W_P1, "cpsmadla1_w_P1", "cpsmadla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbua1.h $crqp,$crpp */
{
MEP_INSN_CPSMSBUA1_H_P1, "cpsmsbua1_h_P1", "cpsmsbua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbla1.h $crqp,$crpp */
{
MEP_INSN_CPSMSBLA1_H_P1, "cpsmsbla1_h_P1", "cpsmsbla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbua1.w $crqp,$crpp */
{
MEP_INSN_CPSMSBUA1_W_P1, "cpsmsbua1_w_P1", "cpsmsbua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbla1.w $crqp,$crpp */
{
MEP_INSN_CPSMSBLA1_W_P1, "cpsmsbla1_w_P1", "cpsmsbla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulslua1.h $crqp,$crpp */
{
MEP_INSN_CPMULSLUA1_H_P1, "cpmulslua1_h_P1", "cpmulslua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulslla1.h $crqp,$crpp */
{
MEP_INSN_CPMULSLLA1_H_P1, "cpmulslla1_h_P1", "cpmulslla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulslua1.w $crqp,$crpp */
{
MEP_INSN_CPMULSLUA1_W_P1, "cpmulslua1_w_P1", "cpmulslua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpmulslla1.w $crqp,$crpp */
{
MEP_INSN_CPMULSLLA1_W_P1, "cpmulslla1_w_P1", "cpmulslla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadslua1.h $crqp,$crpp */
{
MEP_INSN_CPSMADSLUA1_H_P1, "cpsmadslua1_h_P1", "cpsmadslua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadslla1.h $crqp,$crpp */
{
MEP_INSN_CPSMADSLLA1_H_P1, "cpsmadslla1_h_P1", "cpsmadslla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadslua1.w $crqp,$crpp */
{
MEP_INSN_CPSMADSLUA1_W_P1, "cpsmadslua1_w_P1", "cpsmadslua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmadslla1.w $crqp,$crpp */
{
MEP_INSN_CPSMADSLLA1_W_P1, "cpsmadslla1_w_P1", "cpsmadslla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbslua1.h $crqp,$crpp */
{
MEP_INSN_CPSMSBSLUA1_H_P1, "cpsmsbslua1_h_P1", "cpsmsbslua1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbslla1.h $crqp,$crpp */
{
MEP_INSN_CPSMSBSLLA1_H_P1, "cpsmsbslla1_h_P1", "cpsmsbslla1.h", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V4HI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbslua1.w $crqp,$crpp */
{
MEP_INSN_CPSMSBSLUA1_W_P1, "cpsmsbslua1_w_P1", "cpsmsbslua1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
/* cpsmsbslla1.w $crqp,$crpp */
{
MEP_INSN_CPSMSBSLLA1_W_P1, "cpsmsbslla1_w_P1", "cpsmsbslla1.w", 32,
- { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
+ { 0|A(OPTIONAL_CP_INSN), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x4" } }, { { CPTYPE_V2SI, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_P1), 0 } } } }
},
};
Index: opcodes/mep-desc.h
===================================================================
RCS file: /cvs/src/src/opcodes/mep-desc.h,v
retrieving revision 1.7
diff -p -U3 -r1.7 mep-desc.h
--- opcodes/mep-desc.h 27 May 2009 01:49:45 -0000 1.7
+++ opcodes/mep-desc.h 24 Jun 2009 02:59:28 -0000
@@ -92,6 +92,17 @@ typedef enum cdata_attr {
, CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
} CDATA_ATTR;
+/* Enum declaration for datatype to use for coprocessor values. */
+typedef enum cptype_attr {
+ CPTYPE_CP_DATA_BUS_INT, CPTYPE_VECT, CPTYPE_V2SI, CPTYPE_V4HI
+ , CPTYPE_V8QI, CPTYPE_V2USI, CPTYPE_V4UHI, CPTYPE_V8UQI
+} CPTYPE_ATTR;
+
+/* Enum declaration for Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.. */
+typedef enum cret_attr {
+ CRET_VOID, CRET_FIRST, CRET_FIRSTCOPY
+} CRET_ATTR;
+
/* Enum declaration for . */
typedef enum config_attr {
CONFIG_NONE, CONFIG_DEFAULT
@@ -258,21 +269,27 @@ typedef enum cgen_operand_type {
, MEP_OPERAND_UDISP7A4, MEP_OPERAND_UIMM7A4, MEP_OPERAND_UIMM24, MEP_OPERAND_CIMM4
, MEP_OPERAND_CIMM5, MEP_OPERAND_CDISP10, MEP_OPERAND_CDISP10A2, MEP_OPERAND_CDISP10A4
, MEP_OPERAND_CDISP10A8, MEP_OPERAND_ZERO, MEP_OPERAND_RL5, MEP_OPERAND_CDISP12
- , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_CROC
- , MEP_OPERAND_CRQC, MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2
- , MEP_OPERAND_IVC_X_6_3, MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8
- , MEP_OPERAND_IMM5P7, MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4
- , MEP_OPERAND_IMM3P5, MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10
- , MEP_OPERAND_IMM5P8, MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23
- , MEP_OPERAND_IMM3P25, MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20
- , MEP_OPERAND_IMM8P20, MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP
- , MEP_OPERAND_IVC_X_0_2, MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5
- , MEP_OPERAND_IMM16P0, MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN
- , MEP_OPERAND_IVC2CCRN, MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX
+ , MEP_OPERAND_C5RMUIMM20, MEP_OPERAND_C5RNMUIMM24, MEP_OPERAND_CP_FLAG, MEP_OPERAND_IVC2_CSAR0
+ , MEP_OPERAND_IVC2_CC, MEP_OPERAND_IVC2_COFR0, MEP_OPERAND_IVC2_COFR1, MEP_OPERAND_IVC2_COFA0
+ , MEP_OPERAND_IVC2_COFA1, MEP_OPERAND_IVC2_CSAR1, MEP_OPERAND_IVC2_ACC0_0, MEP_OPERAND_IVC2_ACC0_1
+ , MEP_OPERAND_IVC2_ACC0_2, MEP_OPERAND_IVC2_ACC0_3, MEP_OPERAND_IVC2_ACC0_4, MEP_OPERAND_IVC2_ACC0_5
+ , MEP_OPERAND_IVC2_ACC0_6, MEP_OPERAND_IVC2_ACC0_7, MEP_OPERAND_IVC2_ACC1_0, MEP_OPERAND_IVC2_ACC1_1
+ , MEP_OPERAND_IVC2_ACC1_2, MEP_OPERAND_IVC2_ACC1_3, MEP_OPERAND_IVC2_ACC1_4, MEP_OPERAND_IVC2_ACC1_5
+ , MEP_OPERAND_IVC2_ACC1_6, MEP_OPERAND_IVC2_ACC1_7, MEP_OPERAND_CROC, MEP_OPERAND_CRQC
+ , MEP_OPERAND_CRPC, MEP_OPERAND_IVC_X_6_1, MEP_OPERAND_IVC_X_6_2, MEP_OPERAND_IVC_X_6_3
+ , MEP_OPERAND_IMM3P4, MEP_OPERAND_IMM3P9, MEP_OPERAND_IMM4P8, MEP_OPERAND_IMM5P7
+ , MEP_OPERAND_IMM6P6, MEP_OPERAND_IMM8P4, MEP_OPERAND_SIMM8P4, MEP_OPERAND_IMM3P5
+ , MEP_OPERAND_IMM3P12, MEP_OPERAND_IMM4P4, MEP_OPERAND_IMM4P10, MEP_OPERAND_IMM5P8
+ , MEP_OPERAND_IMM5P3, MEP_OPERAND_IMM6P2, MEP_OPERAND_IMM5P23, MEP_OPERAND_IMM3P25
+ , MEP_OPERAND_IMM8P0, MEP_OPERAND_SIMM8P0, MEP_OPERAND_SIMM8P20, MEP_OPERAND_IMM8P20
+ , MEP_OPERAND_CROP, MEP_OPERAND_CRQP, MEP_OPERAND_CRPP, MEP_OPERAND_IVC_X_0_2
+ , MEP_OPERAND_IVC_X_0_3, MEP_OPERAND_IVC_X_0_4, MEP_OPERAND_IVC_X_0_5, MEP_OPERAND_IMM16P0
+ , MEP_OPERAND_SIMM16P0, MEP_OPERAND_IVC2RM, MEP_OPERAND_IVC2CRN, MEP_OPERAND_IVC2CCRN
+ , MEP_OPERAND_IVC2C3CCRN, MEP_OPERAND_MAX
} CGEN_OPERAND_TYPE;
/* Number of operands types. */
-#define MAX_OPERANDS 122
+#define MAX_OPERANDS 145
/* Maximum number of operands referenced by any insn. */
#define MAX_OPERAND_INSTANCES 8
@@ -290,7 +307,8 @@ typedef enum cgen_insn_attr {
, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
- , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_CPTYPE, CGEN_INSN_CRET, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG
+ , CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
@@ -299,6 +317,8 @@ typedef enum cgen_insn_attr {
/* cgen_insn attribute accessor macros. */
#define CGEN_ATTR_CGEN_INSN_MACH_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_MACH-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_ISA_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_ISA-CGEN_INSN_START_NBOOLS-1].bitset)
+#define CGEN_ATTR_CGEN_INSN_CPTYPE_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CPTYPE-CGEN_INSN_START_NBOOLS-1].nonbitset)
+#define CGEN_ATTR_CGEN_INSN_CRET_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CRET-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_LATENCY_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_LATENCY-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_CONFIG_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_CONFIG-CGEN_INSN_START_NBOOLS-1].nonbitset)
#define CGEN_ATTR_CGEN_INSN_SLOTS_VALUE(attrs) ((attrs)->nonbool[CGEN_INSN_SLOTS-CGEN_INSN_START_NBOOLS-1].nonbitset)
Index: opcodes/mep-dis.c
===================================================================
RCS file: /cvs/src/src/opcodes/mep-dis.c,v
retrieving revision 1.8
diff -p -U3 -r1.8 mep-dis.c
--- opcodes/mep-dis.c 27 May 2009 01:49:45 -0000 1.8
+++ opcodes/mep-dis.c 24 Jun 2009 02:59:28 -0000
@@ -928,6 +928,75 @@ mep_cgen_print_operand (CGEN_CPU_DESC cd
case MEP_OPERAND_IVC_X_6_3 :
print_normal (cd, info, fields->f_ivc2_3u6, 0, pc, length);
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, 0, 0);
+ break;
case MEP_OPERAND_IVC2C3CCRN :
print_keyword (cd, info, & mep_cgen_opval_h_ccr_ivc2, fields->f_ivc2_ccrn_c3, 0|(1<<CGEN_OPERAND_VIRTUAL));
break;
Index: opcodes/mep-ibld.c
===================================================================
RCS file: /cvs/src/src/opcodes/mep-ibld.c,v
retrieving revision 1.9
diff -p -U3 -r1.9 mep-ibld.c
--- opcodes/mep-ibld.c 27 May 2009 01:49:45 -0000 1.9
+++ opcodes/mep-ibld.c 24 Jun 2009 02:59:28 -0000
@@ -878,6 +878,52 @@ mep_cgen_insert_operand (CGEN_CPU_DESC c
case MEP_OPERAND_IVC_X_6_3 :
errmsg = insert_normal (cd, fields->f_ivc2_3u6, 0, 0, 6, 3, 32, total_length, buffer);
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ break;
case MEP_OPERAND_IVC2C3CCRN :
{
{
@@ -1459,6 +1505,52 @@ mep_cgen_extract_operand (CGEN_CPU_DESC
case MEP_OPERAND_IVC_X_6_3 :
length = extract_normal (cd, ex_info, insn_value, 0, 0, 6, 3, 32, total_length, pc, & fields->f_ivc2_3u6);
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ break;
case MEP_OPERAND_IVC2C3CCRN :
{
length = extract_normal (cd, ex_info, insn_value, 0, 0, 28, 2, 32, total_length, pc, & fields->f_ivc2_ccrn_c3hi);
@@ -1917,6 +2009,75 @@ mep_cgen_get_int_operand (CGEN_CPU_DESC
case MEP_OPERAND_IVC_X_6_3 :
value = fields->f_ivc2_3u6;
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ value = 0;
+ break;
case MEP_OPERAND_IVC2C3CCRN :
value = fields->f_ivc2_ccrn_c3;
break;
@@ -2300,6 +2461,75 @@ mep_cgen_get_vma_operand (CGEN_CPU_DESC
case MEP_OPERAND_IVC_X_6_3 :
value = fields->f_ivc2_3u6;
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ value = 0;
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ value = 0;
+ break;
case MEP_OPERAND_IVC2C3CCRN :
value = fields->f_ivc2_ccrn_c3;
break;
@@ -2684,6 +2914,52 @@ mep_cgen_set_int_operand (CGEN_CPU_DESC
case MEP_OPERAND_IVC_X_6_3 :
fields->f_ivc2_3u6 = value;
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ break;
case MEP_OPERAND_IVC2C3CCRN :
fields->f_ivc2_ccrn_c3 = value;
break;
@@ -3041,6 +3317,52 @@ mep_cgen_set_vma_operand (CGEN_CPU_DESC
case MEP_OPERAND_IVC_X_6_3 :
fields->f_ivc2_3u6 = value;
break;
+ case MEP_OPERAND_IVC2_ACC0_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC0_7 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_0 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_1 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_2 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_3 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_4 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_5 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_6 :
+ break;
+ case MEP_OPERAND_IVC2_ACC1_7 :
+ break;
+ case MEP_OPERAND_IVC2_CC :
+ break;
+ case MEP_OPERAND_IVC2_COFA0 :
+ break;
+ case MEP_OPERAND_IVC2_COFA1 :
+ break;
+ case MEP_OPERAND_IVC2_COFR0 :
+ break;
+ case MEP_OPERAND_IVC2_COFR1 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR0 :
+ break;
+ case MEP_OPERAND_IVC2_CSAR1 :
+ break;
case MEP_OPERAND_IVC2C3CCRN :
fields->f_ivc2_ccrn_c3 = value;
break;
Index: opcodes/mep-opc.c
===================================================================
RCS file: /cvs/src/src/opcodes/mep-opc.c,v
retrieving revision 1.11
diff -p -U3 -r1.11 mep-opc.c
--- opcodes/mep-opc.c 24 Jun 2009 01:44:53 -0000 1.11
+++ opcodes/mep-opc.c 24 Jun 2009 02:59:28 -0000
@@ -145,6 +145,12 @@ mep_cgen_insn_supported (CGEN_CPU_DESC c
int ok1;
int ok2;
int ok3;
+
+ /* If we're assembling VLIW packets, ignore the 12-bit BSR as we
+ can't relax that. The 24-bit BSR is matched instead. */
+ if (insn->base->num == MEP_INSN_BSR12
+ && cgen_bitset_contains (cd->isas, ISA_EXT_COP1_64))
+ return 0;
/* If the insn has an option bit set that we don't want,
reject it. */
@@ -6173,67 +6179,67 @@ static const CGEN_IBASE mep_cgen_macro_i
/* nop */
{
-1, "nop", "nop", 16,
- { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sb $rnc,$zero($rma) */
{
-1, "sb16-0", "sb", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sh $rns,$zero($rma) */
{
-1, "sh16-0", "sh", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* sw $rnl,$zero($rma) */
{
-1, "sw16-0", "sw", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lb $rnc,$zero($rma) */
{
-1, "lb16-0", "lb", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lh $rns,$zero($rma) */
{
-1, "lh16-0", "lh", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lw $rnl,$zero($rma) */
{
-1, "lw16-0", "lw", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lbu $rnuc,$zero($rma) */
{
-1, "lbu16-0", "lbu", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lhu $rnus,$zero($rma) */
{
-1, "lhu16-0", "lhu", 16,
- { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* swcp $crn,$zero($rma) */
{
-1, "swcp16-0", "swcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lwcp $crn,$zero($rma) */
{
-1, "lwcp16-0", "lwcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* smcp $crn64,$zero($rma) */
{
-1, "smcp16-0", "smcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
/* lmcp $crn64,$zero($rma) */
{
-1, "lmcp16-0", "lmcp", 16,
- { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
+ { 0|A(NO_DIS)|A(OPTIONAL_CP64_INSN)|A(OPTIONAL_CP_INSN)|A(ALIAS), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xc0" } }, { { CPTYPE_CP_DATA_BUS_INT, 0 } }, { { CRET_VOID, 0 } }, { { 0, 0 } }, { { CONFIG_NONE, 0 } }, { { (1<<SLOTS_CORE), 0 } } } }
},
};
Index: sid/component/cgen-cpu/mep/ivc2-cop.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/ivc2-cop.cxx,v
retrieving revision 1.1
diff -p -U3 -r1.1 ivc2-cop.cxx
--- sid/component/cgen-cpu/mep/ivc2-cop.cxx 30 Apr 2009 21:18:37 -0000 1.1
+++ sid/component/cgen-cpu/mep/ivc2-cop.cxx 24 Jun 2009 02:59:29 -0000
@@ -1604,17 +1604,16 @@ DI mep::mep_cpu_cgen::ivc2_cphadd_w (PCA
}
// 1111 000 ooooo 0111 10001 qqqqq 01100 0 cpccadd.b +crqc (c3_1)
-void mep::mep_cpu_cgen::ivc2_cpccadd_b (PCADDR &pc, SI crqc)
+DI mep::mep_cpu_cgen::ivc2_cpccadd_b (PCADDR &pc, DI crqc)
{
int i;
int cc = ccr (IVC2_CC);
- int q = cr (crqc);
for (i=0; i<8; i++)
if ((cc >> (i*2)) & 3)
- q ++;
+ crqc ++;
- cw (crqc, q);
+ return crqc;
}
// 1111 000 ooooo 0111 10001 qqqqq 01101 0 cpbcast.b =croc,crqc (c3_1)
@@ -4937,8 +4936,6 @@ void mep::mep_cpu_cgen::ivc2_cpsubaca0u_
UQI q[8], p[8];
USI cc;
- cout << "^[[35m cpsubaca1u_b ^[[0m\n";
-
unpack (crqp, q);
unpack (crpp, p);
Index: sid/component/cgen-cpu/mep/ivc2-cpu.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/ivc2-cpu.h,v
retrieving revision 1.1
diff -p -U3 -r1.1 ivc2-cpu.h
--- sid/component/cgen-cpu/mep/ivc2-cpu.h 30 Apr 2009 21:18:37 -0000 1.1
+++ sid/component/cgen-cpu/mep/ivc2-cpu.h 24 Jun 2009 02:59:29 -0000
@@ -50,6 +50,7 @@ public:
DI ivc2_cpcastub_h (PCADDR &pc, DI crqc);
DI ivc2_cpcastub_w (PCADDR &pc, DI crqc);
DI ivc2_cpcastuh_w (PCADDR &pc, DI crqc);
+ DI ivc2_cpccadd_b (PCADDR &pc, DI crqc);
DI ivc2_cpclipi3_w (PCADDR &pc, DI crpc, SI imm5_7);
DI ivc2_cpclipiu3_w (PCADDR &pc, DI crpc, SI imm5_7);
DI ivc2_cpextl_b (PCADDR &pc, DI crqc);
@@ -237,7 +238,6 @@ public:
void ivc2_cpamulia1u_b (PCADDR &pc, DI crqp, DI crpp, SI imm8_0);
void ivc2_cpamulila1_h (PCADDR &pc, DI crqp, DI crpp, SI imm8_0);
void ivc2_cpamuliua1_h (PCADDR &pc, DI crqp, DI crpp, SI imm8_0);
- void ivc2_cpccadd_b (PCADDR &pc, SI crqc);
void ivc2_cpcmpeq_b (PCADDR &pc, DI crqc, DI crpc);
void ivc2_cpcmpeq_h (PCADDR &pc, DI crqc, DI crpc);
void ivc2_cpcmpeq_w (PCADDR &pc, DI crqc, DI crpc);
Index: sid/component/cgen-cpu/mep/mep-cop1-16-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-16-decode.cxx,v
retrieving revision 1.2
diff -p -U3 -r1.2 mep-cop1-16-decode.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-16-decode.cxx 22 May 2009 17:37:43 -0000 1.2
+++ sid/component/cgen-cpu/mep/mep-cop1-16-decode.cxx 24 Jun 2009 02:59:29 -0000
@@ -22,142 +22,142 @@ using namespace mep_ext1; // FIXME: name
mepcop1_16_idesc mepcop1_16_idesc::idesc_table[MEPCOP1_16_INSN_CPMOVI_B_P0S_P1 + 1] =
{
- { mepcop1_16_sem_x_invalid, "X_INVALID", MEPCOP1_16_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcop1_16_sem_c0nop_P0_P0S, "C0NOP_P0_P0S", MEPCOP1_16_INSN_C0NOP_P0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x28" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpadd3_b_P0S_P1, "CPADD3_B_P0S_P1", MEPCOP1_16_INSN_CPADD3_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpadd3_h_P0S_P1, "CPADD3_H_P0S_P1", MEPCOP1_16_INSN_CPADD3_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpadd3_w_P0S_P1, "CPADD3_W_P0S_P1", MEPCOP1_16_INSN_CPADD3_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpunpacku_b_P0S_P1, "CPUNPACKU_B_P0S_P1", MEPCOP1_16_INSN_CPUNPACKU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpunpacku_h_P0S_P1, "CPUNPACKU_H_P0S_P1", MEPCOP1_16_INSN_CPUNPACKU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpunpacku_w_P0S_P1, "CPUNPACKU_W_P0S_P1", MEPCOP1_16_INSN_CPUNPACKU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpunpackl_b_P0S_P1, "CPUNPACKL_B_P0S_P1", MEPCOP1_16_INSN_CPUNPACKL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpunpackl_h_P0S_P1, "CPUNPACKL_H_P0S_P1", MEPCOP1_16_INSN_CPUNPACKL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpunpackl_w_P0S_P1, "CPUNPACKL_W_P0S_P1", MEPCOP1_16_INSN_CPUNPACKL_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpsel_P0S_P1, "CPSEL_P0S_P1", MEPCOP1_16_INSN_CPSEL_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpfsftbs0_P0S_P1, "CPFSFTBS0_P0S_P1", MEPCOP1_16_INSN_CPFSFTBS0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpfsftbs1_P0S_P1, "CPFSFTBS1_P0S_P1", MEPCOP1_16_INSN_CPFSFTBS1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpmov_P0S_P1, "CPMOV_P0S_P1", MEPCOP1_16_INSN_CPMOV_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpabsz_b_P0S_P1, "CPABSZ_B_P0S_P1", MEPCOP1_16_INSN_CPABSZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpabsz_h_P0S_P1, "CPABSZ_H_P0S_P1", MEPCOP1_16_INSN_CPABSZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpabsz_w_P0S_P1, "CPABSZ_W_P0S_P1", MEPCOP1_16_INSN_CPABSZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpldz_h_P0S_P1, "CPLDZ_H_P0S_P1", MEPCOP1_16_INSN_CPLDZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpldz_w_P0S_P1, "CPLDZ_W_P0S_P1", MEPCOP1_16_INSN_CPLDZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpnorm_h_P0S_P1, "CPNORM_H_P0S_P1", MEPCOP1_16_INSN_CPNORM_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpnorm_w_P0S_P1, "CPNORM_W_P0S_P1", MEPCOP1_16_INSN_CPNORM_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cphaddu_b_P0S_P1, "CPHADDU_B_P0S_P1", MEPCOP1_16_INSN_CPHADDU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cphadd_b_P0S_P1, "CPHADD_B_P0S_P1", MEPCOP1_16_INSN_CPHADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cphadd_h_P0S_P1, "CPHADD_H_P0S_P1", MEPCOP1_16_INSN_CPHADD_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cphadd_w_P0S_P1, "CPHADD_W_P0S_P1", MEPCOP1_16_INSN_CPHADD_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpccadd_b_P0S_P1, "CPCCADD_B_P0S_P1", MEPCOP1_16_INSN_CPCCADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpbcast_b_P0S_P1, "CPBCAST_B_P0S_P1", MEPCOP1_16_INSN_CPBCAST_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpbcast_h_P0S_P1, "CPBCAST_H_P0S_P1", MEPCOP1_16_INSN_CPBCAST_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpbcast_w_P0S_P1, "CPBCAST_W_P0S_P1", MEPCOP1_16_INSN_CPBCAST_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextuu_b_P0S_P1, "CPEXTUU_B_P0S_P1", MEPCOP1_16_INSN_CPEXTUU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextu_b_P0S_P1, "CPEXTU_B_P0S_P1", MEPCOP1_16_INSN_CPEXTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextuu_h_P0S_P1, "CPEXTUU_H_P0S_P1", MEPCOP1_16_INSN_CPEXTUU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextu_h_P0S_P1, "CPEXTU_H_P0S_P1", MEPCOP1_16_INSN_CPEXTU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextlu_b_P0S_P1, "CPEXTLU_B_P0S_P1", MEPCOP1_16_INSN_CPEXTLU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextl_b_P0S_P1, "CPEXTL_B_P0S_P1", MEPCOP1_16_INSN_CPEXTL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextlu_h_P0S_P1, "CPEXTLU_H_P0S_P1", MEPCOP1_16_INSN_CPEXTLU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpextl_h_P0S_P1, "CPEXTL_H_P0S_P1", MEPCOP1_16_INSN_CPEXTL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcastub_h_P0S_P1, "CPCASTUB_H_P0S_P1", MEPCOP1_16_INSN_CPCASTUB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcastb_h_P0S_P1, "CPCASTB_H_P0S_P1", MEPCOP1_16_INSN_CPCASTB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcastub_w_P0S_P1, "CPCASTUB_W_P0S_P1", MEPCOP1_16_INSN_CPCASTUB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcastb_w_P0S_P1, "CPCASTB_W_P0S_P1", MEPCOP1_16_INSN_CPCASTB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcastuh_w_P0S_P1, "CPCASTUH_W_P0S_P1", MEPCOP1_16_INSN_CPCASTUH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcasth_w_P0S_P1, "CPCASTH_W_P0S_P1", MEPCOP1_16_INSN_CPCASTH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cdcastuw_P0S_P1, "CDCASTUW_P0S_P1", MEPCOP1_16_INSN_CDCASTUW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cdcastw_P0S_P1, "CDCASTW_P0S_P1", MEPCOP1_16_INSN_CDCASTW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpmovfrcsar0_P0S_P1, "CPMOVFRCSAR0_P0S_P1", MEPCOP1_16_INSN_CPMOVFRCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpmovfrcsar1_P0S_P1, "CPMOVFRCSAR1_P0S_P1", MEPCOP1_16_INSN_CPMOVFRCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpmovfrcc_P0S_P1, "CPMOVFRCC_P0S_P1", MEPCOP1_16_INSN_CPMOVFRCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpmovtocsar0_P0S_P1, "CPMOVTOCSAR0_P0S_P1", MEPCOP1_16_INSN_CPMOVTOCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpmovtocsar1_P0S_P1, "CPMOVTOCSAR1_P0S_P1", MEPCOP1_16_INSN_CPMOVTOCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpmovtocc_P0S_P1, "CPMOVTOCC_P0S_P1", MEPCOP1_16_INSN_CPMOVTOCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpeqz_b_P0S_P1, "CPCMPEQZ_B_P0S_P1", MEPCOP1_16_INSN_CPCMPEQZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpeq_b_P0S_P1, "CPCMPEQ_B_P0S_P1", MEPCOP1_16_INSN_CPCMPEQ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpeq_h_P0S_P1, "CPCMPEQ_H_P0S_P1", MEPCOP1_16_INSN_CPCMPEQ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpeq_w_P0S_P1, "CPCMPEQ_W_P0S_P1", MEPCOP1_16_INSN_CPCMPEQ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpne_b_P0S_P1, "CPCMPNE_B_P0S_P1", MEPCOP1_16_INSN_CPCMPNE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpne_h_P0S_P1, "CPCMPNE_H_P0S_P1", MEPCOP1_16_INSN_CPCMPNE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpne_w_P0S_P1, "CPCMPNE_W_P0S_P1", MEPCOP1_16_INSN_CPCMPNE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpgtu_b_P0S_P1, "CPCMPGTU_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpgt_b_P0S_P1, "CPCMPGT_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGT_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpgt_h_P0S_P1, "CPCMPGT_H_P0S_P1", MEPCOP1_16_INSN_CPCMPGT_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpgtu_w_P0S_P1, "CPCMPGTU_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGTU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpgt_w_P0S_P1, "CPCMPGT_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGT_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpgeu_b_P0S_P1, "CPCMPGEU_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGEU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpge_b_P0S_P1, "CPCMPGE_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpge_h_P0S_P1, "CPCMPGE_H_P0S_P1", MEPCOP1_16_INSN_CPCMPGE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpgeu_w_P0S_P1, "CPCMPGEU_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGEU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpcmpge_w_P0S_P1, "CPCMPGE_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_16_sem_cpadda0u_b_P0S, "CPADDA0U_B_P0S", MEPCOP1_16_INSN_CPADDA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpadda0_b_P0S, "CPADDA0_B_P0S", MEPCOP1_16_INSN_CPADDA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpaddua0_h_P0S, "CPADDUA0_H_P0S", MEPCOP1_16_INSN_CPADDUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpaddla0_h_P0S, "CPADDLA0_H_P0S", MEPCOP1_16_INSN_CPADDLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpaddaca0u_b_P0S, "CPADDACA0U_B_P0S", MEPCOP1_16_INSN_CPADDACA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpaddaca0_b_P0S, "CPADDACA0_B_P0S", MEPCOP1_16_INSN_CPADDACA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpaddacua0_h_P0S, "CPADDACUA0_H_P0S", MEPCOP1_16_INSN_CPADDACUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpaddacla0_h_P0S, "CPADDACLA0_H_P0S", MEPCOP1_16_INSN_CPADDACLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsuba0u_b_P0S, "CPSUBA0U_B_P0S", MEPCOP1_16_INSN_CPSUBA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsuba0_b_P0S, "CPSUBA0_B_P0S", MEPCOP1_16_INSN_CPSUBA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsubua0_h_P0S, "CPSUBUA0_H_P0S", MEPCOP1_16_INSN_CPSUBUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsubla0_h_P0S, "CPSUBLA0_H_P0S", MEPCOP1_16_INSN_CPSUBLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsubaca0u_b_P0S, "CPSUBACA0U_B_P0S", MEPCOP1_16_INSN_CPSUBACA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsubaca0_b_P0S, "CPSUBACA0_B_P0S", MEPCOP1_16_INSN_CPSUBACA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsubacua0_h_P0S, "CPSUBACUA0_H_P0S", MEPCOP1_16_INSN_CPSUBACUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsubacla0_h_P0S, "CPSUBACLA0_H_P0S", MEPCOP1_16_INSN_CPSUBACLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpabsa0u_b_P0S, "CPABSA0U_B_P0S", MEPCOP1_16_INSN_CPABSA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpabsa0_b_P0S, "CPABSA0_B_P0S", MEPCOP1_16_INSN_CPABSA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpabsua0_h_P0S, "CPABSUA0_H_P0S", MEPCOP1_16_INSN_CPABSUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpabsla0_h_P0S, "CPABSLA0_H_P0S", MEPCOP1_16_INSN_CPABSLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsada0u_b_P0S, "CPSADA0U_B_P0S", MEPCOP1_16_INSN_CPSADA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsada0_b_P0S, "CPSADA0_B_P0S", MEPCOP1_16_INSN_CPSADA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsadua0_h_P0S, "CPSADUA0_H_P0S", MEPCOP1_16_INSN_CPSADUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsadla0_h_P0S, "CPSADLA0_H_P0S", MEPCOP1_16_INSN_CPSADLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpseta0_h_P0S, "CPSETA0_H_P0S", MEPCOP1_16_INSN_CPSETA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsetua0_w_P0S, "CPSETUA0_W_P0S", MEPCOP1_16_INSN_CPSETUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsetla0_w_P0S, "CPSETLA0_W_P0S", MEPCOP1_16_INSN_CPSETLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmova0_b_P0S, "CPMOVA0_B_P0S", MEPCOP1_16_INSN_CPMOVA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovua0_h_P0S, "CPMOVUA0_H_P0S", MEPCOP1_16_INSN_CPMOVUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovla0_h_P0S, "CPMOVLA0_H_P0S", MEPCOP1_16_INSN_CPMOVLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovuua0_w_P0S, "CPMOVUUA0_W_P0S", MEPCOP1_16_INSN_CPMOVUUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovula0_w_P0S, "CPMOVULA0_W_P0S", MEPCOP1_16_INSN_CPMOVULA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovlua0_w_P0S, "CPMOVLUA0_W_P0S", MEPCOP1_16_INSN_CPMOVLUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovlla0_w_P0S, "CPMOVLLA0_W_P0S", MEPCOP1_16_INSN_CPMOVLLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cppacka0u_b_P0S, "CPPACKA0U_B_P0S", MEPCOP1_16_INSN_CPPACKA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cppacka0_b_P0S, "CPPACKA0_B_P0S", MEPCOP1_16_INSN_CPPACKA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cppackua0_h_P0S, "CPPACKUA0_H_P0S", MEPCOP1_16_INSN_CPPACKUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cppackla0_h_P0S, "CPPACKLA0_H_P0S", MEPCOP1_16_INSN_CPPACKLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cppackua0_w_P0S, "CPPACKUA0_W_P0S", MEPCOP1_16_INSN_CPPACKUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cppackla0_w_P0S, "CPPACKLA0_W_P0S", MEPCOP1_16_INSN_CPPACKLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovhua0_w_P0S, "CPMOVHUA0_W_P0S", MEPCOP1_16_INSN_CPMOVHUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovhla0_w_P0S, "CPMOVHLA0_W_P0S", MEPCOP1_16_INSN_CPMOVHLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpacsuma0_P0S, "CPACSUMA0_P0S", MEPCOP1_16_INSN_CPACSUMA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpaccpa0_P0S, "CPACCPA0_P0S", MEPCOP1_16_INSN_CPACCPA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsrla0_P0S, "CPSRLA0_P0S", MEPCOP1_16_INSN_CPSRLA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsraa0_P0S, "CPSRAA0_P0S", MEPCOP1_16_INSN_CPSRAA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpslla0_P0S, "CPSLLA0_P0S", MEPCOP1_16_INSN_CPSLLA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsrlia0_P0S, "CPSRLIA0_P0S", MEPCOP1_16_INSN_CPSRLIA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsraia0_P0S, "CPSRAIA0_P0S", MEPCOP1_16_INSN_CPSRAIA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpsllia0_P0S, "CPSLLIA0_P0S", MEPCOP1_16_INSN_CPSLLIA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftba0s0u_b_P0S, "CPFSFTBA0S0U_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftba0s0_b_P0S, "CPFSFTBA0S0_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftbua0s0_h_P0S, "CPFSFTBUA0S0_H_P0S", MEPCOP1_16_INSN_CPFSFTBUA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftbla0s0_h_P0S, "CPFSFTBLA0S0_H_P0S", MEPCOP1_16_INSN_CPFSFTBLA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfaca0s0u_b_P0S, "CPFACA0S0U_B_P0S", MEPCOP1_16_INSN_CPFACA0S0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfaca0s0_b_P0S, "CPFACA0S0_B_P0S", MEPCOP1_16_INSN_CPFACA0S0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfacua0s0_h_P0S, "CPFACUA0S0_H_P0S", MEPCOP1_16_INSN_CPFACUA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfacla0s0_h_P0S, "CPFACLA0S0_H_P0S", MEPCOP1_16_INSN_CPFACLA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftba0s1u_b_P0S, "CPFSFTBA0S1U_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S1U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftba0s1_b_P0S, "CPFSFTBA0S1_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S1_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftbua0s1_h_P0S, "CPFSFTBUA0S1_H_P0S", MEPCOP1_16_INSN_CPFSFTBUA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfsftbla0s1_h_P0S, "CPFSFTBLA0S1_H_P0S", MEPCOP1_16_INSN_CPFSFTBLA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfaca0s1u_b_P0S, "CPFACA0S1U_B_P0S", MEPCOP1_16_INSN_CPFACA0S1U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfaca0s1_b_P0S, "CPFACA0S1_B_P0S", MEPCOP1_16_INSN_CPFACA0S1_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfacua0s1_h_P0S, "CPFACUA0S1_H_P0S", MEPCOP1_16_INSN_CPFACUA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpfacla0s1_h_P0S, "CPFACLA0S1_H_P0S", MEPCOP1_16_INSN_CPFACLA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
- { mepcop1_16_sem_cpmovi_b_P0S_P1, "CPMOVI_B_P0S_P1", MEPCOP1_16_INSN_CPMOVI_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_x_invalid, "X_INVALID", MEPCOP1_16_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcop1_16_sem_c0nop_P0_P0S, "C0NOP_P0_P0S", MEPCOP1_16_INSN_C0NOP_P0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x28" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpadd3_b_P0S_P1, "CPADD3_B_P0S_P1", MEPCOP1_16_INSN_CPADD3_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpadd3_h_P0S_P1, "CPADD3_H_P0S_P1", MEPCOP1_16_INSN_CPADD3_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpadd3_w_P0S_P1, "CPADD3_W_P0S_P1", MEPCOP1_16_INSN_CPADD3_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpunpacku_b_P0S_P1, "CPUNPACKU_B_P0S_P1", MEPCOP1_16_INSN_CPUNPACKU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpunpacku_h_P0S_P1, "CPUNPACKU_H_P0S_P1", MEPCOP1_16_INSN_CPUNPACKU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpunpacku_w_P0S_P1, "CPUNPACKU_W_P0S_P1", MEPCOP1_16_INSN_CPUNPACKU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpunpackl_b_P0S_P1, "CPUNPACKL_B_P0S_P1", MEPCOP1_16_INSN_CPUNPACKL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpunpackl_h_P0S_P1, "CPUNPACKL_H_P0S_P1", MEPCOP1_16_INSN_CPUNPACKL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpunpackl_w_P0S_P1, "CPUNPACKL_W_P0S_P1", MEPCOP1_16_INSN_CPUNPACKL_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpsel_P0S_P1, "CPSEL_P0S_P1", MEPCOP1_16_INSN_CPSEL_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpfsftbs0_P0S_P1, "CPFSFTBS0_P0S_P1", MEPCOP1_16_INSN_CPFSFTBS0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpfsftbs1_P0S_P1, "CPFSFTBS1_P0S_P1", MEPCOP1_16_INSN_CPFSFTBS1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpmov_P0S_P1, "CPMOV_P0S_P1", MEPCOP1_16_INSN_CPMOV_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpabsz_b_P0S_P1, "CPABSZ_B_P0S_P1", MEPCOP1_16_INSN_CPABSZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpabsz_h_P0S_P1, "CPABSZ_H_P0S_P1", MEPCOP1_16_INSN_CPABSZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpabsz_w_P0S_P1, "CPABSZ_W_P0S_P1", MEPCOP1_16_INSN_CPABSZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpldz_h_P0S_P1, "CPLDZ_H_P0S_P1", MEPCOP1_16_INSN_CPLDZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpldz_w_P0S_P1, "CPLDZ_W_P0S_P1", MEPCOP1_16_INSN_CPLDZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpnorm_h_P0S_P1, "CPNORM_H_P0S_P1", MEPCOP1_16_INSN_CPNORM_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpnorm_w_P0S_P1, "CPNORM_W_P0S_P1", MEPCOP1_16_INSN_CPNORM_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cphaddu_b_P0S_P1, "CPHADDU_B_P0S_P1", MEPCOP1_16_INSN_CPHADDU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cphadd_b_P0S_P1, "CPHADD_B_P0S_P1", MEPCOP1_16_INSN_CPHADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cphadd_h_P0S_P1, "CPHADD_H_P0S_P1", MEPCOP1_16_INSN_CPHADD_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cphadd_w_P0S_P1, "CPHADD_W_P0S_P1", MEPCOP1_16_INSN_CPHADD_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpccadd_b_P0S_P1, "CPCCADD_B_P0S_P1", MEPCOP1_16_INSN_CPCCADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRSTCOPY, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpbcast_b_P0S_P1, "CPBCAST_B_P0S_P1", MEPCOP1_16_INSN_CPBCAST_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpbcast_h_P0S_P1, "CPBCAST_H_P0S_P1", MEPCOP1_16_INSN_CPBCAST_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpbcast_w_P0S_P1, "CPBCAST_W_P0S_P1", MEPCOP1_16_INSN_CPBCAST_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextuu_b_P0S_P1, "CPEXTUU_B_P0S_P1", MEPCOP1_16_INSN_CPEXTUU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextu_b_P0S_P1, "CPEXTU_B_P0S_P1", MEPCOP1_16_INSN_CPEXTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextuu_h_P0S_P1, "CPEXTUU_H_P0S_P1", MEPCOP1_16_INSN_CPEXTUU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextu_h_P0S_P1, "CPEXTU_H_P0S_P1", MEPCOP1_16_INSN_CPEXTU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextlu_b_P0S_P1, "CPEXTLU_B_P0S_P1", MEPCOP1_16_INSN_CPEXTLU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextl_b_P0S_P1, "CPEXTL_B_P0S_P1", MEPCOP1_16_INSN_CPEXTL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextlu_h_P0S_P1, "CPEXTLU_H_P0S_P1", MEPCOP1_16_INSN_CPEXTLU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpextl_h_P0S_P1, "CPEXTL_H_P0S_P1", MEPCOP1_16_INSN_CPEXTL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcastub_h_P0S_P1, "CPCASTUB_H_P0S_P1", MEPCOP1_16_INSN_CPCASTUB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcastb_h_P0S_P1, "CPCASTB_H_P0S_P1", MEPCOP1_16_INSN_CPCASTB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcastub_w_P0S_P1, "CPCASTUB_W_P0S_P1", MEPCOP1_16_INSN_CPCASTUB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcastb_w_P0S_P1, "CPCASTB_W_P0S_P1", MEPCOP1_16_INSN_CPCASTB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcastuh_w_P0S_P1, "CPCASTUH_W_P0S_P1", MEPCOP1_16_INSN_CPCASTUH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcasth_w_P0S_P1, "CPCASTH_W_P0S_P1", MEPCOP1_16_INSN_CPCASTH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cdcastuw_P0S_P1, "CDCASTUW_P0S_P1", MEPCOP1_16_INSN_CDCASTUW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cdcastw_P0S_P1, "CDCASTW_P0S_P1", MEPCOP1_16_INSN_CDCASTW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpmovfrcsar0_P0S_P1, "CPMOVFRCSAR0_P0S_P1", MEPCOP1_16_INSN_CPMOVFRCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpmovfrcsar1_P0S_P1, "CPMOVFRCSAR1_P0S_P1", MEPCOP1_16_INSN_CPMOVFRCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpmovfrcc_P0S_P1, "CPMOVFRCC_P0S_P1", MEPCOP1_16_INSN_CPMOVFRCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpmovtocsar0_P0S_P1, "CPMOVTOCSAR0_P0S_P1", MEPCOP1_16_INSN_CPMOVTOCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpmovtocsar1_P0S_P1, "CPMOVTOCSAR1_P0S_P1", MEPCOP1_16_INSN_CPMOVTOCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpmovtocc_P0S_P1, "CPMOVTOCC_P0S_P1", MEPCOP1_16_INSN_CPMOVTOCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpeqz_b_P0S_P1, "CPCMPEQZ_B_P0S_P1", MEPCOP1_16_INSN_CPCMPEQZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpeq_b_P0S_P1, "CPCMPEQ_B_P0S_P1", MEPCOP1_16_INSN_CPCMPEQ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpeq_h_P0S_P1, "CPCMPEQ_H_P0S_P1", MEPCOP1_16_INSN_CPCMPEQ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpeq_w_P0S_P1, "CPCMPEQ_W_P0S_P1", MEPCOP1_16_INSN_CPCMPEQ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpne_b_P0S_P1, "CPCMPNE_B_P0S_P1", MEPCOP1_16_INSN_CPCMPNE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpne_h_P0S_P1, "CPCMPNE_H_P0S_P1", MEPCOP1_16_INSN_CPCMPNE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpne_w_P0S_P1, "CPCMPNE_W_P0S_P1", MEPCOP1_16_INSN_CPCMPNE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpgtu_b_P0S_P1, "CPCMPGTU_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpgt_b_P0S_P1, "CPCMPGT_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGT_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpgt_h_P0S_P1, "CPCMPGT_H_P0S_P1", MEPCOP1_16_INSN_CPCMPGT_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpgtu_w_P0S_P1, "CPCMPGTU_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGTU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpgt_w_P0S_P1, "CPCMPGT_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGT_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpgeu_b_P0S_P1, "CPCMPGEU_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGEU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpge_b_P0S_P1, "CPCMPGE_B_P0S_P1", MEPCOP1_16_INSN_CPCMPGE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpge_h_P0S_P1, "CPCMPGE_H_P0S_P1", MEPCOP1_16_INSN_CPCMPGE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpgeu_w_P0S_P1, "CPCMPGEU_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGEU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpcmpge_w_P0S_P1, "CPCMPGE_W_P0S_P1", MEPCOP1_16_INSN_CPCMPGE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_16_sem_cpadda0u_b_P0S, "CPADDA0U_B_P0S", MEPCOP1_16_INSN_CPADDA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpadda0_b_P0S, "CPADDA0_B_P0S", MEPCOP1_16_INSN_CPADDA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpaddua0_h_P0S, "CPADDUA0_H_P0S", MEPCOP1_16_INSN_CPADDUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpaddla0_h_P0S, "CPADDLA0_H_P0S", MEPCOP1_16_INSN_CPADDLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpaddaca0u_b_P0S, "CPADDACA0U_B_P0S", MEPCOP1_16_INSN_CPADDACA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpaddaca0_b_P0S, "CPADDACA0_B_P0S", MEPCOP1_16_INSN_CPADDACA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpaddacua0_h_P0S, "CPADDACUA0_H_P0S", MEPCOP1_16_INSN_CPADDACUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpaddacla0_h_P0S, "CPADDACLA0_H_P0S", MEPCOP1_16_INSN_CPADDACLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsuba0u_b_P0S, "CPSUBA0U_B_P0S", MEPCOP1_16_INSN_CPSUBA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsuba0_b_P0S, "CPSUBA0_B_P0S", MEPCOP1_16_INSN_CPSUBA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsubua0_h_P0S, "CPSUBUA0_H_P0S", MEPCOP1_16_INSN_CPSUBUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsubla0_h_P0S, "CPSUBLA0_H_P0S", MEPCOP1_16_INSN_CPSUBLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsubaca0u_b_P0S, "CPSUBACA0U_B_P0S", MEPCOP1_16_INSN_CPSUBACA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsubaca0_b_P0S, "CPSUBACA0_B_P0S", MEPCOP1_16_INSN_CPSUBACA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsubacua0_h_P0S, "CPSUBACUA0_H_P0S", MEPCOP1_16_INSN_CPSUBACUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsubacla0_h_P0S, "CPSUBACLA0_H_P0S", MEPCOP1_16_INSN_CPSUBACLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpabsa0u_b_P0S, "CPABSA0U_B_P0S", MEPCOP1_16_INSN_CPABSA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpabsa0_b_P0S, "CPABSA0_B_P0S", MEPCOP1_16_INSN_CPABSA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpabsua0_h_P0S, "CPABSUA0_H_P0S", MEPCOP1_16_INSN_CPABSUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpabsla0_h_P0S, "CPABSLA0_H_P0S", MEPCOP1_16_INSN_CPABSLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsada0u_b_P0S, "CPSADA0U_B_P0S", MEPCOP1_16_INSN_CPSADA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsada0_b_P0S, "CPSADA0_B_P0S", MEPCOP1_16_INSN_CPSADA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsadua0_h_P0S, "CPSADUA0_H_P0S", MEPCOP1_16_INSN_CPSADUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsadla0_h_P0S, "CPSADLA0_H_P0S", MEPCOP1_16_INSN_CPSADLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpseta0_h_P0S, "CPSETA0_H_P0S", MEPCOP1_16_INSN_CPSETA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsetua0_w_P0S, "CPSETUA0_W_P0S", MEPCOP1_16_INSN_CPSETUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsetla0_w_P0S, "CPSETLA0_W_P0S", MEPCOP1_16_INSN_CPSETLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmova0_b_P0S, "CPMOVA0_B_P0S", MEPCOP1_16_INSN_CPMOVA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovua0_h_P0S, "CPMOVUA0_H_P0S", MEPCOP1_16_INSN_CPMOVUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovla0_h_P0S, "CPMOVLA0_H_P0S", MEPCOP1_16_INSN_CPMOVLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovuua0_w_P0S, "CPMOVUUA0_W_P0S", MEPCOP1_16_INSN_CPMOVUUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovula0_w_P0S, "CPMOVULA0_W_P0S", MEPCOP1_16_INSN_CPMOVULA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovlua0_w_P0S, "CPMOVLUA0_W_P0S", MEPCOP1_16_INSN_CPMOVLUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovlla0_w_P0S, "CPMOVLLA0_W_P0S", MEPCOP1_16_INSN_CPMOVLLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cppacka0u_b_P0S, "CPPACKA0U_B_P0S", MEPCOP1_16_INSN_CPPACKA0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cppacka0_b_P0S, "CPPACKA0_B_P0S", MEPCOP1_16_INSN_CPPACKA0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cppackua0_h_P0S, "CPPACKUA0_H_P0S", MEPCOP1_16_INSN_CPPACKUA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cppackla0_h_P0S, "CPPACKLA0_H_P0S", MEPCOP1_16_INSN_CPPACKLA0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cppackua0_w_P0S, "CPPACKUA0_W_P0S", MEPCOP1_16_INSN_CPPACKUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cppackla0_w_P0S, "CPPACKLA0_W_P0S", MEPCOP1_16_INSN_CPPACKLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovhua0_w_P0S, "CPMOVHUA0_W_P0S", MEPCOP1_16_INSN_CPMOVHUA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovhla0_w_P0S, "CPMOVHLA0_W_P0S", MEPCOP1_16_INSN_CPMOVHLA0_W_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpacsuma0_P0S, "CPACSUMA0_P0S", MEPCOP1_16_INSN_CPACSUMA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpaccpa0_P0S, "CPACCPA0_P0S", MEPCOP1_16_INSN_CPACCPA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsrla0_P0S, "CPSRLA0_P0S", MEPCOP1_16_INSN_CPSRLA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsraa0_P0S, "CPSRAA0_P0S", MEPCOP1_16_INSN_CPSRAA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpslla0_P0S, "CPSLLA0_P0S", MEPCOP1_16_INSN_CPSLLA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsrlia0_P0S, "CPSRLIA0_P0S", MEPCOP1_16_INSN_CPSRLIA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsraia0_P0S, "CPSRAIA0_P0S", MEPCOP1_16_INSN_CPSRAIA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpsllia0_P0S, "CPSLLIA0_P0S", MEPCOP1_16_INSN_CPSLLIA0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftba0s0u_b_P0S, "CPFSFTBA0S0U_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftba0s0_b_P0S, "CPFSFTBA0S0_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftbua0s0_h_P0S, "CPFSFTBUA0S0_H_P0S", MEPCOP1_16_INSN_CPFSFTBUA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftbla0s0_h_P0S, "CPFSFTBLA0S0_H_P0S", MEPCOP1_16_INSN_CPFSFTBLA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfaca0s0u_b_P0S, "CPFACA0S0U_B_P0S", MEPCOP1_16_INSN_CPFACA0S0U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfaca0s0_b_P0S, "CPFACA0S0_B_P0S", MEPCOP1_16_INSN_CPFACA0S0_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfacua0s0_h_P0S, "CPFACUA0S0_H_P0S", MEPCOP1_16_INSN_CPFACUA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfacla0s0_h_P0S, "CPFACLA0S0_H_P0S", MEPCOP1_16_INSN_CPFACLA0S0_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftba0s1u_b_P0S, "CPFSFTBA0S1U_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S1U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftba0s1_b_P0S, "CPFSFTBA0S1_B_P0S", MEPCOP1_16_INSN_CPFSFTBA0S1_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftbua0s1_h_P0S, "CPFSFTBUA0S1_H_P0S", MEPCOP1_16_INSN_CPFSFTBUA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfsftbla0s1_h_P0S, "CPFSFTBLA0S1_H_P0S", MEPCOP1_16_INSN_CPFSFTBLA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfaca0s1u_b_P0S, "CPFACA0S1U_B_P0S", MEPCOP1_16_INSN_CPFACA0S1U_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfaca0s1_b_P0S, "CPFACA0S1_B_P0S", MEPCOP1_16_INSN_CPFACA0S1_B_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfacua0s1_h_P0S, "CPFACUA0S1_H_P0S", MEPCOP1_16_INSN_CPFACUA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpfacla0s1_h_P0S, "CPFACLA0S1_H_P0S", MEPCOP1_16_INSN_CPFACLA0S1_H_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x20" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S) } },
+ { mepcop1_16_sem_cpmovi_b_P0S_P1, "CPMOVI_B_P0S_P1", MEPCOP1_16_INSN_CPMOVI_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
};
@@ -194,6 +194,24 @@ mepcop1_16_extract_sfmt_cpmovtocsar0_P0S
static void
mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
static void
+mepcop1_16_extract_sfmt_cpadda0u_b_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpaddua0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpaddla0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpaddacua0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpaddacla0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpacsuma0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpaccpa0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
+mepcop1_16_extract_sfmt_cpsrla0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
+static void
mepcop1_16_extract_sfmt_cpsrlia0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
static void
mepcop1_16_extract_sfmt_cpmovi_b_P0S_P1 (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn);
@@ -1536,137 +1554,137 @@ mepcop1_16_scache::decode (mep_ext1_cpu*
case 1536 : /* fall through */
case 1568 :
if ((entire_insn & 0xfff801ff) == 0xc00000)
- { itype = MEPCOP1_16_INSN_CPADDA0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDA0U_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1537 : /* fall through */
case 1569 :
if ((entire_insn & 0xfff801ff) == 0xc00010)
- { itype = MEPCOP1_16_INSN_CPADDA0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDA0_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1538 : /* fall through */
case 1570 :
if ((entire_insn & 0xfff801ff) == 0xc00020)
- { itype = MEPCOP1_16_INSN_CPADDUA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDUA0_H_P0S; mepcop1_16_extract_sfmt_cpaddua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1539 : /* fall through */
case 1571 :
if ((entire_insn & 0xfff801ff) == 0xc00030)
- { itype = MEPCOP1_16_INSN_CPADDLA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDLA0_H_P0S; mepcop1_16_extract_sfmt_cpaddla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1540 : /* fall through */
case 1572 :
if ((entire_insn & 0xfff801ff) == 0xc00040)
- { itype = MEPCOP1_16_INSN_CPADDACA0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDACA0U_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1541 : /* fall through */
case 1573 :
if ((entire_insn & 0xfff801ff) == 0xc00050)
- { itype = MEPCOP1_16_INSN_CPADDACA0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDACA0_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1542 : /* fall through */
case 1574 :
if ((entire_insn & 0xfff801ff) == 0xc00060)
- { itype = MEPCOP1_16_INSN_CPADDACUA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDACUA0_H_P0S; mepcop1_16_extract_sfmt_cpaddacua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1543 : /* fall through */
case 1575 :
if ((entire_insn & 0xfff801ff) == 0xc00070)
- { itype = MEPCOP1_16_INSN_CPADDACLA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPADDACLA0_H_P0S; mepcop1_16_extract_sfmt_cpaddacla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1544 : /* fall through */
case 1576 :
if ((entire_insn & 0xfff801ff) == 0xc00080)
- { itype = MEPCOP1_16_INSN_CPSUBA0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBA0U_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1545 : /* fall through */
case 1577 :
if ((entire_insn & 0xfff801ff) == 0xc00090)
- { itype = MEPCOP1_16_INSN_CPSUBA0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBA0_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1546 : /* fall through */
case 1578 :
if ((entire_insn & 0xfff801ff) == 0xc000a0)
- { itype = MEPCOP1_16_INSN_CPSUBUA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBUA0_H_P0S; mepcop1_16_extract_sfmt_cpaddua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1547 : /* fall through */
case 1579 :
if ((entire_insn & 0xfff801ff) == 0xc000b0)
- { itype = MEPCOP1_16_INSN_CPSUBLA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBLA0_H_P0S; mepcop1_16_extract_sfmt_cpaddla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1548 : /* fall through */
case 1580 :
if ((entire_insn & 0xfff801ff) == 0xc000c0)
- { itype = MEPCOP1_16_INSN_CPSUBACA0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBACA0U_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1549 : /* fall through */
case 1581 :
if ((entire_insn & 0xfff801ff) == 0xc000d0)
- { itype = MEPCOP1_16_INSN_CPSUBACA0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBACA0_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1550 : /* fall through */
case 1582 :
if ((entire_insn & 0xfff801ff) == 0xc000e0)
- { itype = MEPCOP1_16_INSN_CPSUBACUA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBACUA0_H_P0S; mepcop1_16_extract_sfmt_cpaddacua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1551 : /* fall through */
case 1583 :
if ((entire_insn & 0xfff801ff) == 0xc000f0)
- { itype = MEPCOP1_16_INSN_CPSUBACLA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSUBACLA0_H_P0S; mepcop1_16_extract_sfmt_cpaddacla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1552 : /* fall through */
case 1584 :
if ((entire_insn & 0xfff801ff) == 0xc00100)
- { itype = MEPCOP1_16_INSN_CPABSA0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPABSA0U_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1553 : /* fall through */
case 1585 :
if ((entire_insn & 0xfff801ff) == 0xc00110)
- { itype = MEPCOP1_16_INSN_CPABSA0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPABSA0_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1554 : /* fall through */
case 1586 :
if ((entire_insn & 0xfff801ff) == 0xc00120)
- { itype = MEPCOP1_16_INSN_CPABSUA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPABSUA0_H_P0S; mepcop1_16_extract_sfmt_cpaddua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1555 : /* fall through */
case 1587 :
if ((entire_insn & 0xfff801ff) == 0xc00130)
- { itype = MEPCOP1_16_INSN_CPABSLA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPABSLA0_H_P0S; mepcop1_16_extract_sfmt_cpaddla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1556 : /* fall through */
case 1588 :
if ((entire_insn & 0xfff801ff) == 0xc00140)
- { itype = MEPCOP1_16_INSN_CPSADA0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSADA0U_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1557 : /* fall through */
case 1589 :
if ((entire_insn & 0xfff801ff) == 0xc00150)
- { itype = MEPCOP1_16_INSN_CPSADA0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSADA0_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1558 : /* fall through */
case 1590 :
if ((entire_insn & 0xfff801ff) == 0xc00160)
- { itype = MEPCOP1_16_INSN_CPSADUA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSADUA0_H_P0S; mepcop1_16_extract_sfmt_cpaddacua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1559 : /* fall through */
case 1591 :
if ((entire_insn & 0xfff801ff) == 0xc00170)
- { itype = MEPCOP1_16_INSN_CPSADLA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSADLA0_H_P0S; mepcop1_16_extract_sfmt_cpaddacla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1563 : /* fall through */
case 1595 :
if ((entire_insn & 0xfff801ff) == 0xc001b0)
- { itype = MEPCOP1_16_INSN_CPSETA0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSETA0_H_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1564 : /* fall through */
case 1596 :
if ((entire_insn & 0xfff801ff) == 0xc001c0)
- { itype = MEPCOP1_16_INSN_CPSETUA0_W_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSETUA0_W_P0S; mepcop1_16_extract_sfmt_cpaddua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1565 : /* fall through */
case 1597 :
if ((entire_insn & 0xfff801ff) == 0xc001d0)
- { itype = MEPCOP1_16_INSN_CPSETLA0_W_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSETLA0_W_P0S; mepcop1_16_extract_sfmt_cpaddla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1600 :
{
@@ -1703,11 +1721,11 @@ mepcop1_16_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
if ((entire_insn & 0xffffffff) == 0xc82000)
- { itype = MEPCOP1_16_INSN_CPACSUMA0_P0S; mepcop1_16_extract_sfmt_c0nop_P0_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPACSUMA0_P0S; mepcop1_16_extract_sfmt_cpacsuma0_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 9 :
if ((entire_insn & 0xffffffff) == 0xc82200)
- { itype = MEPCOP1_16_INSN_CPACCPA0_P0S; mepcop1_16_extract_sfmt_c0nop_P0_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPACCPA0_P0S; mepcop1_16_extract_sfmt_cpaccpa0_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1817,15 +1835,15 @@ mepcop1_16_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
if ((entire_insn & 0xfff83fff) == 0xc83000)
- { itype = MEPCOP1_16_INSN_CPSRLA0_P0S; mepcop1_16_extract_sfmt_cpmovtocsar0_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSRLA0_P0S; mepcop1_16_extract_sfmt_cpsrla0_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 9 :
if ((entire_insn & 0xfff83fff) == 0xc83200)
- { itype = MEPCOP1_16_INSN_CPSRAA0_P0S; mepcop1_16_extract_sfmt_cpmovtocsar0_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSRAA0_P0S; mepcop1_16_extract_sfmt_cpsrla0_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 10 :
if ((entire_insn & 0xfff83fff) == 0xc83400)
- { itype = MEPCOP1_16_INSN_CPSLLA0_P0S; mepcop1_16_extract_sfmt_cpmovtocsar0_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPSLLA0_P0S; mepcop1_16_extract_sfmt_cpsrla0_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
if ((entire_insn & 0xfffffe0f) == 0xc83800)
@@ -1927,82 +1945,82 @@ mepcop1_16_scache::decode (mep_ext1_cpu*
case 1984 : /* fall through */
case 2016 :
if ((entire_insn & 0xfff801ff) == 0xf80000)
- { itype = MEPCOP1_16_INSN_CPFSFTBA0S0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBA0S0U_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1985 : /* fall through */
case 2017 :
if ((entire_insn & 0xfff801ff) == 0xf80010)
- { itype = MEPCOP1_16_INSN_CPFSFTBA0S0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBA0S0_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1986 : /* fall through */
case 2018 :
if ((entire_insn & 0xfff801ff) == 0xf80020)
- { itype = MEPCOP1_16_INSN_CPFSFTBUA0S0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBUA0S0_H_P0S; mepcop1_16_extract_sfmt_cpaddua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1987 : /* fall through */
case 2019 :
if ((entire_insn & 0xfff801ff) == 0xf80030)
- { itype = MEPCOP1_16_INSN_CPFSFTBLA0S0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBLA0S0_H_P0S; mepcop1_16_extract_sfmt_cpaddla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1988 : /* fall through */
case 2020 :
if ((entire_insn & 0xfff801ff) == 0xf80040)
- { itype = MEPCOP1_16_INSN_CPFACA0S0U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACA0S0U_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1989 : /* fall through */
case 2021 :
if ((entire_insn & 0xfff801ff) == 0xf80050)
- { itype = MEPCOP1_16_INSN_CPFACA0S0_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACA0S0_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1990 : /* fall through */
case 2022 :
if ((entire_insn & 0xfff801ff) == 0xf80060)
- { itype = MEPCOP1_16_INSN_CPFACUA0S0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACUA0S0_H_P0S; mepcop1_16_extract_sfmt_cpaddacua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1991 : /* fall through */
case 2023 :
if ((entire_insn & 0xfff801ff) == 0xf80070)
- { itype = MEPCOP1_16_INSN_CPFACLA0S0_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACLA0S0_H_P0S; mepcop1_16_extract_sfmt_cpaddacla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1992 : /* fall through */
case 2024 :
if ((entire_insn & 0xfff801ff) == 0xf80080)
- { itype = MEPCOP1_16_INSN_CPFSFTBA0S1U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBA0S1U_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1993 : /* fall through */
case 2025 :
if ((entire_insn & 0xfff801ff) == 0xf80090)
- { itype = MEPCOP1_16_INSN_CPFSFTBA0S1_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBA0S1_B_P0S; mepcop1_16_extract_sfmt_cpadda0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1994 : /* fall through */
case 2026 :
if ((entire_insn & 0xfff801ff) == 0xf800a0)
- { itype = MEPCOP1_16_INSN_CPFSFTBUA0S1_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBUA0S1_H_P0S; mepcop1_16_extract_sfmt_cpaddua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1995 : /* fall through */
case 2027 :
if ((entire_insn & 0xfff801ff) == 0xf800b0)
- { itype = MEPCOP1_16_INSN_CPFSFTBLA0S1_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFSFTBLA0S1_H_P0S; mepcop1_16_extract_sfmt_cpaddla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1996 : /* fall through */
case 2028 :
if ((entire_insn & 0xfff801ff) == 0xf800c0)
- { itype = MEPCOP1_16_INSN_CPFACA0S1U_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACA0S1U_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1997 : /* fall through */
case 2029 :
if ((entire_insn & 0xfff801ff) == 0xf800d0)
- { itype = MEPCOP1_16_INSN_CPFACA0S1_B_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACA0S1_B_P0S; mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1998 : /* fall through */
case 2030 :
if ((entire_insn & 0xfff801ff) == 0xf800e0)
- { itype = MEPCOP1_16_INSN_CPFACUA0S1_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACUA0S1_H_P0S; mepcop1_16_extract_sfmt_cpaddacua0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1999 : /* fall through */
case 2031 :
if ((entire_insn & 0xfff801ff) == 0xf800f0)
- { itype = MEPCOP1_16_INSN_CPFACLA0S1_H_P0S; mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_16_INSN_CPFACLA0S1_H_P0S; mepcop1_16_extract_sfmt_cpaddacla0_h_P0S (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_16_INSN_X_INVALID; mepcop1_16_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2225,6 +2243,247 @@ mepcop1_16_extract_sfmt_cpcmpeqz_b_P0S_P
}
void
+mepcop1_16_extract_sfmt_cpadda0u_b_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpadda0u_b_P0S)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpaddua0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddua0_h_P0S)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpaddla0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddla0_h_P0S)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpaddaca0u_b_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddaca0u_b_P0S)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpaddacua0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddacua0_h_P0S)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpaddacla0_h_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddacla0_h_P0S)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpacsuma0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpacsuma0_P0S)\t"
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpaccpa0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaccpa0_P0S)\t"
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_16_extract_sfmt_cpsrla0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
+ mepcop1_16_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpmovi_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpsrla0_P0S)\t"
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
mepcop1_16_extract_sfmt_cpsrlia0_P0S (mepcop1_16_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_16_insn_word base_insn, mepcop1_16_insn_word entire_insn){
mepcop1_16_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
Index: sid/component/cgen-cpu/mep/mep-cop1-16-sem.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-16-sem.cxx,v
retrieving revision 1.2
diff -p -U3 -r1.2 mep-cop1-16-sem.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-16-sem.cxx 22 May 2009 17:37:43 -0000 1.2
+++ sid/component/cgen-cpu/mep/mep-cop1-16-sem.cxx 24 Jun 2009 02:59:29 -0000
@@ -726,7 +726,12 @@ mepcop1_16_sem_cpccadd_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpccadd_b (pc, FLD (f_ivc2_5u13));
+ {
+ DI opval = current_cpu->ivc2_cpccadd_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u13) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr64_set (FLD (f_ivc2_5u13), opval);
+ }
}
current_cpu->done_insn (npc, status);
@@ -1408,6 +1413,12 @@ mepcop1_16_sem_cpcmpeqz_b_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeqz_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1430,6 +1441,12 @@ mepcop1_16_sem_cpcmpeq_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1452,6 +1469,12 @@ mepcop1_16_sem_cpcmpeq_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1474,6 +1497,12 @@ mepcop1_16_sem_cpcmpeq_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1496,6 +1525,12 @@ mepcop1_16_sem_cpcmpne_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1518,6 +1553,12 @@ mepcop1_16_sem_cpcmpne_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1540,6 +1581,12 @@ mepcop1_16_sem_cpcmpne_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1562,6 +1609,12 @@ mepcop1_16_sem_cpcmpgtu_b_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgtu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1584,6 +1637,12 @@ mepcop1_16_sem_cpcmpgt_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1606,6 +1665,12 @@ mepcop1_16_sem_cpcmpgt_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1628,6 +1693,12 @@ mepcop1_16_sem_cpcmpgtu_w_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgtu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1650,6 +1721,12 @@ mepcop1_16_sem_cpcmpgt_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1672,6 +1749,12 @@ mepcop1_16_sem_cpcmpgeu_b_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgeu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1694,6 +1777,12 @@ mepcop1_16_sem_cpcmpge_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1716,6 +1805,12 @@ mepcop1_16_sem_cpcmpge_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1738,6 +1833,12 @@ mepcop1_16_sem_cpcmpgeu_w_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgeu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1760,6 +1861,12 @@ mepcop1_16_sem_cpcmpge_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1782,6 +1889,54 @@ mepcop1_16_sem_cpadda0u_b_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpadda0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1804,6 +1959,54 @@ mepcop1_16_sem_cpadda0_b_P0S (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpadda0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1826,6 +2029,30 @@ mepcop1_16_sem_cpaddua0_h_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpaddua0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1848,6 +2075,30 @@ mepcop1_16_sem_cpaddla0_h_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
current_cpu->ivc2_cpaddla0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1870,6 +2121,60 @@ mepcop1_16_sem_cpaddaca0u_b_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpaddaca0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1892,6 +2197,60 @@ mepcop1_16_sem_cpaddaca0_b_P0S (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpaddaca0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1914,6 +2273,36 @@ mepcop1_16_sem_cpaddacua0_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpaddacua0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1936,6 +2325,36 @@ mepcop1_16_sem_cpaddacla0_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpaddacla0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1958,6 +2377,54 @@ mepcop1_16_sem_cpsuba0u_b_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsuba0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1980,28 +2447,100 @@ mepcop1_16_sem_cpsuba0_b_P0S (mep_ext1_c
{
current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpsuba0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
-}
-
- current_cpu->done_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** cpsubua0_h_P0S: cpsubua0.h $crqp,$crpp
-
-sem_status
-mepcop1_16_sem_cpsubua0_h_P0S (mep_ext1_cpu* current_cpu, mepcop1_16_scache* sem)
-{
-#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
- sem_status status = SEM_STATUS_NORMAL;
- mepcop1_16_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 4;
-
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+current_cpu->ivc2_cpsuba0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** cpsubua0_h_P0S: cpsubua0.h $crqp,$crpp
+
+sem_status
+mepcop1_16_sem_cpsubua0_h_P0S (mep_ext1_cpu* current_cpu, mepcop1_16_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_cpadd3_b_P0S_P1.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcop1_16_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsubua0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2024,6 +2563,30 @@ mepcop1_16_sem_cpsubla0_h_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
current_cpu->ivc2_cpsubla0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2046,6 +2609,60 @@ mepcop1_16_sem_cpsubaca0u_b_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsubaca0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2068,6 +2685,60 @@ mepcop1_16_sem_cpsubaca0_b_P0S (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsubaca0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2090,6 +2761,36 @@ mepcop1_16_sem_cpsubacua0_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsubacua0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2112,6 +2813,36 @@ mepcop1_16_sem_cpsubacla0_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsubacla0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2134,6 +2865,54 @@ mepcop1_16_sem_cpabsa0u_b_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpabsa0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2156,6 +2935,54 @@ mepcop1_16_sem_cpabsa0_b_P0S (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpabsa0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2178,6 +3005,30 @@ mepcop1_16_sem_cpabsua0_h_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpabsua0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2200,6 +3051,30 @@ mepcop1_16_sem_cpabsla0_h_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
current_cpu->ivc2_cpabsla0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2222,6 +3097,60 @@ mepcop1_16_sem_cpsada0u_b_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsada0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2244,6 +3173,60 @@ mepcop1_16_sem_cpsada0_b_P0S (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsada0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2266,6 +3249,36 @@ mepcop1_16_sem_cpsadua0_h_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsadua0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2288,6 +3301,36 @@ mepcop1_16_sem_cpsadla0_h_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpsadla0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2310,6 +3353,54 @@ mepcop1_16_sem_cpseta0_h_P0S (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpseta0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2332,6 +3423,30 @@ mepcop1_16_sem_cpsetua0_w_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsetua0_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2354,6 +3469,30 @@ mepcop1_16_sem_cpsetla0_w_P0S (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
current_cpu->ivc2_cpsetla0_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2781,6 +3920,60 @@ mepcop1_16_sem_cpacsuma0_P0S (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpacsuma0 (pc);
}
@@ -2803,6 +3996,54 @@ mepcop1_16_sem_cpaccpa0_P0S (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpaccpa0 (pc);
}
@@ -2825,6 +4066,54 @@ mepcop1_16_sem_cpsrla0_P0S (mep_ext1_cpu
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsrla0 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
}
@@ -2847,6 +4136,54 @@ mepcop1_16_sem_cpsraa0_P0S (mep_ext1_cpu
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsraa0 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
}
@@ -2869,6 +4206,54 @@ mepcop1_16_sem_cpslla0_P0S (mep_ext1_cpu
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpslla0 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
}
@@ -2891,6 +4276,54 @@ mepcop1_16_sem_cpsrlia0_P0S (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsrlia0 (pc, FLD (f_ivc2_5u23));
}
@@ -2913,6 +4346,54 @@ mepcop1_16_sem_cpsraia0_P0S (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsraia0 (pc, FLD (f_ivc2_5u23));
}
@@ -2935,6 +4416,54 @@ mepcop1_16_sem_cpsllia0_P0S (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpsllia0 (pc, FLD (f_ivc2_5u23));
}
@@ -2957,6 +4486,54 @@ mepcop1_16_sem_cpfsftba0s0u_b_P0S (mep_e
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpfsftba0s0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2979,6 +4556,54 @@ mepcop1_16_sem_cpfsftba0s0_b_P0S (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpfsftba0s0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3001,6 +4626,30 @@ mepcop1_16_sem_cpfsftbua0s0_h_P0S (mep_e
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpfsftbua0s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3023,6 +4672,30 @@ mepcop1_16_sem_cpfsftbla0s0_h_P0S (mep_e
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
current_cpu->ivc2_cpfsftbla0s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3045,6 +4718,60 @@ mepcop1_16_sem_cpfaca0s0u_b_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfaca0s0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3067,6 +4794,60 @@ mepcop1_16_sem_cpfaca0s0_b_P0S (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfaca0s0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3089,6 +4870,36 @@ mepcop1_16_sem_cpfacua0s0_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfacua0s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3111,6 +4922,36 @@ mepcop1_16_sem_cpfacla0s0_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfacla0s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3133,6 +4974,54 @@ mepcop1_16_sem_cpfsftba0s1u_b_P0S (mep_e
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpfsftba0s1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3155,6 +5044,54 @@ mepcop1_16_sem_cpfsftba0s1_b_P0S (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpfsftba0s1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3177,6 +5114,30 @@ mepcop1_16_sem_cpfsftbua0s1_h_P0S (mep_e
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
current_cpu->ivc2_cpfsftbua0s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3199,6 +5160,30 @@ mepcop1_16_sem_cpfsftbla0s1_h_P0S (mep_e
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
current_cpu->ivc2_cpfsftbla0s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3221,6 +5206,60 @@ mepcop1_16_sem_cpfaca0s1u_b_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfaca0s1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3243,6 +5282,60 @@ mepcop1_16_sem_cpfaca0s1_b_P0S (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfaca0s1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3265,6 +5358,36 @@ mepcop1_16_sem_cpfacua0s1_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfacua0s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -3287,6 +5410,36 @@ mepcop1_16_sem_cpfacla0s1_h_P0S (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 6) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 6), opval);
+ }
current_cpu->ivc2_cpfacla0s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
Index: sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx,v
retrieving revision 1.2
diff -p -U3 -r1.2 mep-cop1-32-decode.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx 27 May 2009 01:49:45 -0000 1.2
+++ sid/component/cgen-cpu/mep/mep-cop1-32-decode.cxx 24 Jun 2009 02:59:29 -0000
@@ -22,300 +22,300 @@ using namespace mep_ext1; // FIXME: name
mepcop1_32_idesc mepcop1_32_idesc::idesc_table[MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3 + 1] =
{
- { mepcop1_32_sem_x_invalid, "X_INVALID", MEPCOP1_32_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcop1_32_sem_cmov_crn_rm, "CMOV_CRN_RM", MEPCOP1_32_INSN_CMOV_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cmov_rn_crm, "CMOV_RN_CRM", MEPCOP1_32_INSN_CMOV_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cmovc_ccrn_rm, "CMOVC_CCRN_RM", MEPCOP1_32_INSN_CMOVC_CCRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cmovc_rn_ccrm, "CMOVC_RN_CCRM", MEPCOP1_32_INSN_CMOVC_RN_CCRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cmovh_crn_rm, "CMOVH_CRN_RM", MEPCOP1_32_INSN_CMOVH_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cmovh_rn_crm, "CMOVH_RN_CRM", MEPCOP1_32_INSN_CMOVH_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpadd3_b_C3, "CPADD3_B_C3", MEPCOP1_32_INSN_CPADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpadd3_h_C3, "CPADD3_H_C3", MEPCOP1_32_INSN_CPADD3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpadd3_w_C3, "CPADD3_W_C3", MEPCOP1_32_INSN_CPADD3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdadd3_C3, "CDADD3_C3", MEPCOP1_32_INSN_CDADD3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsub3_b_C3, "CPSUB3_B_C3", MEPCOP1_32_INSN_CPSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsub3_h_C3, "CPSUB3_H_C3", MEPCOP1_32_INSN_CPSUB3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsub3_w_C3, "CPSUB3_W_C3", MEPCOP1_32_INSN_CPSUB3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdsub3_C3, "CDSUB3_C3", MEPCOP1_32_INSN_CDSUB3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpand3_C3, "CPAND3_C3", MEPCOP1_32_INSN_CPAND3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpor3_C3, "CPOR3_C3", MEPCOP1_32_INSN_CPOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpnor3_C3, "CPNOR3_C3", MEPCOP1_32_INSN_CPNOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpxor3_C3, "CPXOR3_C3", MEPCOP1_32_INSN_CPXOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsel_C3, "CPSEL_C3", MEPCOP1_32_INSN_CPSEL_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpfsftbi_C3, "CPFSFTBI_C3", MEPCOP1_32_INSN_CPFSFTBI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpfsftbs0_C3, "CPFSFTBS0_C3", MEPCOP1_32_INSN_CPFSFTBS0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpfsftbs1_C3, "CPFSFTBS1_C3", MEPCOP1_32_INSN_CPFSFTBS1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpunpacku_b_C3, "CPUNPACKU_B_C3", MEPCOP1_32_INSN_CPUNPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpunpacku_h_C3, "CPUNPACKU_H_C3", MEPCOP1_32_INSN_CPUNPACKU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpunpacku_w_C3, "CPUNPACKU_W_C3", MEPCOP1_32_INSN_CPUNPACKU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpunpackl_b_C3, "CPUNPACKL_B_C3", MEPCOP1_32_INSN_CPUNPACKL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpunpackl_h_C3, "CPUNPACKL_H_C3", MEPCOP1_32_INSN_CPUNPACKL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpunpackl_w_C3, "CPUNPACKL_W_C3", MEPCOP1_32_INSN_CPUNPACKL_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppacku_b_C3, "CPPACKU_B_C3", MEPCOP1_32_INSN_CPPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppack_b_C3, "CPPACK_B_C3", MEPCOP1_32_INSN_CPPACK_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppack_h_C3, "CPPACK_H_C3", MEPCOP1_32_INSN_CPPACK_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrl3_b_C3, "CPSRL3_B_C3", MEPCOP1_32_INSN_CPSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssrl3_b_C3, "CPSSRL3_B_C3", MEPCOP1_32_INSN_CPSSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrl3_h_C3, "CPSRL3_H_C3", MEPCOP1_32_INSN_CPSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssrl3_h_C3, "CPSSRL3_H_C3", MEPCOP1_32_INSN_CPSSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrl3_w_C3, "CPSRL3_W_C3", MEPCOP1_32_INSN_CPSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssrl3_w_C3, "CPSSRL3_W_C3", MEPCOP1_32_INSN_CPSSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdsrl3_C3, "CDSRL3_C3", MEPCOP1_32_INSN_CDSRL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsra3_b_C3, "CPSRA3_B_C3", MEPCOP1_32_INSN_CPSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssra3_b_C3, "CPSSRA3_B_C3", MEPCOP1_32_INSN_CPSSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsra3_h_C3, "CPSRA3_H_C3", MEPCOP1_32_INSN_CPSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssra3_h_C3, "CPSSRA3_H_C3", MEPCOP1_32_INSN_CPSSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsra3_w_C3, "CPSRA3_W_C3", MEPCOP1_32_INSN_CPSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssra3_w_C3, "CPSSRA3_W_C3", MEPCOP1_32_INSN_CPSSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdsra3_C3, "CDSRA3_C3", MEPCOP1_32_INSN_CDSRA3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsll3_b_C3, "CPSLL3_B_C3", MEPCOP1_32_INSN_CPSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssll3_b_C3, "CPSSLL3_B_C3", MEPCOP1_32_INSN_CPSSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsll3_h_C3, "CPSLL3_H_C3", MEPCOP1_32_INSN_CPSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssll3_h_C3, "CPSSLL3_H_C3", MEPCOP1_32_INSN_CPSSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsll3_w_C3, "CPSLL3_W_C3", MEPCOP1_32_INSN_CPSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssll3_w_C3, "CPSSLL3_W_C3", MEPCOP1_32_INSN_CPSSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdsll3_C3, "CDSLL3_C3", MEPCOP1_32_INSN_CDSLL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsla3_h_C3, "CPSLA3_H_C3", MEPCOP1_32_INSN_CPSLA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsla3_w_C3, "CPSLA3_W_C3", MEPCOP1_32_INSN_CPSLA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsadd3_h_C3, "CPSADD3_H_C3", MEPCOP1_32_INSN_CPSADD3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsadd3_w_C3, "CPSADD3_W_C3", MEPCOP1_32_INSN_CPSADD3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssub3_h_C3, "CPSSUB3_H_C3", MEPCOP1_32_INSN_CPSSUB3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssub3_w_C3, "CPSSUB3_W_C3", MEPCOP1_32_INSN_CPSSUB3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextuaddu3_b_C3, "CPEXTUADDU3_B_C3", MEPCOP1_32_INSN_CPEXTUADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextuadd3_b_C3, "CPEXTUADD3_B_C3", MEPCOP1_32_INSN_CPEXTUADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextladdu3_b_C3, "CPEXTLADDU3_B_C3", MEPCOP1_32_INSN_CPEXTLADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextladd3_b_C3, "CPEXTLADD3_B_C3", MEPCOP1_32_INSN_CPEXTLADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextusubu3_b_C3, "CPEXTUSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTUSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextusub3_b_C3, "CPEXTUSUB3_B_C3", MEPCOP1_32_INSN_CPEXTUSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextlsubu3_b_C3, "CPEXTLSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTLSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextlsub3_b_C3, "CPEXTLSUB3_B_C3", MEPCOP1_32_INSN_CPEXTLSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaveu3_b_C3, "CPAVEU3_B_C3", MEPCOP1_32_INSN_CPAVEU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpave3_b_C3, "CPAVE3_B_C3", MEPCOP1_32_INSN_CPAVE3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpave3_h_C3, "CPAVE3_H_C3", MEPCOP1_32_INSN_CPAVE3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpave3_w_C3, "CPAVE3_W_C3", MEPCOP1_32_INSN_CPAVE3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddsru3_b_C3, "CPADDSRU3_B_C3", MEPCOP1_32_INSN_CPADDSRU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddsr3_b_C3, "CPADDSR3_B_C3", MEPCOP1_32_INSN_CPADDSR3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddsr3_h_C3, "CPADDSR3_H_C3", MEPCOP1_32_INSN_CPADDSR3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddsr3_w_C3, "CPADDSR3_W_C3", MEPCOP1_32_INSN_CPADDSR3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsu3_b_C3, "CPABSU3_B_C3", MEPCOP1_32_INSN_CPABSU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabs3_b_C3, "CPABS3_B_C3", MEPCOP1_32_INSN_CPABS3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabs3_h_C3, "CPABS3_H_C3", MEPCOP1_32_INSN_CPABS3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmaxu3_b_C3, "CPMAXU3_B_C3", MEPCOP1_32_INSN_CPMAXU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmax3_b_C3, "CPMAX3_B_C3", MEPCOP1_32_INSN_CPMAX3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmax3_h_C3, "CPMAX3_H_C3", MEPCOP1_32_INSN_CPMAX3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmaxu3_w_C3, "CPMAXU3_W_C3", MEPCOP1_32_INSN_CPMAXU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmax3_w_C3, "CPMAX3_W_C3", MEPCOP1_32_INSN_CPMAX3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpminu3_b_C3, "CPMINU3_B_C3", MEPCOP1_32_INSN_CPMINU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmin3_b_C3, "CPMIN3_B_C3", MEPCOP1_32_INSN_CPMIN3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmin3_h_C3, "CPMIN3_H_C3", MEPCOP1_32_INSN_CPMIN3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpminu3_w_C3, "CPMINU3_W_C3", MEPCOP1_32_INSN_CPMINU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmin3_w_C3, "CPMIN3_W_C3", MEPCOP1_32_INSN_CPMIN3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovfrcsar0_C3, "CPMOVFRCSAR0_C3", MEPCOP1_32_INSN_CPMOVFRCSAR0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovfrcsar1_C3, "CPMOVFRCSAR1_C3", MEPCOP1_32_INSN_CPMOVFRCSAR1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovfrcc_C3, "CPMOVFRCC_C3", MEPCOP1_32_INSN_CPMOVFRCC_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovtocsar0_C3, "CPMOVTOCSAR0_C3", MEPCOP1_32_INSN_CPMOVTOCSAR0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovtocsar1_C3, "CPMOVTOCSAR1_C3", MEPCOP1_32_INSN_CPMOVTOCSAR1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovtocc_C3, "CPMOVTOCC_C3", MEPCOP1_32_INSN_CPMOVTOCC_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmov_C3, "CPMOV_C3", MEPCOP1_32_INSN_CPMOV_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsz_b_C3, "CPABSZ_B_C3", MEPCOP1_32_INSN_CPABSZ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsz_h_C3, "CPABSZ_H_C3", MEPCOP1_32_INSN_CPABSZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsz_w_C3, "CPABSZ_W_C3", MEPCOP1_32_INSN_CPABSZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpldz_h_C3, "CPLDZ_H_C3", MEPCOP1_32_INSN_CPLDZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpldz_w_C3, "CPLDZ_W_C3", MEPCOP1_32_INSN_CPLDZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpnorm_h_C3, "CPNORM_H_C3", MEPCOP1_32_INSN_CPNORM_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpnorm_w_C3, "CPNORM_W_C3", MEPCOP1_32_INSN_CPNORM_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cphaddu_b_C3, "CPHADDU_B_C3", MEPCOP1_32_INSN_CPHADDU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cphadd_b_C3, "CPHADD_B_C3", MEPCOP1_32_INSN_CPHADD_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cphadd_h_C3, "CPHADD_H_C3", MEPCOP1_32_INSN_CPHADD_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cphadd_w_C3, "CPHADD_W_C3", MEPCOP1_32_INSN_CPHADD_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpccadd_b_C3, "CPCCADD_B_C3", MEPCOP1_32_INSN_CPCCADD_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpbcast_b_C3, "CPBCAST_B_C3", MEPCOP1_32_INSN_CPBCAST_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpbcast_h_C3, "CPBCAST_H_C3", MEPCOP1_32_INSN_CPBCAST_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpbcast_w_C3, "CPBCAST_W_C3", MEPCOP1_32_INSN_CPBCAST_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextuu_b_C3, "CPEXTUU_B_C3", MEPCOP1_32_INSN_CPEXTUU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextu_b_C3, "CPEXTU_B_C3", MEPCOP1_32_INSN_CPEXTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextuu_h_C3, "CPEXTUU_H_C3", MEPCOP1_32_INSN_CPEXTUU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextu_h_C3, "CPEXTU_H_C3", MEPCOP1_32_INSN_CPEXTU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextlu_b_C3, "CPEXTLU_B_C3", MEPCOP1_32_INSN_CPEXTLU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextl_b_C3, "CPEXTL_B_C3", MEPCOP1_32_INSN_CPEXTL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextlu_h_C3, "CPEXTLU_H_C3", MEPCOP1_32_INSN_CPEXTLU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpextl_h_C3, "CPEXTL_H_C3", MEPCOP1_32_INSN_CPEXTL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcastub_h_C3, "CPCASTUB_H_C3", MEPCOP1_32_INSN_CPCASTUB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcastb_h_C3, "CPCASTB_H_C3", MEPCOP1_32_INSN_CPCASTB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcastub_w_C3, "CPCASTUB_W_C3", MEPCOP1_32_INSN_CPCASTUB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcastb_w_C3, "CPCASTB_W_C3", MEPCOP1_32_INSN_CPCASTB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcastuh_w_C3, "CPCASTUH_W_C3", MEPCOP1_32_INSN_CPCASTUH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcasth_w_C3, "CPCASTH_W_C3", MEPCOP1_32_INSN_CPCASTH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdcastuw_C3, "CDCASTUW_C3", MEPCOP1_32_INSN_CDCASTUW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdcastw_C3, "CDCASTW_C3", MEPCOP1_32_INSN_CDCASTW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpeqz_b_C3, "CPCMPEQZ_B_C3", MEPCOP1_32_INSN_CPCMPEQZ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpeq_b_C3, "CPCMPEQ_B_C3", MEPCOP1_32_INSN_CPCMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpeq_h_C3, "CPCMPEQ_H_C3", MEPCOP1_32_INSN_CPCMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpeq_w_C3, "CPCMPEQ_W_C3", MEPCOP1_32_INSN_CPCMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpne_b_C3, "CPCMPNE_B_C3", MEPCOP1_32_INSN_CPCMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpne_h_C3, "CPCMPNE_H_C3", MEPCOP1_32_INSN_CPCMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpne_w_C3, "CPCMPNE_W_C3", MEPCOP1_32_INSN_CPCMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpgtu_b_C3, "CPCMPGTU_B_C3", MEPCOP1_32_INSN_CPCMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpgt_b_C3, "CPCMPGT_B_C3", MEPCOP1_32_INSN_CPCMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpgt_h_C3, "CPCMPGT_H_C3", MEPCOP1_32_INSN_CPCMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpgtu_w_C3, "CPCMPGTU_W_C3", MEPCOP1_32_INSN_CPCMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpgt_w_C3, "CPCMPGT_W_C3", MEPCOP1_32_INSN_CPCMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpgeu_b_C3, "CPCMPGEU_B_C3", MEPCOP1_32_INSN_CPCMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpge_b_C3, "CPCMPGE_B_C3", MEPCOP1_32_INSN_CPCMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpge_h_C3, "CPCMPGE_H_C3", MEPCOP1_32_INSN_CPCMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpgeu_w_C3, "CPCMPGEU_W_C3", MEPCOP1_32_INSN_CPCMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpcmpge_w_C3, "CPCMPGE_W_C3", MEPCOP1_32_INSN_CPCMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpeq_b_C3, "CPACMPEQ_B_C3", MEPCOP1_32_INSN_CPACMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpeq_h_C3, "CPACMPEQ_H_C3", MEPCOP1_32_INSN_CPACMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpeq_w_C3, "CPACMPEQ_W_C3", MEPCOP1_32_INSN_CPACMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpne_b_C3, "CPACMPNE_B_C3", MEPCOP1_32_INSN_CPACMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpne_h_C3, "CPACMPNE_H_C3", MEPCOP1_32_INSN_CPACMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpne_w_C3, "CPACMPNE_W_C3", MEPCOP1_32_INSN_CPACMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpgtu_b_C3, "CPACMPGTU_B_C3", MEPCOP1_32_INSN_CPACMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpgt_b_C3, "CPACMPGT_B_C3", MEPCOP1_32_INSN_CPACMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpgt_h_C3, "CPACMPGT_H_C3", MEPCOP1_32_INSN_CPACMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpgtu_w_C3, "CPACMPGTU_W_C3", MEPCOP1_32_INSN_CPACMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpgt_w_C3, "CPACMPGT_W_C3", MEPCOP1_32_INSN_CPACMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpgeu_b_C3, "CPACMPGEU_B_C3", MEPCOP1_32_INSN_CPACMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpge_b_C3, "CPACMPGE_B_C3", MEPCOP1_32_INSN_CPACMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpge_h_C3, "CPACMPGE_H_C3", MEPCOP1_32_INSN_CPACMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpgeu_w_C3, "CPACMPGEU_W_C3", MEPCOP1_32_INSN_CPACMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpacmpge_w_C3, "CPACMPGE_W_C3", MEPCOP1_32_INSN_CPACMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpeq_b_C3, "CPOCMPEQ_B_C3", MEPCOP1_32_INSN_CPOCMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpeq_h_C3, "CPOCMPEQ_H_C3", MEPCOP1_32_INSN_CPOCMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpeq_w_C3, "CPOCMPEQ_W_C3", MEPCOP1_32_INSN_CPOCMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpne_b_C3, "CPOCMPNE_B_C3", MEPCOP1_32_INSN_CPOCMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpne_h_C3, "CPOCMPNE_H_C3", MEPCOP1_32_INSN_CPOCMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpne_w_C3, "CPOCMPNE_W_C3", MEPCOP1_32_INSN_CPOCMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpgtu_b_C3, "CPOCMPGTU_B_C3", MEPCOP1_32_INSN_CPOCMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpgt_b_C3, "CPOCMPGT_B_C3", MEPCOP1_32_INSN_CPOCMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpgt_h_C3, "CPOCMPGT_H_C3", MEPCOP1_32_INSN_CPOCMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpgtu_w_C3, "CPOCMPGTU_W_C3", MEPCOP1_32_INSN_CPOCMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpgt_w_C3, "CPOCMPGT_W_C3", MEPCOP1_32_INSN_CPOCMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpgeu_b_C3, "CPOCMPGEU_B_C3", MEPCOP1_32_INSN_CPOCMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpge_b_C3, "CPOCMPGE_B_C3", MEPCOP1_32_INSN_CPOCMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpge_h_C3, "CPOCMPGE_H_C3", MEPCOP1_32_INSN_CPOCMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpgeu_w_C3, "CPOCMPGEU_W_C3", MEPCOP1_32_INSN_CPOCMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpocmpge_w_C3, "CPOCMPGE_W_C3", MEPCOP1_32_INSN_CPOCMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrli3_b_C3, "CPSRLI3_B_C3", MEPCOP1_32_INSN_CPSRLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrli3_h_C3, "CPSRLI3_H_C3", MEPCOP1_32_INSN_CPSRLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrli3_w_C3, "CPSRLI3_W_C3", MEPCOP1_32_INSN_CPSRLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdsrli3_C3, "CDSRLI3_C3", MEPCOP1_32_INSN_CDSRLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrai3_b_C3, "CPSRAI3_B_C3", MEPCOP1_32_INSN_CPSRAI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrai3_h_C3, "CPSRAI3_H_C3", MEPCOP1_32_INSN_CPSRAI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrai3_w_C3, "CPSRAI3_W_C3", MEPCOP1_32_INSN_CPSRAI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdsrai3_C3, "CDSRAI3_C3", MEPCOP1_32_INSN_CDSRAI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpslli3_b_C3, "CPSLLI3_B_C3", MEPCOP1_32_INSN_CPSLLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpslli3_h_C3, "CPSLLI3_H_C3", MEPCOP1_32_INSN_CPSLLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpslli3_w_C3, "CPSLLI3_W_C3", MEPCOP1_32_INSN_CPSLLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdslli3_C3, "CDSLLI3_C3", MEPCOP1_32_INSN_CDSLLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpslai3_h_C3, "CPSLAI3_H_C3", MEPCOP1_32_INSN_CPSLAI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpslai3_w_C3, "CPSLAI3_W_C3", MEPCOP1_32_INSN_CPSLAI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpclipiu3_w_C3, "CPCLIPIU3_W_C3", MEPCOP1_32_INSN_CPCLIPIU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpclipi3_w_C3, "CPCLIPI3_W_C3", MEPCOP1_32_INSN_CPCLIPI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdclipiu3_C3, "CDCLIPIU3_C3", MEPCOP1_32_INSN_CDCLIPIU3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdclipi3_C3, "CDCLIPI3_C3", MEPCOP1_32_INSN_CDCLIPI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovi_b_C3, "CPMOVI_B_C3", MEPCOP1_32_INSN_CPMOVI_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmoviu_h_C3, "CPMOVIU_H_C3", MEPCOP1_32_INSN_CPMOVIU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovi_h_C3, "CPMOVI_H_C3", MEPCOP1_32_INSN_CPMOVI_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmoviu_w_C3, "CPMOVIU_W_C3", MEPCOP1_32_INSN_CPMOVIU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovi_w_C3, "CPMOVI_W_C3", MEPCOP1_32_INSN_CPMOVI_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdmoviu_C3, "CDMOVIU_C3", MEPCOP1_32_INSN_CDMOVIU_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cdmovi_C3, "CDMOVI_C3", MEPCOP1_32_INSN_CDMOVI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpadda1u_b_C3, "CPADDA1U_B_C3", MEPCOP1_32_INSN_CPADDA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpadda1_b_C3, "CPADDA1_B_C3", MEPCOP1_32_INSN_CPADDA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddua1_h_C3, "CPADDUA1_H_C3", MEPCOP1_32_INSN_CPADDUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddla1_h_C3, "CPADDLA1_H_C3", MEPCOP1_32_INSN_CPADDLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddaca1u_b_C3, "CPADDACA1U_B_C3", MEPCOP1_32_INSN_CPADDACA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddaca1_b_C3, "CPADDACA1_B_C3", MEPCOP1_32_INSN_CPADDACA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddacua1_h_C3, "CPADDACUA1_H_C3", MEPCOP1_32_INSN_CPADDACUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpaddacla1_h_C3, "CPADDACLA1_H_C3", MEPCOP1_32_INSN_CPADDACLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsuba1u_b_C3, "CPSUBA1U_B_C3", MEPCOP1_32_INSN_CPSUBA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsuba1_b_C3, "CPSUBA1_B_C3", MEPCOP1_32_INSN_CPSUBA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsubua1_h_C3, "CPSUBUA1_H_C3", MEPCOP1_32_INSN_CPSUBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsubla1_h_C3, "CPSUBLA1_H_C3", MEPCOP1_32_INSN_CPSUBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsubaca1u_b_C3, "CPSUBACA1U_B_C3", MEPCOP1_32_INSN_CPSUBACA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsubaca1_b_C3, "CPSUBACA1_B_C3", MEPCOP1_32_INSN_CPSUBACA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsubacua1_h_C3, "CPSUBACUA1_H_C3", MEPCOP1_32_INSN_CPSUBACUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsubacla1_h_C3, "CPSUBACLA1_H_C3", MEPCOP1_32_INSN_CPSUBACLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsa1u_b_C3, "CPABSA1U_B_C3", MEPCOP1_32_INSN_CPABSA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsa1_b_C3, "CPABSA1_B_C3", MEPCOP1_32_INSN_CPABSA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsua1_h_C3, "CPABSUA1_H_C3", MEPCOP1_32_INSN_CPABSUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpabsla1_h_C3, "CPABSLA1_H_C3", MEPCOP1_32_INSN_CPABSLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsada1u_b_C3, "CPSADA1U_B_C3", MEPCOP1_32_INSN_CPSADA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsada1_b_C3, "CPSADA1_B_C3", MEPCOP1_32_INSN_CPSADA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsadua1_h_C3, "CPSADUA1_H_C3", MEPCOP1_32_INSN_CPSADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsadla1_h_C3, "CPSADLA1_H_C3", MEPCOP1_32_INSN_CPSADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpseta1_h_C3, "CPSETA1_H_C3", MEPCOP1_32_INSN_CPSETA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsetua1_w_C3, "CPSETUA1_W_C3", MEPCOP1_32_INSN_CPSETUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsetla1_w_C3, "CPSETLA1_W_C3", MEPCOP1_32_INSN_CPSETLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmova1_b_C3, "CPMOVA1_B_C3", MEPCOP1_32_INSN_CPMOVA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovua1_h_C3, "CPMOVUA1_H_C3", MEPCOP1_32_INSN_CPMOVUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovla1_h_C3, "CPMOVLA1_H_C3", MEPCOP1_32_INSN_CPMOVLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovuua1_w_C3, "CPMOVUUA1_W_C3", MEPCOP1_32_INSN_CPMOVUUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovula1_w_C3, "CPMOVULA1_W_C3", MEPCOP1_32_INSN_CPMOVULA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovlua1_w_C3, "CPMOVLUA1_W_C3", MEPCOP1_32_INSN_CPMOVLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovlla1_w_C3, "CPMOVLLA1_W_C3", MEPCOP1_32_INSN_CPMOVLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppacka1u_b_C3, "CPPACKA1U_B_C3", MEPCOP1_32_INSN_CPPACKA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppacka1_b_C3, "CPPACKA1_B_C3", MEPCOP1_32_INSN_CPPACKA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppackua1_h_C3, "CPPACKUA1_H_C3", MEPCOP1_32_INSN_CPPACKUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppackla1_h_C3, "CPPACKLA1_H_C3", MEPCOP1_32_INSN_CPPACKLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppackua1_w_C3, "CPPACKUA1_W_C3", MEPCOP1_32_INSN_CPPACKUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cppackla1_w_C3, "CPPACKLA1_W_C3", MEPCOP1_32_INSN_CPPACKLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovhua1_w_C3, "CPMOVHUA1_W_C3", MEPCOP1_32_INSN_CPMOVHUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmovhla1_w_C3, "CPMOVHLA1_W_C3", MEPCOP1_32_INSN_CPMOVHLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrla1_C3, "CPSRLA1_C3", MEPCOP1_32_INSN_CPSRLA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsraa1_C3, "CPSRAA1_C3", MEPCOP1_32_INSN_CPSRAA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpslla1_C3, "CPSLLA1_C3", MEPCOP1_32_INSN_CPSLLA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsrlia1_P1, "CPSRLIA1_P1", MEPCOP1_32_INSN_CPSRLIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsraia1_P1, "CPSRAIA1_P1", MEPCOP1_32_INSN_CPSRAIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsllia1_P1, "CPSLLIA1_P1", MEPCOP1_32_INSN_CPSLLIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssqa1u_b_C3, "CPSSQA1U_B_C3", MEPCOP1_32_INSN_CPSSQA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssqa1_b_C3, "CPSSQA1_B_C3", MEPCOP1_32_INSN_CPSSQA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssda1u_b_C3, "CPSSDA1U_B_C3", MEPCOP1_32_INSN_CPSSDA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpssda1_b_C3, "CPSSDA1_B_C3", MEPCOP1_32_INSN_CPSSDA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmula1u_b_C3, "CPMULA1U_B_C3", MEPCOP1_32_INSN_CPMULA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmula1_b_C3, "CPMULA1_B_C3", MEPCOP1_32_INSN_CPMULA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulua1_h_C3, "CPMULUA1_H_C3", MEPCOP1_32_INSN_CPMULUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulla1_h_C3, "CPMULLA1_H_C3", MEPCOP1_32_INSN_CPMULLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulua1u_w_C3, "CPMULUA1U_W_C3", MEPCOP1_32_INSN_CPMULUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulla1u_w_C3, "CPMULLA1U_W_C3", MEPCOP1_32_INSN_CPMULLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulua1_w_C3, "CPMULUA1_W_C3", MEPCOP1_32_INSN_CPMULUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulla1_w_C3, "CPMULLA1_W_C3", MEPCOP1_32_INSN_CPMULLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmada1u_b_C3, "CPMADA1U_B_C3", MEPCOP1_32_INSN_CPMADA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmada1_b_C3, "CPMADA1_B_C3", MEPCOP1_32_INSN_CPMADA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmadua1_h_C3, "CPMADUA1_H_C3", MEPCOP1_32_INSN_CPMADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmadla1_h_C3, "CPMADLA1_H_C3", MEPCOP1_32_INSN_CPMADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmadua1u_w_C3, "CPMADUA1U_W_C3", MEPCOP1_32_INSN_CPMADUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmadla1u_w_C3, "CPMADLA1U_W_C3", MEPCOP1_32_INSN_CPMADLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmadua1_w_C3, "CPMADUA1_W_C3", MEPCOP1_32_INSN_CPMADUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmadla1_w_C3, "CPMADLA1_W_C3", MEPCOP1_32_INSN_CPMADLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmsbua1_h_C3, "CPMSBUA1_H_C3", MEPCOP1_32_INSN_CPMSBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmsbla1_h_C3, "CPMSBLA1_H_C3", MEPCOP1_32_INSN_CPMSBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmsbua1u_w_C3, "CPMSBUA1U_W_C3", MEPCOP1_32_INSN_CPMSBUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmsbla1u_w_C3, "CPMSBLA1U_W_C3", MEPCOP1_32_INSN_CPMSBLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmsbua1_w_C3, "CPMSBUA1_W_C3", MEPCOP1_32_INSN_CPMSBUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmsbla1_w_C3, "CPMSBLA1_W_C3", MEPCOP1_32_INSN_CPMSBLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadua1_h_C3, "CPSMADUA1_H_C3", MEPCOP1_32_INSN_CPSMADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadla1_h_C3, "CPSMADLA1_H_C3", MEPCOP1_32_INSN_CPSMADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadua1_w_C3, "CPSMADUA1_W_C3", MEPCOP1_32_INSN_CPSMADUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadla1_w_C3, "CPSMADLA1_W_C3", MEPCOP1_32_INSN_CPSMADLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbua1_h_C3, "CPSMSBUA1_H_C3", MEPCOP1_32_INSN_CPSMSBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbla1_h_C3, "CPSMSBLA1_H_C3", MEPCOP1_32_INSN_CPSMSBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbua1_w_C3, "CPSMSBUA1_W_C3", MEPCOP1_32_INSN_CPSMSBUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbla1_w_C3, "CPSMSBLA1_W_C3", MEPCOP1_32_INSN_CPSMSBLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulslua1_h_C3, "CPMULSLUA1_H_C3", MEPCOP1_32_INSN_CPMULSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulslla1_h_C3, "CPMULSLLA1_H_C3", MEPCOP1_32_INSN_CPMULSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulslua1_w_C3, "CPMULSLUA1_W_C3", MEPCOP1_32_INSN_CPMULSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpmulslla1_w_C3, "CPMULSLLA1_W_C3", MEPCOP1_32_INSN_CPMULSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadslua1_h_C3, "CPSMADSLUA1_H_C3", MEPCOP1_32_INSN_CPSMADSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadslla1_h_C3, "CPSMADSLLA1_H_C3", MEPCOP1_32_INSN_CPSMADSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadslua1_w_C3, "CPSMADSLUA1_W_C3", MEPCOP1_32_INSN_CPSMADSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmadslla1_w_C3, "CPSMADSLLA1_W_C3", MEPCOP1_32_INSN_CPSMADSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbslua1_h_C3, "CPSMSBSLUA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbslla1_h_C3, "CPSMSBSLLA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbslua1_w_C3, "CPSMSBSLUA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
- { mepcop1_32_sem_cpsmsbslla1_w_C3, "CPSMSBSLLA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_x_invalid, "X_INVALID", MEPCOP1_32_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcop1_32_sem_cmov_crn_rm, "CMOV_CRN_RM", MEPCOP1_32_INSN_CMOV_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cmov_rn_crm, "CMOV_RN_CRM", MEPCOP1_32_INSN_CMOV_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cmovc_ccrn_rm, "CMOVC_CCRN_RM", MEPCOP1_32_INSN_CMOVC_CCRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cmovc_rn_ccrm, "CMOVC_RN_CCRM", MEPCOP1_32_INSN_CMOVC_RN_CCRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cmovh_crn_rm, "CMOVH_CRN_RM", MEPCOP1_32_INSN_CMOVH_CRN_RM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cmovh_rn_crm, "CMOVH_RN_CRM", MEPCOP1_32_INSN_CMOVH_RN_CRM, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpadd3_b_C3, "CPADD3_B_C3", MEPCOP1_32_INSN_CPADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpadd3_h_C3, "CPADD3_H_C3", MEPCOP1_32_INSN_CPADD3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpadd3_w_C3, "CPADD3_W_C3", MEPCOP1_32_INSN_CPADD3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdadd3_C3, "CDADD3_C3", MEPCOP1_32_INSN_CDADD3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsub3_b_C3, "CPSUB3_B_C3", MEPCOP1_32_INSN_CPSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsub3_h_C3, "CPSUB3_H_C3", MEPCOP1_32_INSN_CPSUB3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsub3_w_C3, "CPSUB3_W_C3", MEPCOP1_32_INSN_CPSUB3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdsub3_C3, "CDSUB3_C3", MEPCOP1_32_INSN_CDSUB3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpand3_C3, "CPAND3_C3", MEPCOP1_32_INSN_CPAND3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpor3_C3, "CPOR3_C3", MEPCOP1_32_INSN_CPOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpnor3_C3, "CPNOR3_C3", MEPCOP1_32_INSN_CPNOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpxor3_C3, "CPXOR3_C3", MEPCOP1_32_INSN_CPXOR3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsel_C3, "CPSEL_C3", MEPCOP1_32_INSN_CPSEL_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpfsftbi_C3, "CPFSFTBI_C3", MEPCOP1_32_INSN_CPFSFTBI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpfsftbs0_C3, "CPFSFTBS0_C3", MEPCOP1_32_INSN_CPFSFTBS0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpfsftbs1_C3, "CPFSFTBS1_C3", MEPCOP1_32_INSN_CPFSFTBS1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpunpacku_b_C3, "CPUNPACKU_B_C3", MEPCOP1_32_INSN_CPUNPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpunpacku_h_C3, "CPUNPACKU_H_C3", MEPCOP1_32_INSN_CPUNPACKU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpunpacku_w_C3, "CPUNPACKU_W_C3", MEPCOP1_32_INSN_CPUNPACKU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpunpackl_b_C3, "CPUNPACKL_B_C3", MEPCOP1_32_INSN_CPUNPACKL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpunpackl_h_C3, "CPUNPACKL_H_C3", MEPCOP1_32_INSN_CPUNPACKL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpunpackl_w_C3, "CPUNPACKL_W_C3", MEPCOP1_32_INSN_CPUNPACKL_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppacku_b_C3, "CPPACKU_B_C3", MEPCOP1_32_INSN_CPPACKU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppack_b_C3, "CPPACK_B_C3", MEPCOP1_32_INSN_CPPACK_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppack_h_C3, "CPPACK_H_C3", MEPCOP1_32_INSN_CPPACK_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrl3_b_C3, "CPSRL3_B_C3", MEPCOP1_32_INSN_CPSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssrl3_b_C3, "CPSSRL3_B_C3", MEPCOP1_32_INSN_CPSSRL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrl3_h_C3, "CPSRL3_H_C3", MEPCOP1_32_INSN_CPSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssrl3_h_C3, "CPSSRL3_H_C3", MEPCOP1_32_INSN_CPSSRL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrl3_w_C3, "CPSRL3_W_C3", MEPCOP1_32_INSN_CPSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssrl3_w_C3, "CPSSRL3_W_C3", MEPCOP1_32_INSN_CPSSRL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdsrl3_C3, "CDSRL3_C3", MEPCOP1_32_INSN_CDSRL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsra3_b_C3, "CPSRA3_B_C3", MEPCOP1_32_INSN_CPSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssra3_b_C3, "CPSSRA3_B_C3", MEPCOP1_32_INSN_CPSSRA3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsra3_h_C3, "CPSRA3_H_C3", MEPCOP1_32_INSN_CPSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssra3_h_C3, "CPSSRA3_H_C3", MEPCOP1_32_INSN_CPSSRA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsra3_w_C3, "CPSRA3_W_C3", MEPCOP1_32_INSN_CPSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssra3_w_C3, "CPSSRA3_W_C3", MEPCOP1_32_INSN_CPSSRA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdsra3_C3, "CDSRA3_C3", MEPCOP1_32_INSN_CDSRA3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsll3_b_C3, "CPSLL3_B_C3", MEPCOP1_32_INSN_CPSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssll3_b_C3, "CPSSLL3_B_C3", MEPCOP1_32_INSN_CPSSLL3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsll3_h_C3, "CPSLL3_H_C3", MEPCOP1_32_INSN_CPSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssll3_h_C3, "CPSSLL3_H_C3", MEPCOP1_32_INSN_CPSSLL3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsll3_w_C3, "CPSLL3_W_C3", MEPCOP1_32_INSN_CPSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssll3_w_C3, "CPSSLL3_W_C3", MEPCOP1_32_INSN_CPSSLL3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdsll3_C3, "CDSLL3_C3", MEPCOP1_32_INSN_CDSLL3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsla3_h_C3, "CPSLA3_H_C3", MEPCOP1_32_INSN_CPSLA3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsla3_w_C3, "CPSLA3_W_C3", MEPCOP1_32_INSN_CPSLA3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsadd3_h_C3, "CPSADD3_H_C3", MEPCOP1_32_INSN_CPSADD3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsadd3_w_C3, "CPSADD3_W_C3", MEPCOP1_32_INSN_CPSADD3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssub3_h_C3, "CPSSUB3_H_C3", MEPCOP1_32_INSN_CPSSUB3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssub3_w_C3, "CPSSUB3_W_C3", MEPCOP1_32_INSN_CPSSUB3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextuaddu3_b_C3, "CPEXTUADDU3_B_C3", MEPCOP1_32_INSN_CPEXTUADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextuadd3_b_C3, "CPEXTUADD3_B_C3", MEPCOP1_32_INSN_CPEXTUADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextladdu3_b_C3, "CPEXTLADDU3_B_C3", MEPCOP1_32_INSN_CPEXTLADDU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextladd3_b_C3, "CPEXTLADD3_B_C3", MEPCOP1_32_INSN_CPEXTLADD3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextusubu3_b_C3, "CPEXTUSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTUSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextusub3_b_C3, "CPEXTUSUB3_B_C3", MEPCOP1_32_INSN_CPEXTUSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextlsubu3_b_C3, "CPEXTLSUBU3_B_C3", MEPCOP1_32_INSN_CPEXTLSUBU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextlsub3_b_C3, "CPEXTLSUB3_B_C3", MEPCOP1_32_INSN_CPEXTLSUB3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaveu3_b_C3, "CPAVEU3_B_C3", MEPCOP1_32_INSN_CPAVEU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpave3_b_C3, "CPAVE3_B_C3", MEPCOP1_32_INSN_CPAVE3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpave3_h_C3, "CPAVE3_H_C3", MEPCOP1_32_INSN_CPAVE3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpave3_w_C3, "CPAVE3_W_C3", MEPCOP1_32_INSN_CPAVE3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddsru3_b_C3, "CPADDSRU3_B_C3", MEPCOP1_32_INSN_CPADDSRU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddsr3_b_C3, "CPADDSR3_B_C3", MEPCOP1_32_INSN_CPADDSR3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddsr3_h_C3, "CPADDSR3_H_C3", MEPCOP1_32_INSN_CPADDSR3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddsr3_w_C3, "CPADDSR3_W_C3", MEPCOP1_32_INSN_CPADDSR3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsu3_b_C3, "CPABSU3_B_C3", MEPCOP1_32_INSN_CPABSU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabs3_b_C3, "CPABS3_B_C3", MEPCOP1_32_INSN_CPABS3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabs3_h_C3, "CPABS3_H_C3", MEPCOP1_32_INSN_CPABS3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmaxu3_b_C3, "CPMAXU3_B_C3", MEPCOP1_32_INSN_CPMAXU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmax3_b_C3, "CPMAX3_B_C3", MEPCOP1_32_INSN_CPMAX3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmax3_h_C3, "CPMAX3_H_C3", MEPCOP1_32_INSN_CPMAX3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmaxu3_w_C3, "CPMAXU3_W_C3", MEPCOP1_32_INSN_CPMAXU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmax3_w_C3, "CPMAX3_W_C3", MEPCOP1_32_INSN_CPMAX3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpminu3_b_C3, "CPMINU3_B_C3", MEPCOP1_32_INSN_CPMINU3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmin3_b_C3, "CPMIN3_B_C3", MEPCOP1_32_INSN_CPMIN3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmin3_h_C3, "CPMIN3_H_C3", MEPCOP1_32_INSN_CPMIN3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpminu3_w_C3, "CPMINU3_W_C3", MEPCOP1_32_INSN_CPMINU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmin3_w_C3, "CPMIN3_W_C3", MEPCOP1_32_INSN_CPMIN3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovfrcsar0_C3, "CPMOVFRCSAR0_C3", MEPCOP1_32_INSN_CPMOVFRCSAR0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovfrcsar1_C3, "CPMOVFRCSAR1_C3", MEPCOP1_32_INSN_CPMOVFRCSAR1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovfrcc_C3, "CPMOVFRCC_C3", MEPCOP1_32_INSN_CPMOVFRCC_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovtocsar0_C3, "CPMOVTOCSAR0_C3", MEPCOP1_32_INSN_CPMOVTOCSAR0_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovtocsar1_C3, "CPMOVTOCSAR1_C3", MEPCOP1_32_INSN_CPMOVTOCSAR1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovtocc_C3, "CPMOVTOCC_C3", MEPCOP1_32_INSN_CPMOVTOCC_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmov_C3, "CPMOV_C3", MEPCOP1_32_INSN_CPMOV_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsz_b_C3, "CPABSZ_B_C3", MEPCOP1_32_INSN_CPABSZ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsz_h_C3, "CPABSZ_H_C3", MEPCOP1_32_INSN_CPABSZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsz_w_C3, "CPABSZ_W_C3", MEPCOP1_32_INSN_CPABSZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpldz_h_C3, "CPLDZ_H_C3", MEPCOP1_32_INSN_CPLDZ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpldz_w_C3, "CPLDZ_W_C3", MEPCOP1_32_INSN_CPLDZ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpnorm_h_C3, "CPNORM_H_C3", MEPCOP1_32_INSN_CPNORM_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpnorm_w_C3, "CPNORM_W_C3", MEPCOP1_32_INSN_CPNORM_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cphaddu_b_C3, "CPHADDU_B_C3", MEPCOP1_32_INSN_CPHADDU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cphadd_b_C3, "CPHADD_B_C3", MEPCOP1_32_INSN_CPHADD_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cphadd_h_C3, "CPHADD_H_C3", MEPCOP1_32_INSN_CPHADD_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cphadd_w_C3, "CPHADD_W_C3", MEPCOP1_32_INSN_CPHADD_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpccadd_b_C3, "CPCCADD_B_C3", MEPCOP1_32_INSN_CPCCADD_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRSTCOPY, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpbcast_b_C3, "CPBCAST_B_C3", MEPCOP1_32_INSN_CPBCAST_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpbcast_h_C3, "CPBCAST_H_C3", MEPCOP1_32_INSN_CPBCAST_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpbcast_w_C3, "CPBCAST_W_C3", MEPCOP1_32_INSN_CPBCAST_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextuu_b_C3, "CPEXTUU_B_C3", MEPCOP1_32_INSN_CPEXTUU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextu_b_C3, "CPEXTU_B_C3", MEPCOP1_32_INSN_CPEXTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextuu_h_C3, "CPEXTUU_H_C3", MEPCOP1_32_INSN_CPEXTUU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextu_h_C3, "CPEXTU_H_C3", MEPCOP1_32_INSN_CPEXTU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextlu_b_C3, "CPEXTLU_B_C3", MEPCOP1_32_INSN_CPEXTLU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextl_b_C3, "CPEXTL_B_C3", MEPCOP1_32_INSN_CPEXTL_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextlu_h_C3, "CPEXTLU_H_C3", MEPCOP1_32_INSN_CPEXTLU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpextl_h_C3, "CPEXTL_H_C3", MEPCOP1_32_INSN_CPEXTL_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcastub_h_C3, "CPCASTUB_H_C3", MEPCOP1_32_INSN_CPCASTUB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcastb_h_C3, "CPCASTB_H_C3", MEPCOP1_32_INSN_CPCASTB_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcastub_w_C3, "CPCASTUB_W_C3", MEPCOP1_32_INSN_CPCASTUB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcastb_w_C3, "CPCASTB_W_C3", MEPCOP1_32_INSN_CPCASTB_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcastuh_w_C3, "CPCASTUH_W_C3", MEPCOP1_32_INSN_CPCASTUH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcasth_w_C3, "CPCASTH_W_C3", MEPCOP1_32_INSN_CPCASTH_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdcastuw_C3, "CDCASTUW_C3", MEPCOP1_32_INSN_CDCASTUW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdcastw_C3, "CDCASTW_C3", MEPCOP1_32_INSN_CDCASTW_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpeqz_b_C3, "CPCMPEQZ_B_C3", MEPCOP1_32_INSN_CPCMPEQZ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpeq_b_C3, "CPCMPEQ_B_C3", MEPCOP1_32_INSN_CPCMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpeq_h_C3, "CPCMPEQ_H_C3", MEPCOP1_32_INSN_CPCMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpeq_w_C3, "CPCMPEQ_W_C3", MEPCOP1_32_INSN_CPCMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpne_b_C3, "CPCMPNE_B_C3", MEPCOP1_32_INSN_CPCMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpne_h_C3, "CPCMPNE_H_C3", MEPCOP1_32_INSN_CPCMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpne_w_C3, "CPCMPNE_W_C3", MEPCOP1_32_INSN_CPCMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpgtu_b_C3, "CPCMPGTU_B_C3", MEPCOP1_32_INSN_CPCMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpgt_b_C3, "CPCMPGT_B_C3", MEPCOP1_32_INSN_CPCMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpgt_h_C3, "CPCMPGT_H_C3", MEPCOP1_32_INSN_CPCMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpgtu_w_C3, "CPCMPGTU_W_C3", MEPCOP1_32_INSN_CPCMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpgt_w_C3, "CPCMPGT_W_C3", MEPCOP1_32_INSN_CPCMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpgeu_b_C3, "CPCMPGEU_B_C3", MEPCOP1_32_INSN_CPCMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpge_b_C3, "CPCMPGE_B_C3", MEPCOP1_32_INSN_CPCMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpge_h_C3, "CPCMPGE_H_C3", MEPCOP1_32_INSN_CPCMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpgeu_w_C3, "CPCMPGEU_W_C3", MEPCOP1_32_INSN_CPCMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpcmpge_w_C3, "CPCMPGE_W_C3", MEPCOP1_32_INSN_CPCMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpeq_b_C3, "CPACMPEQ_B_C3", MEPCOP1_32_INSN_CPACMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpeq_h_C3, "CPACMPEQ_H_C3", MEPCOP1_32_INSN_CPACMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpeq_w_C3, "CPACMPEQ_W_C3", MEPCOP1_32_INSN_CPACMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpne_b_C3, "CPACMPNE_B_C3", MEPCOP1_32_INSN_CPACMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpne_h_C3, "CPACMPNE_H_C3", MEPCOP1_32_INSN_CPACMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpne_w_C3, "CPACMPNE_W_C3", MEPCOP1_32_INSN_CPACMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpgtu_b_C3, "CPACMPGTU_B_C3", MEPCOP1_32_INSN_CPACMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpgt_b_C3, "CPACMPGT_B_C3", MEPCOP1_32_INSN_CPACMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpgt_h_C3, "CPACMPGT_H_C3", MEPCOP1_32_INSN_CPACMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpgtu_w_C3, "CPACMPGTU_W_C3", MEPCOP1_32_INSN_CPACMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpgt_w_C3, "CPACMPGT_W_C3", MEPCOP1_32_INSN_CPACMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpgeu_b_C3, "CPACMPGEU_B_C3", MEPCOP1_32_INSN_CPACMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpge_b_C3, "CPACMPGE_B_C3", MEPCOP1_32_INSN_CPACMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpge_h_C3, "CPACMPGE_H_C3", MEPCOP1_32_INSN_CPACMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpgeu_w_C3, "CPACMPGEU_W_C3", MEPCOP1_32_INSN_CPACMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpacmpge_w_C3, "CPACMPGE_W_C3", MEPCOP1_32_INSN_CPACMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpeq_b_C3, "CPOCMPEQ_B_C3", MEPCOP1_32_INSN_CPOCMPEQ_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpeq_h_C3, "CPOCMPEQ_H_C3", MEPCOP1_32_INSN_CPOCMPEQ_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpeq_w_C3, "CPOCMPEQ_W_C3", MEPCOP1_32_INSN_CPOCMPEQ_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpne_b_C3, "CPOCMPNE_B_C3", MEPCOP1_32_INSN_CPOCMPNE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpne_h_C3, "CPOCMPNE_H_C3", MEPCOP1_32_INSN_CPOCMPNE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpne_w_C3, "CPOCMPNE_W_C3", MEPCOP1_32_INSN_CPOCMPNE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpgtu_b_C3, "CPOCMPGTU_B_C3", MEPCOP1_32_INSN_CPOCMPGTU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpgt_b_C3, "CPOCMPGT_B_C3", MEPCOP1_32_INSN_CPOCMPGT_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpgt_h_C3, "CPOCMPGT_H_C3", MEPCOP1_32_INSN_CPOCMPGT_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpgtu_w_C3, "CPOCMPGTU_W_C3", MEPCOP1_32_INSN_CPOCMPGTU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpgt_w_C3, "CPOCMPGT_W_C3", MEPCOP1_32_INSN_CPOCMPGT_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpgeu_b_C3, "CPOCMPGEU_B_C3", MEPCOP1_32_INSN_CPOCMPGEU_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpge_b_C3, "CPOCMPGE_B_C3", MEPCOP1_32_INSN_CPOCMPGE_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpge_h_C3, "CPOCMPGE_H_C3", MEPCOP1_32_INSN_CPOCMPGE_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpgeu_w_C3, "CPOCMPGEU_W_C3", MEPCOP1_32_INSN_CPOCMPGEU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpocmpge_w_C3, "CPOCMPGE_W_C3", MEPCOP1_32_INSN_CPOCMPGE_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrli3_b_C3, "CPSRLI3_B_C3", MEPCOP1_32_INSN_CPSRLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrli3_h_C3, "CPSRLI3_H_C3", MEPCOP1_32_INSN_CPSRLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrli3_w_C3, "CPSRLI3_W_C3", MEPCOP1_32_INSN_CPSRLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdsrli3_C3, "CDSRLI3_C3", MEPCOP1_32_INSN_CDSRLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrai3_b_C3, "CPSRAI3_B_C3", MEPCOP1_32_INSN_CPSRAI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrai3_h_C3, "CPSRAI3_H_C3", MEPCOP1_32_INSN_CPSRAI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrai3_w_C3, "CPSRAI3_W_C3", MEPCOP1_32_INSN_CPSRAI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdsrai3_C3, "CDSRAI3_C3", MEPCOP1_32_INSN_CDSRAI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpslli3_b_C3, "CPSLLI3_B_C3", MEPCOP1_32_INSN_CPSLLI3_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpslli3_h_C3, "CPSLLI3_H_C3", MEPCOP1_32_INSN_CPSLLI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpslli3_w_C3, "CPSLLI3_W_C3", MEPCOP1_32_INSN_CPSLLI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdslli3_C3, "CDSLLI3_C3", MEPCOP1_32_INSN_CDSLLI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpslai3_h_C3, "CPSLAI3_H_C3", MEPCOP1_32_INSN_CPSLAI3_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpslai3_w_C3, "CPSLAI3_W_C3", MEPCOP1_32_INSN_CPSLAI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpclipiu3_w_C3, "CPCLIPIU3_W_C3", MEPCOP1_32_INSN_CPCLIPIU3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpclipi3_w_C3, "CPCLIPI3_W_C3", MEPCOP1_32_INSN_CPCLIPI3_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdclipiu3_C3, "CDCLIPIU3_C3", MEPCOP1_32_INSN_CDCLIPIU3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdclipi3_C3, "CDCLIPI3_C3", MEPCOP1_32_INSN_CDCLIPI3_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovi_b_C3, "CPMOVI_B_C3", MEPCOP1_32_INSN_CPMOVI_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmoviu_h_C3, "CPMOVIU_H_C3", MEPCOP1_32_INSN_CPMOVIU_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovi_h_C3, "CPMOVI_H_C3", MEPCOP1_32_INSN_CPMOVI_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmoviu_w_C3, "CPMOVIU_W_C3", MEPCOP1_32_INSN_CPMOVIU_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovi_w_C3, "CPMOVI_W_C3", MEPCOP1_32_INSN_CPMOVI_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdmoviu_C3, "CDMOVIU_C3", MEPCOP1_32_INSN_CDMOVIU_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cdmovi_C3, "CDMOVI_C3", MEPCOP1_32_INSN_CDMOVI_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpadda1u_b_C3, "CPADDA1U_B_C3", MEPCOP1_32_INSN_CPADDA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpadda1_b_C3, "CPADDA1_B_C3", MEPCOP1_32_INSN_CPADDA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddua1_h_C3, "CPADDUA1_H_C3", MEPCOP1_32_INSN_CPADDUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddla1_h_C3, "CPADDLA1_H_C3", MEPCOP1_32_INSN_CPADDLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddaca1u_b_C3, "CPADDACA1U_B_C3", MEPCOP1_32_INSN_CPADDACA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddaca1_b_C3, "CPADDACA1_B_C3", MEPCOP1_32_INSN_CPADDACA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddacua1_h_C3, "CPADDACUA1_H_C3", MEPCOP1_32_INSN_CPADDACUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpaddacla1_h_C3, "CPADDACLA1_H_C3", MEPCOP1_32_INSN_CPADDACLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsuba1u_b_C3, "CPSUBA1U_B_C3", MEPCOP1_32_INSN_CPSUBA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsuba1_b_C3, "CPSUBA1_B_C3", MEPCOP1_32_INSN_CPSUBA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsubua1_h_C3, "CPSUBUA1_H_C3", MEPCOP1_32_INSN_CPSUBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsubla1_h_C3, "CPSUBLA1_H_C3", MEPCOP1_32_INSN_CPSUBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsubaca1u_b_C3, "CPSUBACA1U_B_C3", MEPCOP1_32_INSN_CPSUBACA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsubaca1_b_C3, "CPSUBACA1_B_C3", MEPCOP1_32_INSN_CPSUBACA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsubacua1_h_C3, "CPSUBACUA1_H_C3", MEPCOP1_32_INSN_CPSUBACUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsubacla1_h_C3, "CPSUBACLA1_H_C3", MEPCOP1_32_INSN_CPSUBACLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsa1u_b_C3, "CPABSA1U_B_C3", MEPCOP1_32_INSN_CPABSA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsa1_b_C3, "CPABSA1_B_C3", MEPCOP1_32_INSN_CPABSA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsua1_h_C3, "CPABSUA1_H_C3", MEPCOP1_32_INSN_CPABSUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpabsla1_h_C3, "CPABSLA1_H_C3", MEPCOP1_32_INSN_CPABSLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsada1u_b_C3, "CPSADA1U_B_C3", MEPCOP1_32_INSN_CPSADA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsada1_b_C3, "CPSADA1_B_C3", MEPCOP1_32_INSN_CPSADA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsadua1_h_C3, "CPSADUA1_H_C3", MEPCOP1_32_INSN_CPSADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsadla1_h_C3, "CPSADLA1_H_C3", MEPCOP1_32_INSN_CPSADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpseta1_h_C3, "CPSETA1_H_C3", MEPCOP1_32_INSN_CPSETA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsetua1_w_C3, "CPSETUA1_W_C3", MEPCOP1_32_INSN_CPSETUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsetla1_w_C3, "CPSETLA1_W_C3", MEPCOP1_32_INSN_CPSETLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmova1_b_C3, "CPMOVA1_B_C3", MEPCOP1_32_INSN_CPMOVA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovua1_h_C3, "CPMOVUA1_H_C3", MEPCOP1_32_INSN_CPMOVUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovla1_h_C3, "CPMOVLA1_H_C3", MEPCOP1_32_INSN_CPMOVLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovuua1_w_C3, "CPMOVUUA1_W_C3", MEPCOP1_32_INSN_CPMOVUUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovula1_w_C3, "CPMOVULA1_W_C3", MEPCOP1_32_INSN_CPMOVULA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovlua1_w_C3, "CPMOVLUA1_W_C3", MEPCOP1_32_INSN_CPMOVLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovlla1_w_C3, "CPMOVLLA1_W_C3", MEPCOP1_32_INSN_CPMOVLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppacka1u_b_C3, "CPPACKA1U_B_C3", MEPCOP1_32_INSN_CPPACKA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppacka1_b_C3, "CPPACKA1_B_C3", MEPCOP1_32_INSN_CPPACKA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppackua1_h_C3, "CPPACKUA1_H_C3", MEPCOP1_32_INSN_CPPACKUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppackla1_h_C3, "CPPACKLA1_H_C3", MEPCOP1_32_INSN_CPPACKLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppackua1_w_C3, "CPPACKUA1_W_C3", MEPCOP1_32_INSN_CPPACKUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cppackla1_w_C3, "CPPACKLA1_W_C3", MEPCOP1_32_INSN_CPPACKLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovhua1_w_C3, "CPMOVHUA1_W_C3", MEPCOP1_32_INSN_CPMOVHUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmovhla1_w_C3, "CPMOVHLA1_W_C3", MEPCOP1_32_INSN_CPMOVHLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrla1_C3, "CPSRLA1_C3", MEPCOP1_32_INSN_CPSRLA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsraa1_C3, "CPSRAA1_C3", MEPCOP1_32_INSN_CPSRAA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpslla1_C3, "CPSLLA1_C3", MEPCOP1_32_INSN_CPSLLA1_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsrlia1_P1, "CPSRLIA1_P1", MEPCOP1_32_INSN_CPSRLIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsraia1_P1, "CPSRAIA1_P1", MEPCOP1_32_INSN_CPSRAIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsllia1_P1, "CPSLLIA1_P1", MEPCOP1_32_INSN_CPSLLIA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssqa1u_b_C3, "CPSSQA1U_B_C3", MEPCOP1_32_INSN_CPSSQA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssqa1_b_C3, "CPSSQA1_B_C3", MEPCOP1_32_INSN_CPSSQA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssda1u_b_C3, "CPSSDA1U_B_C3", MEPCOP1_32_INSN_CPSSDA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpssda1_b_C3, "CPSSDA1_B_C3", MEPCOP1_32_INSN_CPSSDA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmula1u_b_C3, "CPMULA1U_B_C3", MEPCOP1_32_INSN_CPMULA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmula1_b_C3, "CPMULA1_B_C3", MEPCOP1_32_INSN_CPMULA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulua1_h_C3, "CPMULUA1_H_C3", MEPCOP1_32_INSN_CPMULUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulla1_h_C3, "CPMULLA1_H_C3", MEPCOP1_32_INSN_CPMULLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulua1u_w_C3, "CPMULUA1U_W_C3", MEPCOP1_32_INSN_CPMULUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulla1u_w_C3, "CPMULLA1U_W_C3", MEPCOP1_32_INSN_CPMULLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulua1_w_C3, "CPMULUA1_W_C3", MEPCOP1_32_INSN_CPMULUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulla1_w_C3, "CPMULLA1_W_C3", MEPCOP1_32_INSN_CPMULLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmada1u_b_C3, "CPMADA1U_B_C3", MEPCOP1_32_INSN_CPMADA1U_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmada1_b_C3, "CPMADA1_B_C3", MEPCOP1_32_INSN_CPMADA1_B_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmadua1_h_C3, "CPMADUA1_H_C3", MEPCOP1_32_INSN_CPMADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmadla1_h_C3, "CPMADLA1_H_C3", MEPCOP1_32_INSN_CPMADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmadua1u_w_C3, "CPMADUA1U_W_C3", MEPCOP1_32_INSN_CPMADUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmadla1u_w_C3, "CPMADLA1U_W_C3", MEPCOP1_32_INSN_CPMADLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmadua1_w_C3, "CPMADUA1_W_C3", MEPCOP1_32_INSN_CPMADUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmadla1_w_C3, "CPMADLA1_W_C3", MEPCOP1_32_INSN_CPMADLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmsbua1_h_C3, "CPMSBUA1_H_C3", MEPCOP1_32_INSN_CPMSBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmsbla1_h_C3, "CPMSBLA1_H_C3", MEPCOP1_32_INSN_CPMSBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmsbua1u_w_C3, "CPMSBUA1U_W_C3", MEPCOP1_32_INSN_CPMSBUA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmsbla1u_w_C3, "CPMSBLA1U_W_C3", MEPCOP1_32_INSN_CPMSBLA1U_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmsbua1_w_C3, "CPMSBUA1_W_C3", MEPCOP1_32_INSN_CPMSBUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmsbla1_w_C3, "CPMSBLA1_W_C3", MEPCOP1_32_INSN_CPMSBLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadua1_h_C3, "CPSMADUA1_H_C3", MEPCOP1_32_INSN_CPSMADUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadla1_h_C3, "CPSMADLA1_H_C3", MEPCOP1_32_INSN_CPSMADLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadua1_w_C3, "CPSMADUA1_W_C3", MEPCOP1_32_INSN_CPSMADUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadla1_w_C3, "CPSMADLA1_W_C3", MEPCOP1_32_INSN_CPSMADLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbua1_h_C3, "CPSMSBUA1_H_C3", MEPCOP1_32_INSN_CPSMSBUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbla1_h_C3, "CPSMSBLA1_H_C3", MEPCOP1_32_INSN_CPSMSBLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbua1_w_C3, "CPSMSBUA1_W_C3", MEPCOP1_32_INSN_CPSMSBUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbla1_w_C3, "CPSMSBLA1_W_C3", MEPCOP1_32_INSN_CPSMSBLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulslua1_h_C3, "CPMULSLUA1_H_C3", MEPCOP1_32_INSN_CPMULSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulslla1_h_C3, "CPMULSLLA1_H_C3", MEPCOP1_32_INSN_CPMULSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulslua1_w_C3, "CPMULSLUA1_W_C3", MEPCOP1_32_INSN_CPMULSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpmulslla1_w_C3, "CPMULSLLA1_W_C3", MEPCOP1_32_INSN_CPMULSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadslua1_h_C3, "CPSMADSLUA1_H_C3", MEPCOP1_32_INSN_CPSMADSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadslla1_h_C3, "CPSMADSLLA1_H_C3", MEPCOP1_32_INSN_CPSMADSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadslua1_w_C3, "CPSMADSLUA1_W_C3", MEPCOP1_32_INSN_CPSMADSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmadslla1_w_C3, "CPSMADSLLA1_W_C3", MEPCOP1_32_INSN_CPSMADSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbslua1_h_C3, "CPSMSBSLUA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbslla1_h_C3, "CPSMSBSLLA1_H_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbslua1_w_C3, "CPSMSBSLUA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
+ { mepcop1_32_sem_cpsmsbslla1_w_C3, "CPSMSBSLLA1_W_C3", MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x10" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_C3) } },
};
@@ -350,6 +350,8 @@ mepcop1_32_extract_sfmt_cpadd3_b_C3 (mep
static void
mepcop1_32_extract_sfmt_cpfsftbi_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
static void
+mepcop1_32_extract_sfmt_cpssub3_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
mepcop1_32_extract_sfmt_cpmovfrcsar0_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
static void
mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
@@ -372,6 +374,20 @@ mepcop1_32_extract_sfmt_cpmovi_b_C3 (mep
static void
mepcop1_32_extract_sfmt_cpmoviu_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
static void
+mepcop1_32_extract_sfmt_cpadda1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
+mepcop1_32_extract_sfmt_cpsrla1_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
+static void
mepcop1_32_extract_sfmt_cpsrlia1_P1 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn);
// Fetch & decode instruction
@@ -402,35 +418,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf0070001)
- { itype = MEPCOP1_32_INSN_CPADDA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf0170001)
- { itype = MEPCOP1_32_INSN_CPADDA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf0470001)
- { itype = MEPCOP1_32_INSN_CPADDACA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDACA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf0570001)
- { itype = MEPCOP1_32_INSN_CPADDACA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDACA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfffff801) == 0xf0870001)
- { itype = MEPCOP1_32_INSN_CPSUBA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfffff801) == 0xf0970001)
- { itype = MEPCOP1_32_INSN_CPSUBA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfffff801) == 0xf0c70001)
- { itype = MEPCOP1_32_INSN_CPSUBACA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBACA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfffff801) == 0xf0d70001)
- { itype = MEPCOP1_32_INSN_CPSUBACA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBACA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -449,35 +465,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf0070801)
- { itype = MEPCOP1_32_INSN_CPSSQA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSSQA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf0170801)
- { itype = MEPCOP1_32_INSN_CPSSQA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSSQA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf0470801)
- { itype = MEPCOP1_32_INSN_CPSSDA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSSDA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf0570801)
- { itype = MEPCOP1_32_INSN_CPSSDA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSSDA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfffff801) == 0xf0870801)
- { itype = MEPCOP1_32_INSN_CPMULA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfffff801) == 0xf0970801)
- { itype = MEPCOP1_32_INSN_CPMULA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfffff801) == 0xf0c70801)
- { itype = MEPCOP1_32_INSN_CPMULUA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULUA1U_W_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfffff801) == 0xf0d70801)
- { itype = MEPCOP1_32_INSN_CPMULLA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULLA1U_W_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -496,11 +512,11 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff83f) == 0xf0071001)
- { itype = MEPCOP1_32_INSN_CPSRLA1_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSRLA1_C3; mepcop1_32_extract_sfmt_cpsrla1_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff83f) == 0xf0171001)
- { itype = MEPCOP1_32_INSN_CPSRAA1_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSRAA1_C3; mepcop1_32_extract_sfmt_cpsrla1_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1097,35 +1113,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf0270001)
- { itype = MEPCOP1_32_INSN_CPADDUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf0370001)
- { itype = MEPCOP1_32_INSN_CPADDLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf0670001)
- { itype = MEPCOP1_32_INSN_CPADDACUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDACUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf0770001)
- { itype = MEPCOP1_32_INSN_CPADDACLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPADDACLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfffff801) == 0xf0a70001)
- { itype = MEPCOP1_32_INSN_CPSUBUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfffff801) == 0xf0b70001)
- { itype = MEPCOP1_32_INSN_CPSUBLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfffff801) == 0xf0e70001)
- { itype = MEPCOP1_32_INSN_CPSUBACUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBACUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfffff801) == 0xf0f70001)
- { itype = MEPCOP1_32_INSN_CPSUBACLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSUBACLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1137,26 +1153,26 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf0a70801)
- { itype = MEPCOP1_32_INSN_CPMULUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf0b70801)
- { itype = MEPCOP1_32_INSN_CPMULLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf0e70801)
- { itype = MEPCOP1_32_INSN_CPMULUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULUA1_W_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf0f70801)
- { itype = MEPCOP1_32_INSN_CPMULLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULLA1_W_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
}
case 69 :
if ((entire_insn & 0xfffff83f) == 0xf0271001)
- { itype = MEPCOP1_32_INSN_CPSLLA1_C3; mepcop1_32_extract_sfmt_cpmovtocsar0_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSLLA1_C3; mepcop1_32_extract_sfmt_cpsrla1_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 96 : /* fall through */
case 160 : /* fall through */
@@ -1203,19 +1219,19 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf1070001)
- { itype = MEPCOP1_32_INSN_CPABSA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPABSA1U_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf1170001)
- { itype = MEPCOP1_32_INSN_CPABSA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPABSA1_B_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf1470001)
- { itype = MEPCOP1_32_INSN_CPSADA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSADA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf1570001)
- { itype = MEPCOP1_32_INSN_CPSADA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSADA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1227,27 +1243,27 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf1070801)
- { itype = MEPCOP1_32_INSN_CPMADA1U_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADA1U_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf1170801)
- { itype = MEPCOP1_32_INSN_CPMADA1_B_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADA1_B_C3; mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf1470801)
- { itype = MEPCOP1_32_INSN_CPMADUA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADUA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf1570801)
- { itype = MEPCOP1_32_INSN_CPMADLA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADLA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfffff801) == 0xf1c70801)
- { itype = MEPCOP1_32_INSN_CPMSBUA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMSBUA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfffff801) == 0xf1d70801)
- { itype = MEPCOP1_32_INSN_CPMSBLA1U_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMSBLA1U_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1299,19 +1315,19 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf1270001)
- { itype = MEPCOP1_32_INSN_CPABSUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPABSUA1_H_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf1370001)
- { itype = MEPCOP1_32_INSN_CPABSLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPABSLA1_H_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf1670001)
- { itype = MEPCOP1_32_INSN_CPSADUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSADUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf1770001)
- { itype = MEPCOP1_32_INSN_CPSADLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSADLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1323,35 +1339,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf1270801)
- { itype = MEPCOP1_32_INSN_CPMADUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf1370801)
- { itype = MEPCOP1_32_INSN_CPMADLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf1670801)
- { itype = MEPCOP1_32_INSN_CPMADUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf1770801)
- { itype = MEPCOP1_32_INSN_CPMADLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMADLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfffff801) == 0xf1a70801)
- { itype = MEPCOP1_32_INSN_CPMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfffff801) == 0xf1b70801)
- { itype = MEPCOP1_32_INSN_CPMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfffff801) == 0xf1e70801)
- { itype = MEPCOP1_32_INSN_CPMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfffff801) == 0xf1f70801)
- { itype = MEPCOP1_32_INSN_CPMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1381,7 +1397,7 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 257 :
if ((entire_insn & 0xfffff801) == 0xf2070001)
- { itype = MEPCOP1_32_INSN_CPSETA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSETA1_H_C3; mepcop1_32_extract_sfmt_cpadda1u_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 258 : /* fall through */
case 322 : /* fall through */
@@ -1484,11 +1500,11 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf2270001)
- { itype = MEPCOP1_32_INSN_CPSETUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSETUA1_W_C3; mepcop1_32_extract_sfmt_cpaddua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf2370001)
- { itype = MEPCOP1_32_INSN_CPSETLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSETLA1_W_C3; mepcop1_32_extract_sfmt_cpaddla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1556,35 +1572,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf3270801)
- { itype = MEPCOP1_32_INSN_CPSMADUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf3370801)
- { itype = MEPCOP1_32_INSN_CPSMADLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf3670801)
- { itype = MEPCOP1_32_INSN_CPSMADUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf3770801)
- { itype = MEPCOP1_32_INSN_CPSMADLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfffff801) == 0xf3a70801)
- { itype = MEPCOP1_32_INSN_CPSMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfffff801) == 0xf3b70801)
- { itype = MEPCOP1_32_INSN_CPSMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfffff801) == 0xf3e70801)
- { itype = MEPCOP1_32_INSN_CPSMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfffff801) == 0xf3f70801)
- { itype = MEPCOP1_32_INSN_CPSMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1779,19 +1795,19 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf4a70801)
- { itype = MEPCOP1_32_INSN_CPMULSLUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULSLUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf4b70801)
- { itype = MEPCOP1_32_INSN_CPMULSLLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULSLLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf4e70801)
- { itype = MEPCOP1_32_INSN_CPMULSLUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULSLUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf4f70801)
- { itype = MEPCOP1_32_INSN_CPMULSLLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPMULSLLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1945,35 +1961,35 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfffff801) == 0xf7270801)
- { itype = MEPCOP1_32_INSN_CPSMADSLUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADSLUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfffff801) == 0xf7370801)
- { itype = MEPCOP1_32_INSN_CPSMADSLLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADSLLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfffff801) == 0xf7670801)
- { itype = MEPCOP1_32_INSN_CPSMADSLUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADSLUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfffff801) == 0xf7770801)
- { itype = MEPCOP1_32_INSN_CPSMADSLLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMADSLLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfffff801) == 0xf7a70801)
- { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_H_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfffff801) == 0xf7b70801)
- { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_H_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfffff801) == 0xf7e70801)
- { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBSLUA1_W_C3; mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfffff801) == 0xf7f70801)
- { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3; mepcop1_32_extract_sfmt_cpcmpeqz_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSMSBSLLA1_W_C3; mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2245,7 +2261,7 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
case 1680 : /* fall through */
case 1744 :
if ((entire_insn & 0xfe0ff801) == 0xfc074000)
- { itype = MEPCOP1_32_INSN_CPSSUB3_H_C3; mepcop1_32_extract_sfmt_cpadd3_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSSUB3_H_C3; mepcop1_32_extract_sfmt_cpssub3_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1554 : /* fall through */
case 1618 : /* fall through */
@@ -2331,7 +2347,7 @@ mepcop1_32_scache::decode (mep_ext1_cpu*
case 1936 : /* fall through */
case 2000 :
if ((entire_insn & 0xfe0ff801) == 0xfe074000)
- { itype = MEPCOP1_32_INSN_CPSSUB3_W_C3; mepcop1_32_extract_sfmt_cpadd3_b_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_32_INSN_CPSSUB3_W_C3; mepcop1_32_extract_sfmt_cpssub3_h_C3 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_32_INSN_X_INVALID; mepcop1_32_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1810 : /* fall through */
case 1874 : /* fall through */
@@ -2591,6 +2607,39 @@ mepcop1_32_extract_sfmt_cpfsftbi_C3 (mep
}
void
+mepcop1_32_extract_sfmt_cpssub3_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfsftbi_C3.f
+ UINT f_ivc2_5u7;
+ UINT f_ivc2_5u21;
+ UINT f_ivc2_5u26;
+
+ f_ivc2_5u7 = EXTRACT_MSB0_UINT (insn, 32, 7, 5);
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+ f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u26) = f_ivc2_5u26;
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ FLD (f_ivc2_5u7) = f_ivc2_5u7;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpssub3_h_C3)\t"
+ << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << " f_ivc2_5u7:0x" << hex << f_ivc2_5u7 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
mepcop1_32_extract_sfmt_cpmovfrcsar0_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
mepcop1_32_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cpfsftbi_C3.f
@@ -2914,6 +2963,205 @@ mepcop1_32_extract_sfmt_cpmoviu_h_C3 (me
}
void
+mepcop1_32_extract_sfmt_cpadda1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+ UINT f_ivc2_5u21;
+ UINT f_ivc2_5u26;
+
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+ f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u26) = f_ivc2_5u26;
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpadda1u_b_C3)\t"
+ << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+ UINT f_ivc2_5u21;
+ UINT f_ivc2_5u26;
+
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+ f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u26) = f_ivc2_5u26;
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddua1_h_C3)\t"
+ << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+ UINT f_ivc2_5u21;
+ UINT f_ivc2_5u26;
+
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+ f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u26) = f_ivc2_5u26;
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddla1_h_C3)\t"
+ << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddaca1u_b_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+ UINT f_ivc2_5u21;
+ UINT f_ivc2_5u26;
+
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+ f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u26) = f_ivc2_5u26;
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddaca1u_b_C3)\t"
+ << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddacua1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+ UINT f_ivc2_5u21;
+ UINT f_ivc2_5u26;
+
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+ f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u26) = f_ivc2_5u26;
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddacua1_h_C3)\t"
+ << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpaddacla1_h_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+ UINT f_ivc2_5u21;
+ UINT f_ivc2_5u26;
+
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+ f_ivc2_5u26 = EXTRACT_MSB0_UINT (insn, 32, 26, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u26) = f_ivc2_5u26;
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddacla1_h_C3)\t"
+ << " f_ivc2_5u26:0x" << hex << f_ivc2_5u26 << dec
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_32_extract_sfmt_cpsrla1_C3 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
+ mepcop1_32_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpmoviu_h_C3.f
+ UINT f_ivc2_5u21;
+
+ f_ivc2_5u21 = EXTRACT_MSB0_UINT (insn, 32, 21, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u21) = f_ivc2_5u21;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpsrla1_C3)\t"
+ << " f_ivc2_5u21:0x" << hex << f_ivc2_5u21 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
mepcop1_32_extract_sfmt_cpsrlia1_P1 (mepcop1_32_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_32_insn_word base_insn, mepcop1_32_insn_word entire_insn){
mepcop1_32_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cpfsftbi_C3.f
Index: sid/component/cgen-cpu/mep/mep-cop1-32-sem.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-32-sem.cxx,v
retrieving revision 1.2
diff -p -U3 -r1.2 mep-cop1-32-sem.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-32-sem.cxx 27 May 2009 01:49:45 -0000 1.2
+++ sid/component/cgen-cpu/mep/mep-cop1-32-sem.cxx 24 Jun 2009 02:59:29 -0000
@@ -103,7 +103,7 @@ mepcop1_32_sem_cmovc_ccrn_rm (mep_ext1_c
PCADDR npc = pc + 4;
{
- DI opval = * FLD (i_rm);
+ SI opval = * FLD (i_rm);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "ccr-ivc2" << '[' << FLD (f_ivc2_ccrn_c3) << ']' << ":=0x" << hex << opval << dec << " ";
current_cpu->h_ccr_ivc2_set (FLD (f_ivc2_ccrn_c3), opval);
@@ -1551,6 +1551,12 @@ mepcop1_32_sem_cpssub3_h_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
{
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 4) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 4), opval);
+ }
+ {
DI opval = current_cpu->ivc2_cpssub3_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u7) << ']' << ":=0x" << hex << opval << dec << " ";
@@ -1578,6 +1584,12 @@ mepcop1_32_sem_cpssub3_w_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
{
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 4) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 4), opval);
+ }
+ {
DI opval = current_cpu->ivc2_cpssub3_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u7) << ']' << ":=0x" << hex << opval << dec << " ";
@@ -2858,7 +2870,12 @@ mepcop1_32_sem_cpccadd_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpccadd_b (pc, FLD (f_ivc2_5u21));
+ {
+ DI opval = current_cpu->ivc2_cpccadd_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)]);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr64_set (FLD (f_ivc2_5u21), opval);
+ }
}
current_cpu->done_insn (npc, status);
@@ -3393,6 +3410,12 @@ mepcop1_32_sem_cpcmpeqz_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeqz_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3415,6 +3438,12 @@ mepcop1_32_sem_cpcmpeq_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3437,6 +3466,12 @@ mepcop1_32_sem_cpcmpeq_h_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3459,6 +3494,12 @@ mepcop1_32_sem_cpcmpeq_w_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3481,6 +3522,12 @@ mepcop1_32_sem_cpcmpne_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3503,6 +3550,12 @@ mepcop1_32_sem_cpcmpne_h_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3525,6 +3578,12 @@ mepcop1_32_sem_cpcmpne_w_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3547,6 +3606,12 @@ mepcop1_32_sem_cpcmpgtu_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgtu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3569,6 +3634,12 @@ mepcop1_32_sem_cpcmpgt_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3591,6 +3662,12 @@ mepcop1_32_sem_cpcmpgt_h_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3613,6 +3690,12 @@ mepcop1_32_sem_cpcmpgtu_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgtu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3635,6 +3718,12 @@ mepcop1_32_sem_cpcmpgt_w_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3657,6 +3746,12 @@ mepcop1_32_sem_cpcmpgeu_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgeu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3679,6 +3774,12 @@ mepcop1_32_sem_cpcmpge_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3701,6 +3802,12 @@ mepcop1_32_sem_cpcmpge_h_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3723,6 +3830,12 @@ mepcop1_32_sem_cpcmpgeu_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgeu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3745,6 +3858,12 @@ mepcop1_32_sem_cpcmpge_w_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3767,6 +3886,12 @@ mepcop1_32_sem_cpacmpeq_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpeq_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3789,6 +3914,12 @@ mepcop1_32_sem_cpacmpeq_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpeq_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3811,6 +3942,12 @@ mepcop1_32_sem_cpacmpeq_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpeq_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3833,6 +3970,12 @@ mepcop1_32_sem_cpacmpne_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpne_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3855,6 +3998,12 @@ mepcop1_32_sem_cpacmpne_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpne_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3877,6 +4026,12 @@ mepcop1_32_sem_cpacmpne_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpne_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3899,6 +4054,12 @@ mepcop1_32_sem_cpacmpgtu_b_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpgtu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3921,6 +4082,12 @@ mepcop1_32_sem_cpacmpgt_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpgt_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3943,6 +4110,12 @@ mepcop1_32_sem_cpacmpgt_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpgt_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3965,6 +4138,12 @@ mepcop1_32_sem_cpacmpgtu_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpgtu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -3987,6 +4166,12 @@ mepcop1_32_sem_cpacmpgt_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpgt_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4009,6 +4194,12 @@ mepcop1_32_sem_cpacmpgeu_b_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpgeu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4031,6 +4222,12 @@ mepcop1_32_sem_cpacmpge_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpge_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4053,6 +4250,12 @@ mepcop1_32_sem_cpacmpge_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpge_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4075,6 +4278,12 @@ mepcop1_32_sem_cpacmpgeu_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpgeu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4097,6 +4306,12 @@ mepcop1_32_sem_cpacmpge_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpacmpge_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4119,6 +4334,12 @@ mepcop1_32_sem_cpocmpeq_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpeq_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4141,6 +4362,12 @@ mepcop1_32_sem_cpocmpeq_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpeq_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4163,6 +4390,12 @@ mepcop1_32_sem_cpocmpeq_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpeq_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4185,6 +4418,12 @@ mepcop1_32_sem_cpocmpne_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpne_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4207,6 +4446,12 @@ mepcop1_32_sem_cpocmpne_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpne_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4229,6 +4474,12 @@ mepcop1_32_sem_cpocmpne_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpne_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4251,6 +4502,12 @@ mepcop1_32_sem_cpocmpgtu_b_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpgtu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4273,6 +4530,12 @@ mepcop1_32_sem_cpocmpgt_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpgt_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4295,6 +4558,12 @@ mepcop1_32_sem_cpocmpgt_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpgt_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4317,6 +4586,12 @@ mepcop1_32_sem_cpocmpgtu_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpgtu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4339,6 +4614,12 @@ mepcop1_32_sem_cpocmpgt_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpgt_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4361,6 +4642,12 @@ mepcop1_32_sem_cpocmpgeu_b_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpgeu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4383,6 +4670,12 @@ mepcop1_32_sem_cpocmpge_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpge_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4405,6 +4698,12 @@ mepcop1_32_sem_cpocmpge_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpge_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4427,6 +4726,12 @@ mepcop1_32_sem_cpocmpgeu_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpgeu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -4449,6 +4754,12 @@ mepcop1_32_sem_cpocmpge_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpocmpge_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5146,6 +5457,54 @@ mepcop1_32_sem_cpadda1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpadda1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5168,6 +5527,54 @@ mepcop1_32_sem_cpadda1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpadda1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5190,6 +5597,30 @@ mepcop1_32_sem_cpaddua1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpaddua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5212,6 +5643,30 @@ mepcop1_32_sem_cpaddla1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpaddla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5234,32 +5689,140 @@ mepcop1_32_sem_cpaddaca1u_b_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpaddaca1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
-}
-
- current_cpu->done_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** cpaddaca1_b_C3: cpaddaca1.b $crqc,$crpc
-
-sem_status
-mepcop1_32_sem_cpaddaca1_b_C3 (mep_ext1_cpu* current_cpu, mepcop1_32_scache* sem)
-{
-#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
- sem_status status = SEM_STATUS_NORMAL;
- mepcop1_32_scache* abuf = sem;
- unsigned long long written = 0;
- PCADDR pc = abuf->addr;
- PCADDR npc = pc + 4;
-
-{
-current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpaddaca1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
-}
-
- current_cpu->done_insn (npc, status);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
+current_cpu->ivc2_cpaddaca1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** cpaddaca1_b_C3: cpaddaca1.b $crqc,$crpc
+
+sem_status
+mepcop1_32_sem_cpaddaca1_b_C3 (mep_ext1_cpu* current_cpu, mepcop1_32_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_cdsrli3_C3.f
+ sem_status status = SEM_STATUS_NORMAL;
+ mepcop1_32_scache* abuf = sem;
+ unsigned long long written = 0;
+ PCADDR pc = abuf->addr;
+ PCADDR npc = pc + 4;
+
+{
+current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
+current_cpu->ivc2_cpaddaca1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
+}
+
+ current_cpu->done_insn (npc, status);
return status;
#undef FLD
}
@@ -5278,6 +5841,36 @@ mepcop1_32_sem_cpaddacua1_h_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpaddacua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5300,6 +5893,36 @@ mepcop1_32_sem_cpaddacla1_h_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpaddacla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5322,6 +5945,54 @@ mepcop1_32_sem_cpsuba1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsuba1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5344,6 +6015,54 @@ mepcop1_32_sem_cpsuba1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsuba1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5366,6 +6085,30 @@ mepcop1_32_sem_cpsubua1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsubua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5388,6 +6131,30 @@ mepcop1_32_sem_cpsubla1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpsubla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5410,6 +6177,60 @@ mepcop1_32_sem_cpsubaca1u_b_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubaca1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5432,6 +6253,60 @@ mepcop1_32_sem_cpsubaca1_b_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubaca1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5454,6 +6329,36 @@ mepcop1_32_sem_cpsubacua1_h_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubacua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5476,6 +6381,36 @@ mepcop1_32_sem_cpsubacla1_h_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubacla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5498,6 +6433,54 @@ mepcop1_32_sem_cpabsa1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpabsa1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5520,6 +6503,54 @@ mepcop1_32_sem_cpabsa1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpabsa1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5542,6 +6573,30 @@ mepcop1_32_sem_cpabsua1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpabsua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5564,6 +6619,30 @@ mepcop1_32_sem_cpabsla1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpabsla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5586,6 +6665,60 @@ mepcop1_32_sem_cpsada1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsada1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5608,6 +6741,60 @@ mepcop1_32_sem_cpsada1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsada1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5630,6 +6817,36 @@ mepcop1_32_sem_cpsadua1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsadua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5652,6 +6869,36 @@ mepcop1_32_sem_cpsadla1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsadla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5674,6 +6921,54 @@ mepcop1_32_sem_cpseta1_h_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpseta1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5696,6 +6991,30 @@ mepcop1_32_sem_cpsetua1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsetua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -5718,6 +7037,30 @@ mepcop1_32_sem_cpsetla1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpsetla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6145,6 +7488,54 @@ mepcop1_32_sem_cpsrla1_C3 (mep_ext1_cpu*
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsrla1 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)]);
}
@@ -6167,6 +7558,54 @@ mepcop1_32_sem_cpsraa1_C3 (mep_ext1_cpu*
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsraa1 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)]);
}
@@ -6189,6 +7628,54 @@ mepcop1_32_sem_cpslla1_C3 (mep_ext1_cpu*
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpslla1 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)]);
}
@@ -6211,6 +7698,54 @@ mepcop1_32_sem_cpsrlia1_P1 (mep_ext1_cpu
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsrlia1 (pc, FLD (f_ivc2_5u7));
}
@@ -6233,6 +7768,54 @@ mepcop1_32_sem_cpsraia1_P1 (mep_ext1_cpu
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsraia1 (pc, FLD (f_ivc2_5u7));
}
@@ -6255,6 +7838,54 @@ mepcop1_32_sem_cpsllia1_P1 (mep_ext1_cpu
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsllia1 (pc, FLD (f_ivc2_5u7));
}
@@ -6277,6 +7908,54 @@ mepcop1_32_sem_cpssqa1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpssqa1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6299,6 +7978,54 @@ mepcop1_32_sem_cpssqa1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpssqa1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6321,6 +8048,60 @@ mepcop1_32_sem_cpssda1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpssda1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6343,6 +8124,60 @@ mepcop1_32_sem_cpssda1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpssda1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6365,6 +8200,54 @@ mepcop1_32_sem_cpmula1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmula1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6387,6 +8270,54 @@ mepcop1_32_sem_cpmula1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmula1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6409,6 +8340,30 @@ mepcop1_32_sem_cpmulua1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmulua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6431,6 +8386,30 @@ mepcop1_32_sem_cpmulla1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpmulla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6453,6 +8432,30 @@ mepcop1_32_sem_cpmulua1u_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmulua1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6475,6 +8478,30 @@ mepcop1_32_sem_cpmulla1u_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpmulla1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6497,6 +8524,30 @@ mepcop1_32_sem_cpmulua1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmulua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6519,6 +8570,30 @@ mepcop1_32_sem_cpmulla1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpmulla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6541,6 +8616,60 @@ mepcop1_32_sem_cpmada1u_b_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmada1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6563,6 +8692,60 @@ mepcop1_32_sem_cpmada1_b_C3 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmada1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6585,6 +8768,36 @@ mepcop1_32_sem_cpmadua1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6607,6 +8820,36 @@ mepcop1_32_sem_cpmadla1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6629,6 +8872,36 @@ mepcop1_32_sem_cpmadua1u_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadua1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6651,6 +8924,36 @@ mepcop1_32_sem_cpmadla1u_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadla1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6673,6 +8976,36 @@ mepcop1_32_sem_cpmadua1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6695,6 +9028,36 @@ mepcop1_32_sem_cpmadla1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6717,6 +9080,36 @@ mepcop1_32_sem_cpmsbua1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6739,6 +9132,36 @@ mepcop1_32_sem_cpmsbla1_h_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6761,6 +9184,36 @@ mepcop1_32_sem_cpmsbua1u_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbua1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6783,6 +9236,36 @@ mepcop1_32_sem_cpmsbla1u_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbla1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6805,6 +9288,36 @@ mepcop1_32_sem_cpmsbua1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6827,6 +9340,36 @@ mepcop1_32_sem_cpmsbla1_w_C3 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6849,6 +9392,36 @@ mepcop1_32_sem_cpsmadua1_h_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6871,6 +9444,36 @@ mepcop1_32_sem_cpsmadla1_h_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6893,6 +9496,36 @@ mepcop1_32_sem_cpsmadua1_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6915,6 +9548,36 @@ mepcop1_32_sem_cpsmadla1_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6937,6 +9600,36 @@ mepcop1_32_sem_cpsmsbua1_h_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6959,6 +9652,36 @@ mepcop1_32_sem_cpsmsbla1_h_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -6981,6 +9704,36 @@ mepcop1_32_sem_cpsmsbua1_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7003,6 +9756,36 @@ mepcop1_32_sem_cpsmsbla1_w_C3 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7025,6 +9808,36 @@ mepcop1_32_sem_cpmulslua1_h_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7047,6 +9860,36 @@ mepcop1_32_sem_cpmulslla1_h_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7069,6 +9912,36 @@ mepcop1_32_sem_cpmulslua1_w_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7091,6 +9964,36 @@ mepcop1_32_sem_cpmulslla1_w_C3 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7113,6 +10016,36 @@ mepcop1_32_sem_cpsmadslua1_h_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7135,6 +10068,36 @@ mepcop1_32_sem_cpsmadslla1_h_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7157,6 +10120,36 @@ mepcop1_32_sem_cpsmadslua1_w_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7179,6 +10172,36 @@ mepcop1_32_sem_cpsmadslla1_w_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7201,6 +10224,36 @@ mepcop1_32_sem_cpsmsbslua1_h_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7223,6 +10276,36 @@ mepcop1_32_sem_cpsmsbslla1_h_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7245,6 +10328,36 @@ mepcop1_32_sem_cpsmsbslua1_w_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
@@ -7267,6 +10380,36 @@ mepcop1_32_sem_cpsmsbslla1_w_C3 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u21)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u26)]);
}
Index: sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx,v
retrieving revision 1.1
diff -p -U3 -r1.1 mep-cop1-48-decode.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx 30 Apr 2009 21:18:37 -0000 1.1
+++ sid/component/cgen-cpu/mep/mep-cop1-48-decode.cxx 24 Jun 2009 02:59:29 -0000
@@ -22,138 +22,138 @@ using namespace mep_ext1; // FIXME: name
mepcop1_48_idesc mepcop1_48_idesc::idesc_table[MEPCOP1_48_INSN_CDMOVI_P0_P1 + 1] =
{
- { mepcop1_48_sem_x_invalid, "X_INVALID", MEPCOP1_48_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x8" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcop1_48_sem_cmov_crn_rm_p0, "CMOV_CRN_RM_P0", MEPCOP1_48_INSN_CMOV_CRN_RM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
- { mepcop1_48_sem_cmov_rn_crm_p0, "CMOV_RN_CRM_P0", MEPCOP1_48_INSN_CMOV_RN_CRM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
- { mepcop1_48_sem_cmovc_ccrn_rm_p0, "CMOVC_CCRN_RM_P0", MEPCOP1_48_INSN_CMOVC_CCRN_RM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
- { mepcop1_48_sem_cmovc_rn_ccrm_p0, "CMOVC_RN_CCRM_P0", MEPCOP1_48_INSN_CMOVC_RN_CCRM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
- { mepcop1_48_sem_cmovh_crn_rm_p0, "CMOVH_CRN_RM_P0", MEPCOP1_48_INSN_CMOVH_CRN_RM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
- { mepcop1_48_sem_cmovh_rn_crm_p0, "CMOVH_RN_CRM_P0", MEPCOP1_48_INSN_CMOVH_RN_CRM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
- { mepcop1_48_sem_c0nop_P0_P0S, "C0NOP_P0_P0S", MEPCOP1_48_INSN_C0NOP_P0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x28" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P0S) } },
- { mepcop1_48_sem_cpfsftbi_P0_P1, "CPFSFTBI_P0_P1", MEPCOP1_48_INSN_CPFSFTBI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpeq_b_P0_P1, "CPACMPEQ_B_P0_P1", MEPCOP1_48_INSN_CPACMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpeq_h_P0_P1, "CPACMPEQ_H_P0_P1", MEPCOP1_48_INSN_CPACMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpeq_w_P0_P1, "CPACMPEQ_W_P0_P1", MEPCOP1_48_INSN_CPACMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpne_b_P0_P1, "CPACMPNE_B_P0_P1", MEPCOP1_48_INSN_CPACMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpne_h_P0_P1, "CPACMPNE_H_P0_P1", MEPCOP1_48_INSN_CPACMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpne_w_P0_P1, "CPACMPNE_W_P0_P1", MEPCOP1_48_INSN_CPACMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpgtu_b_P0_P1, "CPACMPGTU_B_P0_P1", MEPCOP1_48_INSN_CPACMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpgt_b_P0_P1, "CPACMPGT_B_P0_P1", MEPCOP1_48_INSN_CPACMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpgt_h_P0_P1, "CPACMPGT_H_P0_P1", MEPCOP1_48_INSN_CPACMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpgtu_w_P0_P1, "CPACMPGTU_W_P0_P1", MEPCOP1_48_INSN_CPACMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpgt_w_P0_P1, "CPACMPGT_W_P0_P1", MEPCOP1_48_INSN_CPACMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpgeu_b_P0_P1, "CPACMPGEU_B_P0_P1", MEPCOP1_48_INSN_CPACMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpge_b_P0_P1, "CPACMPGE_B_P0_P1", MEPCOP1_48_INSN_CPACMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpge_h_P0_P1, "CPACMPGE_H_P0_P1", MEPCOP1_48_INSN_CPACMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpgeu_w_P0_P1, "CPACMPGEU_W_P0_P1", MEPCOP1_48_INSN_CPACMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpacmpge_w_P0_P1, "CPACMPGE_W_P0_P1", MEPCOP1_48_INSN_CPACMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpeq_b_P0_P1, "CPOCMPEQ_B_P0_P1", MEPCOP1_48_INSN_CPOCMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpeq_h_P0_P1, "CPOCMPEQ_H_P0_P1", MEPCOP1_48_INSN_CPOCMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpeq_w_P0_P1, "CPOCMPEQ_W_P0_P1", MEPCOP1_48_INSN_CPOCMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpne_b_P0_P1, "CPOCMPNE_B_P0_P1", MEPCOP1_48_INSN_CPOCMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpne_h_P0_P1, "CPOCMPNE_H_P0_P1", MEPCOP1_48_INSN_CPOCMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpne_w_P0_P1, "CPOCMPNE_W_P0_P1", MEPCOP1_48_INSN_CPOCMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpgtu_b_P0_P1, "CPOCMPGTU_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpgt_b_P0_P1, "CPOCMPGT_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpgt_h_P0_P1, "CPOCMPGT_H_P0_P1", MEPCOP1_48_INSN_CPOCMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpgtu_w_P0_P1, "CPOCMPGTU_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpgt_w_P0_P1, "CPOCMPGT_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpgeu_b_P0_P1, "CPOCMPGEU_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpge_b_P0_P1, "CPOCMPGE_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpge_h_P0_P1, "CPOCMPGE_H_P0_P1", MEPCOP1_48_INSN_CPOCMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpgeu_w_P0_P1, "CPOCMPGEU_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpocmpge_w_P0_P1, "CPOCMPGE_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdadd3_P0_P1, "CDADD3_P0_P1", MEPCOP1_48_INSN_CDADD3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsub3_b_P0_P1, "CPSUB3_B_P0_P1", MEPCOP1_48_INSN_CPSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsub3_h_P0_P1, "CPSUB3_H_P0_P1", MEPCOP1_48_INSN_CPSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsub3_w_P0_P1, "CPSUB3_W_P0_P1", MEPCOP1_48_INSN_CPSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdsub3_P0_P1, "CDSUB3_P0_P1", MEPCOP1_48_INSN_CDSUB3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsadd3_h_P0_P1, "CPSADD3_H_P0_P1", MEPCOP1_48_INSN_CPSADD3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsadd3_w_P0_P1, "CPSADD3_W_P0_P1", MEPCOP1_48_INSN_CPSADD3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssub3_h_P0_P1, "CPSSUB3_H_P0_P1", MEPCOP1_48_INSN_CPSSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssub3_w_P0_P1, "CPSSUB3_W_P0_P1", MEPCOP1_48_INSN_CPSSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextuaddu3_b_P0_P1, "CPEXTUADDU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextuadd3_b_P0_P1, "CPEXTUADD3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextladdu3_b_P0_P1, "CPEXTLADDU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextladd3_b_P0_P1, "CPEXTLADD3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextusubu3_b_P0_P1, "CPEXTUSUBU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextusub3_b_P0_P1, "CPEXTUSUB3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextlsubu3_b_P0_P1, "CPEXTLSUBU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpextlsub3_b_P0_P1, "CPEXTLSUB3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpaveu3_b_P0_P1, "CPAVEU3_B_P0_P1", MEPCOP1_48_INSN_CPAVEU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpave3_b_P0_P1, "CPAVE3_B_P0_P1", MEPCOP1_48_INSN_CPAVE3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpave3_h_P0_P1, "CPAVE3_H_P0_P1", MEPCOP1_48_INSN_CPAVE3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpave3_w_P0_P1, "CPAVE3_W_P0_P1", MEPCOP1_48_INSN_CPAVE3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpaddsru3_b_P0_P1, "CPADDSRU3_B_P0_P1", MEPCOP1_48_INSN_CPADDSRU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpaddsr3_b_P0_P1, "CPADDSR3_B_P0_P1", MEPCOP1_48_INSN_CPADDSR3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpaddsr3_h_P0_P1, "CPADDSR3_H_P0_P1", MEPCOP1_48_INSN_CPADDSR3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpaddsr3_w_P0_P1, "CPADDSR3_W_P0_P1", MEPCOP1_48_INSN_CPADDSR3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpabsu3_b_P0_P1, "CPABSU3_B_P0_P1", MEPCOP1_48_INSN_CPABSU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpabs3_b_P0_P1, "CPABS3_B_P0_P1", MEPCOP1_48_INSN_CPABS3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpabs3_h_P0_P1, "CPABS3_H_P0_P1", MEPCOP1_48_INSN_CPABS3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpand3_P0_P1, "CPAND3_P0_P1", MEPCOP1_48_INSN_CPAND3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpor3_P0_P1, "CPOR3_P0_P1", MEPCOP1_48_INSN_CPOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpnor3_P0_P1, "CPNOR3_P0_P1", MEPCOP1_48_INSN_CPNOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpxor3_P0_P1, "CPXOR3_P0_P1", MEPCOP1_48_INSN_CPXOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cppacku_b_P0_P1, "CPPACKU_B_P0_P1", MEPCOP1_48_INSN_CPPACKU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cppack_b_P0_P1, "CPPACK_B_P0_P1", MEPCOP1_48_INSN_CPPACK_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cppack_h_P0_P1, "CPPACK_H_P0_P1", MEPCOP1_48_INSN_CPPACK_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmaxu3_b_P0_P1, "CPMAXU3_B_P0_P1", MEPCOP1_48_INSN_CPMAXU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmax3_b_P0_P1, "CPMAX3_B_P0_P1", MEPCOP1_48_INSN_CPMAX3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmax3_h_P0_P1, "CPMAX3_H_P0_P1", MEPCOP1_48_INSN_CPMAX3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmaxu3_w_P0_P1, "CPMAXU3_W_P0_P1", MEPCOP1_48_INSN_CPMAXU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmax3_w_P0_P1, "CPMAX3_W_P0_P1", MEPCOP1_48_INSN_CPMAX3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpminu3_b_P0_P1, "CPMINU3_B_P0_P1", MEPCOP1_48_INSN_CPMINU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmin3_b_P0_P1, "CPMIN3_B_P0_P1", MEPCOP1_48_INSN_CPMIN3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmin3_h_P0_P1, "CPMIN3_H_P0_P1", MEPCOP1_48_INSN_CPMIN3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpminu3_w_P0_P1, "CPMINU3_W_P0_P1", MEPCOP1_48_INSN_CPMINU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmin3_w_P0_P1, "CPMIN3_W_P0_P1", MEPCOP1_48_INSN_CPMIN3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrl3_b_P0_P1, "CPSRL3_B_P0_P1", MEPCOP1_48_INSN_CPSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssrl3_b_P0_P1, "CPSSRL3_B_P0_P1", MEPCOP1_48_INSN_CPSSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrl3_h_P0_P1, "CPSRL3_H_P0_P1", MEPCOP1_48_INSN_CPSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssrl3_h_P0_P1, "CPSSRL3_H_P0_P1", MEPCOP1_48_INSN_CPSSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrl3_w_P0_P1, "CPSRL3_W_P0_P1", MEPCOP1_48_INSN_CPSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssrl3_w_P0_P1, "CPSSRL3_W_P0_P1", MEPCOP1_48_INSN_CPSSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdsrl3_P0_P1, "CDSRL3_P0_P1", MEPCOP1_48_INSN_CDSRL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsra3_b_P0_P1, "CPSRA3_B_P0_P1", MEPCOP1_48_INSN_CPSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssra3_b_P0_P1, "CPSSRA3_B_P0_P1", MEPCOP1_48_INSN_CPSSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsra3_h_P0_P1, "CPSRA3_H_P0_P1", MEPCOP1_48_INSN_CPSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssra3_h_P0_P1, "CPSSRA3_H_P0_P1", MEPCOP1_48_INSN_CPSSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsra3_w_P0_P1, "CPSRA3_W_P0_P1", MEPCOP1_48_INSN_CPSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssra3_w_P0_P1, "CPSSRA3_W_P0_P1", MEPCOP1_48_INSN_CPSSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdsra3_P0_P1, "CDSRA3_P0_P1", MEPCOP1_48_INSN_CDSRA3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsll3_b_P0_P1, "CPSLL3_B_P0_P1", MEPCOP1_48_INSN_CPSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssll3_b_P0_P1, "CPSSLL3_B_P0_P1", MEPCOP1_48_INSN_CPSSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsll3_h_P0_P1, "CPSLL3_H_P0_P1", MEPCOP1_48_INSN_CPSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssll3_h_P0_P1, "CPSSLL3_H_P0_P1", MEPCOP1_48_INSN_CPSSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsll3_w_P0_P1, "CPSLL3_W_P0_P1", MEPCOP1_48_INSN_CPSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpssll3_w_P0_P1, "CPSSLL3_W_P0_P1", MEPCOP1_48_INSN_CPSSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdsll3_P0_P1, "CDSLL3_P0_P1", MEPCOP1_48_INSN_CDSLL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsla3_h_P0_P1, "CPSLA3_H_P0_P1", MEPCOP1_48_INSN_CPSLA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsla3_w_P0_P1, "CPSLA3_W_P0_P1", MEPCOP1_48_INSN_CPSLA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrli3_b_P0_P1, "CPSRLI3_B_P0_P1", MEPCOP1_48_INSN_CPSRLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrli3_h_P0_P1, "CPSRLI3_H_P0_P1", MEPCOP1_48_INSN_CPSRLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrli3_w_P0_P1, "CPSRLI3_W_P0_P1", MEPCOP1_48_INSN_CPSRLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdsrli3_P0_P1, "CDSRLI3_P0_P1", MEPCOP1_48_INSN_CDSRLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrai3_b_P0_P1, "CPSRAI3_B_P0_P1", MEPCOP1_48_INSN_CPSRAI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrai3_h_P0_P1, "CPSRAI3_H_P0_P1", MEPCOP1_48_INSN_CPSRAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpsrai3_w_P0_P1, "CPSRAI3_W_P0_P1", MEPCOP1_48_INSN_CPSRAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdsrai3_P0_P1, "CDSRAI3_P0_P1", MEPCOP1_48_INSN_CDSRAI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpslli3_b_P0_P1, "CPSLLI3_B_P0_P1", MEPCOP1_48_INSN_CPSLLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpslli3_h_P0_P1, "CPSLLI3_H_P0_P1", MEPCOP1_48_INSN_CPSLLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpslli3_w_P0_P1, "CPSLLI3_W_P0_P1", MEPCOP1_48_INSN_CPSLLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdslli3_P0_P1, "CDSLLI3_P0_P1", MEPCOP1_48_INSN_CDSLLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpslai3_h_P0_P1, "CPSLAI3_H_P0_P1", MEPCOP1_48_INSN_CPSLAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpslai3_w_P0_P1, "CPSLAI3_W_P0_P1", MEPCOP1_48_INSN_CPSLAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpclipiu3_w_P0_P1, "CPCLIPIU3_W_P0_P1", MEPCOP1_48_INSN_CPCLIPIU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpclipi3_w_P0_P1, "CPCLIPI3_W_P0_P1", MEPCOP1_48_INSN_CPCLIPI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdclipiu3_P0_P1, "CDCLIPIU3_P0_P1", MEPCOP1_48_INSN_CDCLIPIU3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdclipi3_P0_P1, "CDCLIPI3_P0_P1", MEPCOP1_48_INSN_CDCLIPI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmovi_h_P0_P1, "CPMOVI_H_P0_P1", MEPCOP1_48_INSN_CPMOVI_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmoviu_w_P0_P1, "CPMOVIU_W_P0_P1", MEPCOP1_48_INSN_CPMOVIU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cpmovi_w_P0_P1, "CPMOVI_W_P0_P1", MEPCOP1_48_INSN_CPMOVI_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdmoviu_P0_P1, "CDMOVIU_P0_P1", MEPCOP1_48_INSN_CDMOVIU_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_48_sem_cdmovi_P0_P1, "CDMOVI_P0_P1", MEPCOP1_48_INSN_CDMOVI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_x_invalid, "X_INVALID", MEPCOP1_48_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x8" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcop1_48_sem_cmov_crn_rm_p0, "CMOV_CRN_RM_P0", MEPCOP1_48_INSN_CMOV_CRN_RM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
+ { mepcop1_48_sem_cmov_rn_crm_p0, "CMOV_RN_CRM_P0", MEPCOP1_48_INSN_CMOV_RN_CRM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
+ { mepcop1_48_sem_cmovc_ccrn_rm_p0, "CMOVC_CCRN_RM_P0", MEPCOP1_48_INSN_CMOVC_CCRN_RM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
+ { mepcop1_48_sem_cmovc_rn_ccrm_p0, "CMOVC_RN_CCRM_P0", MEPCOP1_48_INSN_CMOVC_RN_CCRM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
+ { mepcop1_48_sem_cmovh_crn_rm_p0, "CMOVH_CRN_RM_P0", MEPCOP1_48_INSN_CMOVH_CRN_RM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
+ { mepcop1_48_sem_cmovh_rn_crm_p0, "CMOVH_RN_CRM_P0", MEPCOP1_48_INSN_CMOVH_RN_CRM_P0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x8" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0) } },
+ { mepcop1_48_sem_c0nop_P0_P0S, "C0NOP_P0_P0S", MEPCOP1_48_INSN_C0NOP_P0_P0S, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x28" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P0S) } },
+ { mepcop1_48_sem_cpfsftbi_P0_P1, "CPFSFTBI_P0_P1", MEPCOP1_48_INSN_CPFSFTBI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpeq_b_P0_P1, "CPACMPEQ_B_P0_P1", MEPCOP1_48_INSN_CPACMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpeq_h_P0_P1, "CPACMPEQ_H_P0_P1", MEPCOP1_48_INSN_CPACMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpeq_w_P0_P1, "CPACMPEQ_W_P0_P1", MEPCOP1_48_INSN_CPACMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpne_b_P0_P1, "CPACMPNE_B_P0_P1", MEPCOP1_48_INSN_CPACMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpne_h_P0_P1, "CPACMPNE_H_P0_P1", MEPCOP1_48_INSN_CPACMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpne_w_P0_P1, "CPACMPNE_W_P0_P1", MEPCOP1_48_INSN_CPACMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpgtu_b_P0_P1, "CPACMPGTU_B_P0_P1", MEPCOP1_48_INSN_CPACMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpgt_b_P0_P1, "CPACMPGT_B_P0_P1", MEPCOP1_48_INSN_CPACMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpgt_h_P0_P1, "CPACMPGT_H_P0_P1", MEPCOP1_48_INSN_CPACMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpgtu_w_P0_P1, "CPACMPGTU_W_P0_P1", MEPCOP1_48_INSN_CPACMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpgt_w_P0_P1, "CPACMPGT_W_P0_P1", MEPCOP1_48_INSN_CPACMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpgeu_b_P0_P1, "CPACMPGEU_B_P0_P1", MEPCOP1_48_INSN_CPACMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpge_b_P0_P1, "CPACMPGE_B_P0_P1", MEPCOP1_48_INSN_CPACMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpge_h_P0_P1, "CPACMPGE_H_P0_P1", MEPCOP1_48_INSN_CPACMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpgeu_w_P0_P1, "CPACMPGEU_W_P0_P1", MEPCOP1_48_INSN_CPACMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpacmpge_w_P0_P1, "CPACMPGE_W_P0_P1", MEPCOP1_48_INSN_CPACMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpeq_b_P0_P1, "CPOCMPEQ_B_P0_P1", MEPCOP1_48_INSN_CPOCMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpeq_h_P0_P1, "CPOCMPEQ_H_P0_P1", MEPCOP1_48_INSN_CPOCMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpeq_w_P0_P1, "CPOCMPEQ_W_P0_P1", MEPCOP1_48_INSN_CPOCMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpne_b_P0_P1, "CPOCMPNE_B_P0_P1", MEPCOP1_48_INSN_CPOCMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpne_h_P0_P1, "CPOCMPNE_H_P0_P1", MEPCOP1_48_INSN_CPOCMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpne_w_P0_P1, "CPOCMPNE_W_P0_P1", MEPCOP1_48_INSN_CPOCMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpgtu_b_P0_P1, "CPOCMPGTU_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpgt_b_P0_P1, "CPOCMPGT_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpgt_h_P0_P1, "CPOCMPGT_H_P0_P1", MEPCOP1_48_INSN_CPOCMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpgtu_w_P0_P1, "CPOCMPGTU_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpgt_w_P0_P1, "CPOCMPGT_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpgeu_b_P0_P1, "CPOCMPGEU_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpge_b_P0_P1, "CPOCMPGE_B_P0_P1", MEPCOP1_48_INSN_CPOCMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpge_h_P0_P1, "CPOCMPGE_H_P0_P1", MEPCOP1_48_INSN_CPOCMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpgeu_w_P0_P1, "CPOCMPGEU_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpocmpge_w_P0_P1, "CPOCMPGE_W_P0_P1", MEPCOP1_48_INSN_CPOCMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdadd3_P0_P1, "CDADD3_P0_P1", MEPCOP1_48_INSN_CDADD3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsub3_b_P0_P1, "CPSUB3_B_P0_P1", MEPCOP1_48_INSN_CPSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsub3_h_P0_P1, "CPSUB3_H_P0_P1", MEPCOP1_48_INSN_CPSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsub3_w_P0_P1, "CPSUB3_W_P0_P1", MEPCOP1_48_INSN_CPSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdsub3_P0_P1, "CDSUB3_P0_P1", MEPCOP1_48_INSN_CDSUB3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsadd3_h_P0_P1, "CPSADD3_H_P0_P1", MEPCOP1_48_INSN_CPSADD3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsadd3_w_P0_P1, "CPSADD3_W_P0_P1", MEPCOP1_48_INSN_CPSADD3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssub3_h_P0_P1, "CPSSUB3_H_P0_P1", MEPCOP1_48_INSN_CPSSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssub3_w_P0_P1, "CPSSUB3_W_P0_P1", MEPCOP1_48_INSN_CPSSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextuaddu3_b_P0_P1, "CPEXTUADDU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextuadd3_b_P0_P1, "CPEXTUADD3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextladdu3_b_P0_P1, "CPEXTLADDU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextladd3_b_P0_P1, "CPEXTLADD3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextusubu3_b_P0_P1, "CPEXTUSUBU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextusub3_b_P0_P1, "CPEXTUSUB3_B_P0_P1", MEPCOP1_48_INSN_CPEXTUSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextlsubu3_b_P0_P1, "CPEXTLSUBU3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpextlsub3_b_P0_P1, "CPEXTLSUB3_B_P0_P1", MEPCOP1_48_INSN_CPEXTLSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpaveu3_b_P0_P1, "CPAVEU3_B_P0_P1", MEPCOP1_48_INSN_CPAVEU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpave3_b_P0_P1, "CPAVE3_B_P0_P1", MEPCOP1_48_INSN_CPAVE3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpave3_h_P0_P1, "CPAVE3_H_P0_P1", MEPCOP1_48_INSN_CPAVE3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpave3_w_P0_P1, "CPAVE3_W_P0_P1", MEPCOP1_48_INSN_CPAVE3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpaddsru3_b_P0_P1, "CPADDSRU3_B_P0_P1", MEPCOP1_48_INSN_CPADDSRU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpaddsr3_b_P0_P1, "CPADDSR3_B_P0_P1", MEPCOP1_48_INSN_CPADDSR3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpaddsr3_h_P0_P1, "CPADDSR3_H_P0_P1", MEPCOP1_48_INSN_CPADDSR3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpaddsr3_w_P0_P1, "CPADDSR3_W_P0_P1", MEPCOP1_48_INSN_CPADDSR3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpabsu3_b_P0_P1, "CPABSU3_B_P0_P1", MEPCOP1_48_INSN_CPABSU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpabs3_b_P0_P1, "CPABS3_B_P0_P1", MEPCOP1_48_INSN_CPABS3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpabs3_h_P0_P1, "CPABS3_H_P0_P1", MEPCOP1_48_INSN_CPABS3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpand3_P0_P1, "CPAND3_P0_P1", MEPCOP1_48_INSN_CPAND3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpor3_P0_P1, "CPOR3_P0_P1", MEPCOP1_48_INSN_CPOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpnor3_P0_P1, "CPNOR3_P0_P1", MEPCOP1_48_INSN_CPNOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpxor3_P0_P1, "CPXOR3_P0_P1", MEPCOP1_48_INSN_CPXOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cppacku_b_P0_P1, "CPPACKU_B_P0_P1", MEPCOP1_48_INSN_CPPACKU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cppack_b_P0_P1, "CPPACK_B_P0_P1", MEPCOP1_48_INSN_CPPACK_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cppack_h_P0_P1, "CPPACK_H_P0_P1", MEPCOP1_48_INSN_CPPACK_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmaxu3_b_P0_P1, "CPMAXU3_B_P0_P1", MEPCOP1_48_INSN_CPMAXU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmax3_b_P0_P1, "CPMAX3_B_P0_P1", MEPCOP1_48_INSN_CPMAX3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmax3_h_P0_P1, "CPMAX3_H_P0_P1", MEPCOP1_48_INSN_CPMAX3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmaxu3_w_P0_P1, "CPMAXU3_W_P0_P1", MEPCOP1_48_INSN_CPMAXU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmax3_w_P0_P1, "CPMAX3_W_P0_P1", MEPCOP1_48_INSN_CPMAX3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpminu3_b_P0_P1, "CPMINU3_B_P0_P1", MEPCOP1_48_INSN_CPMINU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmin3_b_P0_P1, "CPMIN3_B_P0_P1", MEPCOP1_48_INSN_CPMIN3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmin3_h_P0_P1, "CPMIN3_H_P0_P1", MEPCOP1_48_INSN_CPMIN3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpminu3_w_P0_P1, "CPMINU3_W_P0_P1", MEPCOP1_48_INSN_CPMINU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmin3_w_P0_P1, "CPMIN3_W_P0_P1", MEPCOP1_48_INSN_CPMIN3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrl3_b_P0_P1, "CPSRL3_B_P0_P1", MEPCOP1_48_INSN_CPSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssrl3_b_P0_P1, "CPSSRL3_B_P0_P1", MEPCOP1_48_INSN_CPSSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrl3_h_P0_P1, "CPSRL3_H_P0_P1", MEPCOP1_48_INSN_CPSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssrl3_h_P0_P1, "CPSSRL3_H_P0_P1", MEPCOP1_48_INSN_CPSSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrl3_w_P0_P1, "CPSRL3_W_P0_P1", MEPCOP1_48_INSN_CPSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssrl3_w_P0_P1, "CPSSRL3_W_P0_P1", MEPCOP1_48_INSN_CPSSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdsrl3_P0_P1, "CDSRL3_P0_P1", MEPCOP1_48_INSN_CDSRL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsra3_b_P0_P1, "CPSRA3_B_P0_P1", MEPCOP1_48_INSN_CPSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssra3_b_P0_P1, "CPSSRA3_B_P0_P1", MEPCOP1_48_INSN_CPSSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsra3_h_P0_P1, "CPSRA3_H_P0_P1", MEPCOP1_48_INSN_CPSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssra3_h_P0_P1, "CPSSRA3_H_P0_P1", MEPCOP1_48_INSN_CPSSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsra3_w_P0_P1, "CPSRA3_W_P0_P1", MEPCOP1_48_INSN_CPSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssra3_w_P0_P1, "CPSSRA3_W_P0_P1", MEPCOP1_48_INSN_CPSSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdsra3_P0_P1, "CDSRA3_P0_P1", MEPCOP1_48_INSN_CDSRA3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsll3_b_P0_P1, "CPSLL3_B_P0_P1", MEPCOP1_48_INSN_CPSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssll3_b_P0_P1, "CPSSLL3_B_P0_P1", MEPCOP1_48_INSN_CPSSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsll3_h_P0_P1, "CPSLL3_H_P0_P1", MEPCOP1_48_INSN_CPSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssll3_h_P0_P1, "CPSSLL3_H_P0_P1", MEPCOP1_48_INSN_CPSSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsll3_w_P0_P1, "CPSLL3_W_P0_P1", MEPCOP1_48_INSN_CPSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpssll3_w_P0_P1, "CPSSLL3_W_P0_P1", MEPCOP1_48_INSN_CPSSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdsll3_P0_P1, "CDSLL3_P0_P1", MEPCOP1_48_INSN_CDSLL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsla3_h_P0_P1, "CPSLA3_H_P0_P1", MEPCOP1_48_INSN_CPSLA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsla3_w_P0_P1, "CPSLA3_W_P0_P1", MEPCOP1_48_INSN_CPSLA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrli3_b_P0_P1, "CPSRLI3_B_P0_P1", MEPCOP1_48_INSN_CPSRLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrli3_h_P0_P1, "CPSRLI3_H_P0_P1", MEPCOP1_48_INSN_CPSRLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrli3_w_P0_P1, "CPSRLI3_W_P0_P1", MEPCOP1_48_INSN_CPSRLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdsrli3_P0_P1, "CDSRLI3_P0_P1", MEPCOP1_48_INSN_CDSRLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrai3_b_P0_P1, "CPSRAI3_B_P0_P1", MEPCOP1_48_INSN_CPSRAI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrai3_h_P0_P1, "CPSRAI3_H_P0_P1", MEPCOP1_48_INSN_CPSRAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpsrai3_w_P0_P1, "CPSRAI3_W_P0_P1", MEPCOP1_48_INSN_CPSRAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdsrai3_P0_P1, "CDSRAI3_P0_P1", MEPCOP1_48_INSN_CDSRAI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpslli3_b_P0_P1, "CPSLLI3_B_P0_P1", MEPCOP1_48_INSN_CPSLLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpslli3_h_P0_P1, "CPSLLI3_H_P0_P1", MEPCOP1_48_INSN_CPSLLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpslli3_w_P0_P1, "CPSLLI3_W_P0_P1", MEPCOP1_48_INSN_CPSLLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdslli3_P0_P1, "CDSLLI3_P0_P1", MEPCOP1_48_INSN_CDSLLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpslai3_h_P0_P1, "CPSLAI3_H_P0_P1", MEPCOP1_48_INSN_CPSLAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpslai3_w_P0_P1, "CPSLAI3_W_P0_P1", MEPCOP1_48_INSN_CPSLAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpclipiu3_w_P0_P1, "CPCLIPIU3_W_P0_P1", MEPCOP1_48_INSN_CPCLIPIU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpclipi3_w_P0_P1, "CPCLIPI3_W_P0_P1", MEPCOP1_48_INSN_CPCLIPI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdclipiu3_P0_P1, "CDCLIPIU3_P0_P1", MEPCOP1_48_INSN_CDCLIPIU3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdclipi3_P0_P1, "CDCLIPI3_P0_P1", MEPCOP1_48_INSN_CDCLIPI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmovi_h_P0_P1, "CPMOVI_H_P0_P1", MEPCOP1_48_INSN_CPMOVI_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmoviu_w_P0_P1, "CPMOVIU_W_P0_P1", MEPCOP1_48_INSN_CPMOVIU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cpmovi_w_P0_P1, "CPMOVI_W_P0_P1", MEPCOP1_48_INSN_CPMOVI_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdmoviu_P0_P1, "CDMOVIU_P0_P1", MEPCOP1_48_INSN_CDMOVIU_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_48_sem_cdmovi_P0_P1, "CDMOVI_P0_P1", MEPCOP1_48_INSN_CDMOVI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
};
@@ -194,6 +194,8 @@ mepcop1_48_extract_sfmt_cpacmpeq_b_P0_P1
static void
mepcop1_48_extract_sfmt_cdadd3_P0_P1 (mepcop1_48_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_48_insn_word base_insn, mepcop1_48_insn_word entire_insn);
static void
+mepcop1_48_extract_sfmt_cpssub3_h_P0_P1 (mepcop1_48_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_48_insn_word base_insn, mepcop1_48_insn_word entire_insn);
+static void
mepcop1_48_extract_sfmt_cpsrli3_b_P0_P1 (mepcop1_48_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_48_insn_word base_insn, mepcop1_48_insn_word entire_insn);
static void
mepcop1_48_extract_sfmt_cpsrli3_h_P0_P1 (mepcop1_48_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_48_insn_word base_insn, mepcop1_48_insn_word entire_insn);
@@ -1177,11 +1179,11 @@ mepcop1_48_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_48_INSN_X_INVALID; mepcop1_48_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 228 :
if ((entire_insn & 0xfff8000f) == 0xea00000)
- { itype = MEPCOP1_48_INSN_CPSSUB3_H_P0_P1; mepcop1_48_extract_sfmt_cdadd3_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_48_INSN_CPSSUB3_H_P0_P1; mepcop1_48_extract_sfmt_cpssub3_h_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_48_INSN_X_INVALID; mepcop1_48_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 244 :
if ((entire_insn & 0xfff8000f) == 0xfa00000)
- { itype = MEPCOP1_48_INSN_CPSSUB3_W_P0_P1; mepcop1_48_extract_sfmt_cdadd3_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_48_INSN_CPSSUB3_W_P0_P1; mepcop1_48_extract_sfmt_cpssub3_h_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_48_INSN_X_INVALID; mepcop1_48_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 260 :
if ((entire_insn & 0xfff8000f) == 0x10a00000)
@@ -1748,6 +1750,39 @@ mepcop1_48_extract_sfmt_cdadd3_P0_P1 (me
}
void
+mepcop1_48_extract_sfmt_cpssub3_h_P0_P1 (mepcop1_48_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_48_insn_word base_insn, mepcop1_48_insn_word entire_insn){
+ mepcop1_48_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfsftbi_P0_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_5u23;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_5u23 = EXTRACT_MSB0_UINT (insn, 32, 23, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_5u23) = f_ivc2_5u23;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpssub3_h_P0_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_5u23:0x" << hex << f_ivc2_5u23 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
mepcop1_48_extract_sfmt_cpsrli3_b_P0_P1 (mepcop1_48_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_48_insn_word base_insn, mepcop1_48_insn_word entire_insn){
mepcop1_48_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cpfsftbi_P0_P1.f
Index: sid/component/cgen-cpu/mep/mep-cop1-48-sem.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-48-sem.cxx,v
retrieving revision 1.2
diff -p -U3 -r1.2 mep-cop1-48-sem.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-48-sem.cxx 27 May 2009 01:49:45 -0000 1.2
+++ sid/component/cgen-cpu/mep/mep-cop1-48-sem.cxx 24 Jun 2009 02:59:30 -0000
@@ -103,7 +103,7 @@ mepcop1_48_sem_cmovc_ccrn_rm_p0 (mep_ext
PCADDR npc = pc + 4;
{
- DI opval = * FLD (i_ivc2rm);
+ SI opval = * FLD (i_ivc2rm);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "ccr-ivc2" << '[' << FLD (f_ivc2_ccrn) << ']' << ":=0x" << hex << opval << dec << " ";
current_cpu->h_ccr_ivc2_set (FLD (f_ivc2_ccrn), opval);
@@ -1143,6 +1143,12 @@ mepcop1_48_sem_cpssub3_h_P0_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
{
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 4) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 4), opval);
+ }
+ {
DI opval = current_cpu->ivc2_cpssub3_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u23) << ']' << ":=0x" << hex << opval << dec << " ";
@@ -1170,6 +1176,12 @@ mepcop1_48_sem_cpssub3_w_P0_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
{
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 4) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 4), opval);
+ }
+ {
DI opval = current_cpu->ivc2_cpssub3_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u23) << ']' << ":=0x" << hex << opval << dec << " ";
Index: sid/component/cgen-cpu/mep/mep-cop1-64-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-64-decode.cxx,v
retrieving revision 1.2
diff -p -U3 -r1.2 mep-cop1-64-decode.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-64-decode.cxx 22 May 2009 17:37:44 -0000 1.2
+++ sid/component/cgen-cpu/mep/mep-cop1-64-decode.cxx 24 Jun 2009 02:59:30 -0000
@@ -22,329 +22,329 @@ using namespace mep_ext1; // FIXME: name
mepcop1_64_idesc mepcop1_64_idesc::idesc_table[MEPCOP1_64_INSN_CPSMSBSLLA1_W_P1 + 1] =
{
- { mepcop1_64_sem_x_invalid, "X_INVALID", MEPCOP1_64_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcop1_64_sem_cpadd3_b_P0S_P1, "CPADD3_B_P0S_P1", MEPCOP1_64_INSN_CPADD3_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpadd3_h_P0S_P1, "CPADD3_H_P0S_P1", MEPCOP1_64_INSN_CPADD3_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpadd3_w_P0S_P1, "CPADD3_W_P0S_P1", MEPCOP1_64_INSN_CPADD3_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpunpacku_b_P0S_P1, "CPUNPACKU_B_P0S_P1", MEPCOP1_64_INSN_CPUNPACKU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpunpacku_h_P0S_P1, "CPUNPACKU_H_P0S_P1", MEPCOP1_64_INSN_CPUNPACKU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpunpacku_w_P0S_P1, "CPUNPACKU_W_P0S_P1", MEPCOP1_64_INSN_CPUNPACKU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpunpackl_b_P0S_P1, "CPUNPACKL_B_P0S_P1", MEPCOP1_64_INSN_CPUNPACKL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpunpackl_h_P0S_P1, "CPUNPACKL_H_P0S_P1", MEPCOP1_64_INSN_CPUNPACKL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpunpackl_w_P0S_P1, "CPUNPACKL_W_P0S_P1", MEPCOP1_64_INSN_CPUNPACKL_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsel_P0S_P1, "CPSEL_P0S_P1", MEPCOP1_64_INSN_CPSEL_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfsftbs0_P0S_P1, "CPFSFTBS0_P0S_P1", MEPCOP1_64_INSN_CPFSFTBS0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfsftbs1_P0S_P1, "CPFSFTBS1_P0S_P1", MEPCOP1_64_INSN_CPFSFTBS1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmov_P0S_P1, "CPMOV_P0S_P1", MEPCOP1_64_INSN_CPMOV_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsz_b_P0S_P1, "CPABSZ_B_P0S_P1", MEPCOP1_64_INSN_CPABSZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsz_h_P0S_P1, "CPABSZ_H_P0S_P1", MEPCOP1_64_INSN_CPABSZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsz_w_P0S_P1, "CPABSZ_W_P0S_P1", MEPCOP1_64_INSN_CPABSZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpldz_h_P0S_P1, "CPLDZ_H_P0S_P1", MEPCOP1_64_INSN_CPLDZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpldz_w_P0S_P1, "CPLDZ_W_P0S_P1", MEPCOP1_64_INSN_CPLDZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpnorm_h_P0S_P1, "CPNORM_H_P0S_P1", MEPCOP1_64_INSN_CPNORM_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpnorm_w_P0S_P1, "CPNORM_W_P0S_P1", MEPCOP1_64_INSN_CPNORM_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cphaddu_b_P0S_P1, "CPHADDU_B_P0S_P1", MEPCOP1_64_INSN_CPHADDU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cphadd_b_P0S_P1, "CPHADD_B_P0S_P1", MEPCOP1_64_INSN_CPHADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cphadd_h_P0S_P1, "CPHADD_H_P0S_P1", MEPCOP1_64_INSN_CPHADD_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cphadd_w_P0S_P1, "CPHADD_W_P0S_P1", MEPCOP1_64_INSN_CPHADD_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpccadd_b_P0S_P1, "CPCCADD_B_P0S_P1", MEPCOP1_64_INSN_CPCCADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpbcast_b_P0S_P1, "CPBCAST_B_P0S_P1", MEPCOP1_64_INSN_CPBCAST_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpbcast_h_P0S_P1, "CPBCAST_H_P0S_P1", MEPCOP1_64_INSN_CPBCAST_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpbcast_w_P0S_P1, "CPBCAST_W_P0S_P1", MEPCOP1_64_INSN_CPBCAST_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextuu_b_P0S_P1, "CPEXTUU_B_P0S_P1", MEPCOP1_64_INSN_CPEXTUU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextu_b_P0S_P1, "CPEXTU_B_P0S_P1", MEPCOP1_64_INSN_CPEXTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextuu_h_P0S_P1, "CPEXTUU_H_P0S_P1", MEPCOP1_64_INSN_CPEXTUU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextu_h_P0S_P1, "CPEXTU_H_P0S_P1", MEPCOP1_64_INSN_CPEXTU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextlu_b_P0S_P1, "CPEXTLU_B_P0S_P1", MEPCOP1_64_INSN_CPEXTLU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextl_b_P0S_P1, "CPEXTL_B_P0S_P1", MEPCOP1_64_INSN_CPEXTL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextlu_h_P0S_P1, "CPEXTLU_H_P0S_P1", MEPCOP1_64_INSN_CPEXTLU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextl_h_P0S_P1, "CPEXTL_H_P0S_P1", MEPCOP1_64_INSN_CPEXTL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcastub_h_P0S_P1, "CPCASTUB_H_P0S_P1", MEPCOP1_64_INSN_CPCASTUB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcastb_h_P0S_P1, "CPCASTB_H_P0S_P1", MEPCOP1_64_INSN_CPCASTB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcastub_w_P0S_P1, "CPCASTUB_W_P0S_P1", MEPCOP1_64_INSN_CPCASTUB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcastb_w_P0S_P1, "CPCASTB_W_P0S_P1", MEPCOP1_64_INSN_CPCASTB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcastuh_w_P0S_P1, "CPCASTUH_W_P0S_P1", MEPCOP1_64_INSN_CPCASTUH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcasth_w_P0S_P1, "CPCASTH_W_P0S_P1", MEPCOP1_64_INSN_CPCASTH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdcastuw_P0S_P1, "CDCASTUW_P0S_P1", MEPCOP1_64_INSN_CDCASTUW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdcastw_P0S_P1, "CDCASTW_P0S_P1", MEPCOP1_64_INSN_CDCASTW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovfrcsar0_P0S_P1, "CPMOVFRCSAR0_P0S_P1", MEPCOP1_64_INSN_CPMOVFRCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovfrcsar1_P0S_P1, "CPMOVFRCSAR1_P0S_P1", MEPCOP1_64_INSN_CPMOVFRCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovfrcc_P0S_P1, "CPMOVFRCC_P0S_P1", MEPCOP1_64_INSN_CPMOVFRCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovtocsar0_P0S_P1, "CPMOVTOCSAR0_P0S_P1", MEPCOP1_64_INSN_CPMOVTOCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovtocsar1_P0S_P1, "CPMOVTOCSAR1_P0S_P1", MEPCOP1_64_INSN_CPMOVTOCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovtocc_P0S_P1, "CPMOVTOCC_P0S_P1", MEPCOP1_64_INSN_CPMOVTOCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpeqz_b_P0S_P1, "CPCMPEQZ_B_P0S_P1", MEPCOP1_64_INSN_CPCMPEQZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpeq_b_P0S_P1, "CPCMPEQ_B_P0S_P1", MEPCOP1_64_INSN_CPCMPEQ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpeq_h_P0S_P1, "CPCMPEQ_H_P0S_P1", MEPCOP1_64_INSN_CPCMPEQ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpeq_w_P0S_P1, "CPCMPEQ_W_P0S_P1", MEPCOP1_64_INSN_CPCMPEQ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpne_b_P0S_P1, "CPCMPNE_B_P0S_P1", MEPCOP1_64_INSN_CPCMPNE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpne_h_P0S_P1, "CPCMPNE_H_P0S_P1", MEPCOP1_64_INSN_CPCMPNE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpne_w_P0S_P1, "CPCMPNE_W_P0S_P1", MEPCOP1_64_INSN_CPCMPNE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpgtu_b_P0S_P1, "CPCMPGTU_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpgt_b_P0S_P1, "CPCMPGT_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGT_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpgt_h_P0S_P1, "CPCMPGT_H_P0S_P1", MEPCOP1_64_INSN_CPCMPGT_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpgtu_w_P0S_P1, "CPCMPGTU_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGTU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpgt_w_P0S_P1, "CPCMPGT_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGT_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpgeu_b_P0S_P1, "CPCMPGEU_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGEU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpge_b_P0S_P1, "CPCMPGE_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpge_h_P0S_P1, "CPCMPGE_H_P0S_P1", MEPCOP1_64_INSN_CPCMPGE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpgeu_w_P0S_P1, "CPCMPGEU_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGEU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpcmpge_w_P0S_P1, "CPCMPGE_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfsftbi_P0_P1, "CPFSFTBI_P0_P1", MEPCOP1_64_INSN_CPFSFTBI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpeq_b_P0_P1, "CPACMPEQ_B_P0_P1", MEPCOP1_64_INSN_CPACMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpeq_h_P0_P1, "CPACMPEQ_H_P0_P1", MEPCOP1_64_INSN_CPACMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpeq_w_P0_P1, "CPACMPEQ_W_P0_P1", MEPCOP1_64_INSN_CPACMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpne_b_P0_P1, "CPACMPNE_B_P0_P1", MEPCOP1_64_INSN_CPACMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpne_h_P0_P1, "CPACMPNE_H_P0_P1", MEPCOP1_64_INSN_CPACMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpne_w_P0_P1, "CPACMPNE_W_P0_P1", MEPCOP1_64_INSN_CPACMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpgtu_b_P0_P1, "CPACMPGTU_B_P0_P1", MEPCOP1_64_INSN_CPACMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpgt_b_P0_P1, "CPACMPGT_B_P0_P1", MEPCOP1_64_INSN_CPACMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpgt_h_P0_P1, "CPACMPGT_H_P0_P1", MEPCOP1_64_INSN_CPACMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpgtu_w_P0_P1, "CPACMPGTU_W_P0_P1", MEPCOP1_64_INSN_CPACMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpgt_w_P0_P1, "CPACMPGT_W_P0_P1", MEPCOP1_64_INSN_CPACMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpgeu_b_P0_P1, "CPACMPGEU_B_P0_P1", MEPCOP1_64_INSN_CPACMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpge_b_P0_P1, "CPACMPGE_B_P0_P1", MEPCOP1_64_INSN_CPACMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpge_h_P0_P1, "CPACMPGE_H_P0_P1", MEPCOP1_64_INSN_CPACMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpgeu_w_P0_P1, "CPACMPGEU_W_P0_P1", MEPCOP1_64_INSN_CPACMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacmpge_w_P0_P1, "CPACMPGE_W_P0_P1", MEPCOP1_64_INSN_CPACMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpeq_b_P0_P1, "CPOCMPEQ_B_P0_P1", MEPCOP1_64_INSN_CPOCMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpeq_h_P0_P1, "CPOCMPEQ_H_P0_P1", MEPCOP1_64_INSN_CPOCMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpeq_w_P0_P1, "CPOCMPEQ_W_P0_P1", MEPCOP1_64_INSN_CPOCMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpne_b_P0_P1, "CPOCMPNE_B_P0_P1", MEPCOP1_64_INSN_CPOCMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpne_h_P0_P1, "CPOCMPNE_H_P0_P1", MEPCOP1_64_INSN_CPOCMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpne_w_P0_P1, "CPOCMPNE_W_P0_P1", MEPCOP1_64_INSN_CPOCMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpgtu_b_P0_P1, "CPOCMPGTU_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpgt_b_P0_P1, "CPOCMPGT_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpgt_h_P0_P1, "CPOCMPGT_H_P0_P1", MEPCOP1_64_INSN_CPOCMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpgtu_w_P0_P1, "CPOCMPGTU_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpgt_w_P0_P1, "CPOCMPGT_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpgeu_b_P0_P1, "CPOCMPGEU_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpge_b_P0_P1, "CPOCMPGE_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpge_h_P0_P1, "CPOCMPGE_H_P0_P1", MEPCOP1_64_INSN_CPOCMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpgeu_w_P0_P1, "CPOCMPGEU_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpocmpge_w_P0_P1, "CPOCMPGE_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdadd3_P0_P1, "CDADD3_P0_P1", MEPCOP1_64_INSN_CDADD3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsub3_b_P0_P1, "CPSUB3_B_P0_P1", MEPCOP1_64_INSN_CPSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsub3_h_P0_P1, "CPSUB3_H_P0_P1", MEPCOP1_64_INSN_CPSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsub3_w_P0_P1, "CPSUB3_W_P0_P1", MEPCOP1_64_INSN_CPSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdsub3_P0_P1, "CDSUB3_P0_P1", MEPCOP1_64_INSN_CDSUB3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsadd3_h_P0_P1, "CPSADD3_H_P0_P1", MEPCOP1_64_INSN_CPSADD3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsadd3_w_P0_P1, "CPSADD3_W_P0_P1", MEPCOP1_64_INSN_CPSADD3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssub3_h_P0_P1, "CPSSUB3_H_P0_P1", MEPCOP1_64_INSN_CPSSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssub3_w_P0_P1, "CPSSUB3_W_P0_P1", MEPCOP1_64_INSN_CPSSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextuaddu3_b_P0_P1, "CPEXTUADDU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextuadd3_b_P0_P1, "CPEXTUADD3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextladdu3_b_P0_P1, "CPEXTLADDU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextladd3_b_P0_P1, "CPEXTLADD3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextusubu3_b_P0_P1, "CPEXTUSUBU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextusub3_b_P0_P1, "CPEXTUSUB3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextlsubu3_b_P0_P1, "CPEXTLSUBU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpextlsub3_b_P0_P1, "CPEXTLSUB3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaveu3_b_P0_P1, "CPAVEU3_B_P0_P1", MEPCOP1_64_INSN_CPAVEU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpave3_b_P0_P1, "CPAVE3_B_P0_P1", MEPCOP1_64_INSN_CPAVE3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpave3_h_P0_P1, "CPAVE3_H_P0_P1", MEPCOP1_64_INSN_CPAVE3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpave3_w_P0_P1, "CPAVE3_W_P0_P1", MEPCOP1_64_INSN_CPAVE3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddsru3_b_P0_P1, "CPADDSRU3_B_P0_P1", MEPCOP1_64_INSN_CPADDSRU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddsr3_b_P0_P1, "CPADDSR3_B_P0_P1", MEPCOP1_64_INSN_CPADDSR3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddsr3_h_P0_P1, "CPADDSR3_H_P0_P1", MEPCOP1_64_INSN_CPADDSR3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddsr3_w_P0_P1, "CPADDSR3_W_P0_P1", MEPCOP1_64_INSN_CPADDSR3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsu3_b_P0_P1, "CPABSU3_B_P0_P1", MEPCOP1_64_INSN_CPABSU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabs3_b_P0_P1, "CPABS3_B_P0_P1", MEPCOP1_64_INSN_CPABS3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabs3_h_P0_P1, "CPABS3_H_P0_P1", MEPCOP1_64_INSN_CPABS3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpand3_P0_P1, "CPAND3_P0_P1", MEPCOP1_64_INSN_CPAND3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpor3_P0_P1, "CPOR3_P0_P1", MEPCOP1_64_INSN_CPOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpnor3_P0_P1, "CPNOR3_P0_P1", MEPCOP1_64_INSN_CPNOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpxor3_P0_P1, "CPXOR3_P0_P1", MEPCOP1_64_INSN_CPXOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppacku_b_P0_P1, "CPPACKU_B_P0_P1", MEPCOP1_64_INSN_CPPACKU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppack_b_P0_P1, "CPPACK_B_P0_P1", MEPCOP1_64_INSN_CPPACK_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppack_h_P0_P1, "CPPACK_H_P0_P1", MEPCOP1_64_INSN_CPPACK_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmaxu3_b_P0_P1, "CPMAXU3_B_P0_P1", MEPCOP1_64_INSN_CPMAXU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmax3_b_P0_P1, "CPMAX3_B_P0_P1", MEPCOP1_64_INSN_CPMAX3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmax3_h_P0_P1, "CPMAX3_H_P0_P1", MEPCOP1_64_INSN_CPMAX3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmaxu3_w_P0_P1, "CPMAXU3_W_P0_P1", MEPCOP1_64_INSN_CPMAXU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmax3_w_P0_P1, "CPMAX3_W_P0_P1", MEPCOP1_64_INSN_CPMAX3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpminu3_b_P0_P1, "CPMINU3_B_P0_P1", MEPCOP1_64_INSN_CPMINU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmin3_b_P0_P1, "CPMIN3_B_P0_P1", MEPCOP1_64_INSN_CPMIN3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmin3_h_P0_P1, "CPMIN3_H_P0_P1", MEPCOP1_64_INSN_CPMIN3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpminu3_w_P0_P1, "CPMINU3_W_P0_P1", MEPCOP1_64_INSN_CPMINU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmin3_w_P0_P1, "CPMIN3_W_P0_P1", MEPCOP1_64_INSN_CPMIN3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrl3_b_P0_P1, "CPSRL3_B_P0_P1", MEPCOP1_64_INSN_CPSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssrl3_b_P0_P1, "CPSSRL3_B_P0_P1", MEPCOP1_64_INSN_CPSSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrl3_h_P0_P1, "CPSRL3_H_P0_P1", MEPCOP1_64_INSN_CPSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssrl3_h_P0_P1, "CPSSRL3_H_P0_P1", MEPCOP1_64_INSN_CPSSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrl3_w_P0_P1, "CPSRL3_W_P0_P1", MEPCOP1_64_INSN_CPSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssrl3_w_P0_P1, "CPSSRL3_W_P0_P1", MEPCOP1_64_INSN_CPSSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdsrl3_P0_P1, "CDSRL3_P0_P1", MEPCOP1_64_INSN_CDSRL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsra3_b_P0_P1, "CPSRA3_B_P0_P1", MEPCOP1_64_INSN_CPSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssra3_b_P0_P1, "CPSSRA3_B_P0_P1", MEPCOP1_64_INSN_CPSSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsra3_h_P0_P1, "CPSRA3_H_P0_P1", MEPCOP1_64_INSN_CPSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssra3_h_P0_P1, "CPSSRA3_H_P0_P1", MEPCOP1_64_INSN_CPSSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsra3_w_P0_P1, "CPSRA3_W_P0_P1", MEPCOP1_64_INSN_CPSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssra3_w_P0_P1, "CPSSRA3_W_P0_P1", MEPCOP1_64_INSN_CPSSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdsra3_P0_P1, "CDSRA3_P0_P1", MEPCOP1_64_INSN_CDSRA3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsll3_b_P0_P1, "CPSLL3_B_P0_P1", MEPCOP1_64_INSN_CPSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssll3_b_P0_P1, "CPSSLL3_B_P0_P1", MEPCOP1_64_INSN_CPSSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsll3_h_P0_P1, "CPSLL3_H_P0_P1", MEPCOP1_64_INSN_CPSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssll3_h_P0_P1, "CPSSLL3_H_P0_P1", MEPCOP1_64_INSN_CPSSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsll3_w_P0_P1, "CPSLL3_W_P0_P1", MEPCOP1_64_INSN_CPSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssll3_w_P0_P1, "CPSSLL3_W_P0_P1", MEPCOP1_64_INSN_CPSSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdsll3_P0_P1, "CDSLL3_P0_P1", MEPCOP1_64_INSN_CDSLL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsla3_h_P0_P1, "CPSLA3_H_P0_P1", MEPCOP1_64_INSN_CPSLA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsla3_w_P0_P1, "CPSLA3_W_P0_P1", MEPCOP1_64_INSN_CPSLA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrli3_b_P0_P1, "CPSRLI3_B_P0_P1", MEPCOP1_64_INSN_CPSRLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrli3_h_P0_P1, "CPSRLI3_H_P0_P1", MEPCOP1_64_INSN_CPSRLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrli3_w_P0_P1, "CPSRLI3_W_P0_P1", MEPCOP1_64_INSN_CPSRLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdsrli3_P0_P1, "CDSRLI3_P0_P1", MEPCOP1_64_INSN_CDSRLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrai3_b_P0_P1, "CPSRAI3_B_P0_P1", MEPCOP1_64_INSN_CPSRAI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrai3_h_P0_P1, "CPSRAI3_H_P0_P1", MEPCOP1_64_INSN_CPSRAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrai3_w_P0_P1, "CPSRAI3_W_P0_P1", MEPCOP1_64_INSN_CPSRAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdsrai3_P0_P1, "CDSRAI3_P0_P1", MEPCOP1_64_INSN_CDSRAI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpslli3_b_P0_P1, "CPSLLI3_B_P0_P1", MEPCOP1_64_INSN_CPSLLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpslli3_h_P0_P1, "CPSLLI3_H_P0_P1", MEPCOP1_64_INSN_CPSLLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpslli3_w_P0_P1, "CPSLLI3_W_P0_P1", MEPCOP1_64_INSN_CPSLLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdslli3_P0_P1, "CDSLLI3_P0_P1", MEPCOP1_64_INSN_CDSLLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpslai3_h_P0_P1, "CPSLAI3_H_P0_P1", MEPCOP1_64_INSN_CPSLAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpslai3_w_P0_P1, "CPSLAI3_W_P0_P1", MEPCOP1_64_INSN_CPSLAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpclipiu3_w_P0_P1, "CPCLIPIU3_W_P0_P1", MEPCOP1_64_INSN_CPCLIPIU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpclipi3_w_P0_P1, "CPCLIPI3_W_P0_P1", MEPCOP1_64_INSN_CPCLIPI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdclipiu3_P0_P1, "CDCLIPIU3_P0_P1", MEPCOP1_64_INSN_CDCLIPIU3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdclipi3_P0_P1, "CDCLIPI3_P0_P1", MEPCOP1_64_INSN_CDCLIPI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovi_h_P0_P1, "CPMOVI_H_P0_P1", MEPCOP1_64_INSN_CPMOVI_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmoviu_w_P0_P1, "CPMOVIU_W_P0_P1", MEPCOP1_64_INSN_CPMOVIU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovi_w_P0_P1, "CPMOVI_W_P0_P1", MEPCOP1_64_INSN_CPMOVI_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdmoviu_P0_P1, "CDMOVIU_P0_P1", MEPCOP1_64_INSN_CDMOVIU_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cdmovi_P0_P1, "CDMOVI_P0_P1", MEPCOP1_64_INSN_CDMOVI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_c1nop_P1, "C1NOP_P1", MEPCOP1_64_INSN_C1NOP_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovi_b_P0S_P1, "CPMOVI_B_P0S_P1", MEPCOP1_64_INSN_CPMOVI_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpadda1u_b_P1, "CPADDA1U_B_P1", MEPCOP1_64_INSN_CPADDA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpadda1_b_P1, "CPADDA1_B_P1", MEPCOP1_64_INSN_CPADDA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddua1_h_P1, "CPADDUA1_H_P1", MEPCOP1_64_INSN_CPADDUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddla1_h_P1, "CPADDLA1_H_P1", MEPCOP1_64_INSN_CPADDLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddaca1u_b_P1, "CPADDACA1U_B_P1", MEPCOP1_64_INSN_CPADDACA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddaca1_b_P1, "CPADDACA1_B_P1", MEPCOP1_64_INSN_CPADDACA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddacua1_h_P1, "CPADDACUA1_H_P1", MEPCOP1_64_INSN_CPADDACUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaddacla1_h_P1, "CPADDACLA1_H_P1", MEPCOP1_64_INSN_CPADDACLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsuba1u_b_P1, "CPSUBA1U_B_P1", MEPCOP1_64_INSN_CPSUBA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsuba1_b_P1, "CPSUBA1_B_P1", MEPCOP1_64_INSN_CPSUBA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsubua1_h_P1, "CPSUBUA1_H_P1", MEPCOP1_64_INSN_CPSUBUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsubla1_h_P1, "CPSUBLA1_H_P1", MEPCOP1_64_INSN_CPSUBLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsubaca1u_b_P1, "CPSUBACA1U_B_P1", MEPCOP1_64_INSN_CPSUBACA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsubaca1_b_P1, "CPSUBACA1_B_P1", MEPCOP1_64_INSN_CPSUBACA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsubacua1_h_P1, "CPSUBACUA1_H_P1", MEPCOP1_64_INSN_CPSUBACUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsubacla1_h_P1, "CPSUBACLA1_H_P1", MEPCOP1_64_INSN_CPSUBACLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsa1u_b_P1, "CPABSA1U_B_P1", MEPCOP1_64_INSN_CPABSA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsa1_b_P1, "CPABSA1_B_P1", MEPCOP1_64_INSN_CPABSA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsua1_h_P1, "CPABSUA1_H_P1", MEPCOP1_64_INSN_CPABSUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpabsla1_h_P1, "CPABSLA1_H_P1", MEPCOP1_64_INSN_CPABSLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsada1u_b_P1, "CPSADA1U_B_P1", MEPCOP1_64_INSN_CPSADA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsada1_b_P1, "CPSADA1_B_P1", MEPCOP1_64_INSN_CPSADA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsadua1_h_P1, "CPSADUA1_H_P1", MEPCOP1_64_INSN_CPSADUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsadla1_h_P1, "CPSADLA1_H_P1", MEPCOP1_64_INSN_CPSADLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpseta1_h_P1, "CPSETA1_H_P1", MEPCOP1_64_INSN_CPSETA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsetua1_w_P1, "CPSETUA1_W_P1", MEPCOP1_64_INSN_CPSETUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsetla1_w_P1, "CPSETLA1_W_P1", MEPCOP1_64_INSN_CPSETLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmova1_b_P1, "CPMOVA1_B_P1", MEPCOP1_64_INSN_CPMOVA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovua1_h_P1, "CPMOVUA1_H_P1", MEPCOP1_64_INSN_CPMOVUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovla1_h_P1, "CPMOVLA1_H_P1", MEPCOP1_64_INSN_CPMOVLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovuua1_w_P1, "CPMOVUUA1_W_P1", MEPCOP1_64_INSN_CPMOVUUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovula1_w_P1, "CPMOVULA1_W_P1", MEPCOP1_64_INSN_CPMOVULA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovlua1_w_P1, "CPMOVLUA1_W_P1", MEPCOP1_64_INSN_CPMOVLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovlla1_w_P1, "CPMOVLLA1_W_P1", MEPCOP1_64_INSN_CPMOVLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppacka1u_b_P1, "CPPACKA1U_B_P1", MEPCOP1_64_INSN_CPPACKA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppacka1_b_P1, "CPPACKA1_B_P1", MEPCOP1_64_INSN_CPPACKA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppackua1_h_P1, "CPPACKUA1_H_P1", MEPCOP1_64_INSN_CPPACKUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppackla1_h_P1, "CPPACKLA1_H_P1", MEPCOP1_64_INSN_CPPACKLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppackua1_w_P1, "CPPACKUA1_W_P1", MEPCOP1_64_INSN_CPPACKUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cppackla1_w_P1, "CPPACKLA1_W_P1", MEPCOP1_64_INSN_CPPACKLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovhua1_w_P1, "CPMOVHUA1_W_P1", MEPCOP1_64_INSN_CPMOVHUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmovhla1_w_P1, "CPMOVHLA1_W_P1", MEPCOP1_64_INSN_CPMOVHLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacsuma1_P1, "CPACSUMA1_P1", MEPCOP1_64_INSN_CPACSUMA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpaccpa1_P1, "CPACCPA1_P1", MEPCOP1_64_INSN_CPACCPA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpacswp_P1, "CPACSWP_P1", MEPCOP1_64_INSN_CPACSWP_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrla1_P1, "CPSRLA1_P1", MEPCOP1_64_INSN_CPSRLA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsraa1_P1, "CPSRAA1_P1", MEPCOP1_64_INSN_CPSRAA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpslla1_P1, "CPSLLA1_P1", MEPCOP1_64_INSN_CPSLLA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsrlia1_1_p1, "CPSRLIA1_1_P1", MEPCOP1_64_INSN_CPSRLIA1_1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsraia1_1_p1, "CPSRAIA1_1_P1", MEPCOP1_64_INSN_CPSRAIA1_1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsllia1_1_p1, "CPSLLIA1_1_P1", MEPCOP1_64_INSN_CPSLLIA1_1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulia1s0u_b_P1, "CPFMULIA1S0U_B_P1", MEPCOP1_64_INSN_CPFMULIA1S0U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulia1s0_b_P1, "CPFMULIA1S0_B_P1", MEPCOP1_64_INSN_CPFMULIA1S0_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmuliua1s0_h_P1, "CPFMULIUA1S0_H_P1", MEPCOP1_64_INSN_CPFMULIUA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulila1s0_h_P1, "CPFMULILA1S0_H_P1", MEPCOP1_64_INSN_CPFMULILA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadia1s0u_b_P1, "CPFMADIA1S0U_B_P1", MEPCOP1_64_INSN_CPFMADIA1S0U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadia1s0_b_P1, "CPFMADIA1S0_B_P1", MEPCOP1_64_INSN_CPFMADIA1S0_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadiua1s0_h_P1, "CPFMADIUA1S0_H_P1", MEPCOP1_64_INSN_CPFMADIUA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadila1s0_h_P1, "CPFMADILA1S0_H_P1", MEPCOP1_64_INSN_CPFMADILA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulia1s1u_b_P1, "CPFMULIA1S1U_B_P1", MEPCOP1_64_INSN_CPFMULIA1S1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulia1s1_b_P1, "CPFMULIA1S1_B_P1", MEPCOP1_64_INSN_CPFMULIA1S1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmuliua1s1_h_P1, "CPFMULIUA1S1_H_P1", MEPCOP1_64_INSN_CPFMULIUA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulila1s1_h_P1, "CPFMULILA1S1_H_P1", MEPCOP1_64_INSN_CPFMULILA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadia1s1u_b_P1, "CPFMADIA1S1U_B_P1", MEPCOP1_64_INSN_CPFMADIA1S1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadia1s1_b_P1, "CPFMADIA1S1_B_P1", MEPCOP1_64_INSN_CPFMADIA1S1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadiua1s1_h_P1, "CPFMADIUA1S1_H_P1", MEPCOP1_64_INSN_CPFMADIUA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadila1s1_h_P1, "CPFMADILA1S1_H_P1", MEPCOP1_64_INSN_CPFMADILA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamulia1u_b_P1, "CPAMULIA1U_B_P1", MEPCOP1_64_INSN_CPAMULIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamulia1_b_P1, "CPAMULIA1_B_P1", MEPCOP1_64_INSN_CPAMULIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamuliua1_h_P1, "CPAMULIUA1_H_P1", MEPCOP1_64_INSN_CPAMULIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamulila1_h_P1, "CPAMULILA1_H_P1", MEPCOP1_64_INSN_CPAMULILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamadia1u_b_P1, "CPAMADIA1U_B_P1", MEPCOP1_64_INSN_CPAMADIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamadia1_b_P1, "CPAMADIA1_B_P1", MEPCOP1_64_INSN_CPAMADIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamadiua1_h_P1, "CPAMADIUA1_H_P1", MEPCOP1_64_INSN_CPAMADIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpamadila1_h_P1, "CPAMADILA1_H_P1", MEPCOP1_64_INSN_CPAMADILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulia1u_b_P1, "CPFMULIA1U_B_P1", MEPCOP1_64_INSN_CPFMULIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulia1_b_P1, "CPFMULIA1_B_P1", MEPCOP1_64_INSN_CPFMULIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmuliua1_h_P1, "CPFMULIUA1_H_P1", MEPCOP1_64_INSN_CPFMULIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmulila1_h_P1, "CPFMULILA1_H_P1", MEPCOP1_64_INSN_CPFMULILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadia1u_b_P1, "CPFMADIA1U_B_P1", MEPCOP1_64_INSN_CPFMADIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadia1_b_P1, "CPFMADIA1_B_P1", MEPCOP1_64_INSN_CPFMADIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadiua1_h_P1, "CPFMADIUA1_H_P1", MEPCOP1_64_INSN_CPFMADIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpfmadila1_h_P1, "CPFMADILA1_H_P1", MEPCOP1_64_INSN_CPFMADILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssqa1u_b_P1, "CPSSQA1U_B_P1", MEPCOP1_64_INSN_CPSSQA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssqa1_b_P1, "CPSSQA1_B_P1", MEPCOP1_64_INSN_CPSSQA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssda1u_b_P1, "CPSSDA1U_B_P1", MEPCOP1_64_INSN_CPSSDA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpssda1_b_P1, "CPSSDA1_B_P1", MEPCOP1_64_INSN_CPSSDA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmula1u_b_P1, "CPMULA1U_B_P1", MEPCOP1_64_INSN_CPMULA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmula1_b_P1, "CPMULA1_B_P1", MEPCOP1_64_INSN_CPMULA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulua1_h_P1, "CPMULUA1_H_P1", MEPCOP1_64_INSN_CPMULUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulla1_h_P1, "CPMULLA1_H_P1", MEPCOP1_64_INSN_CPMULLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulua1u_w_P1, "CPMULUA1U_W_P1", MEPCOP1_64_INSN_CPMULUA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulla1u_w_P1, "CPMULLA1U_W_P1", MEPCOP1_64_INSN_CPMULLA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulua1_w_P1, "CPMULUA1_W_P1", MEPCOP1_64_INSN_CPMULUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulla1_w_P1, "CPMULLA1_W_P1", MEPCOP1_64_INSN_CPMULLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmada1u_b_P1, "CPMADA1U_B_P1", MEPCOP1_64_INSN_CPMADA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmada1_b_P1, "CPMADA1_B_P1", MEPCOP1_64_INSN_CPMADA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmadua1_h_P1, "CPMADUA1_H_P1", MEPCOP1_64_INSN_CPMADUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmadla1_h_P1, "CPMADLA1_H_P1", MEPCOP1_64_INSN_CPMADLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmadua1u_w_P1, "CPMADUA1U_W_P1", MEPCOP1_64_INSN_CPMADUA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmadla1u_w_P1, "CPMADLA1U_W_P1", MEPCOP1_64_INSN_CPMADLA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmadua1_w_P1, "CPMADUA1_W_P1", MEPCOP1_64_INSN_CPMADUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmadla1_w_P1, "CPMADLA1_W_P1", MEPCOP1_64_INSN_CPMADLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmsbua1_h_P1, "CPMSBUA1_H_P1", MEPCOP1_64_INSN_CPMSBUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmsbla1_h_P1, "CPMSBLA1_H_P1", MEPCOP1_64_INSN_CPMSBLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmsbua1u_w_P1, "CPMSBUA1U_W_P1", MEPCOP1_64_INSN_CPMSBUA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmsbla1u_w_P1, "CPMSBLA1U_W_P1", MEPCOP1_64_INSN_CPMSBLA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmsbua1_w_P1, "CPMSBUA1_W_P1", MEPCOP1_64_INSN_CPMSBUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmsbla1_w_P1, "CPMSBLA1_W_P1", MEPCOP1_64_INSN_CPMSBLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadua1_h_P1, "CPSMADUA1_H_P1", MEPCOP1_64_INSN_CPSMADUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadla1_h_P1, "CPSMADLA1_H_P1", MEPCOP1_64_INSN_CPSMADLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadua1_w_P1, "CPSMADUA1_W_P1", MEPCOP1_64_INSN_CPSMADUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadla1_w_P1, "CPSMADLA1_W_P1", MEPCOP1_64_INSN_CPSMADLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbua1_h_P1, "CPSMSBUA1_H_P1", MEPCOP1_64_INSN_CPSMSBUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbla1_h_P1, "CPSMSBLA1_H_P1", MEPCOP1_64_INSN_CPSMSBLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbua1_w_P1, "CPSMSBUA1_W_P1", MEPCOP1_64_INSN_CPSMSBUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbla1_w_P1, "CPSMSBLA1_W_P1", MEPCOP1_64_INSN_CPSMSBLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulslua1_h_P1, "CPMULSLUA1_H_P1", MEPCOP1_64_INSN_CPMULSLUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulslla1_h_P1, "CPMULSLLA1_H_P1", MEPCOP1_64_INSN_CPMULSLLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulslua1_w_P1, "CPMULSLUA1_W_P1", MEPCOP1_64_INSN_CPMULSLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpmulslla1_w_P1, "CPMULSLLA1_W_P1", MEPCOP1_64_INSN_CPMULSLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadslua1_h_P1, "CPSMADSLUA1_H_P1", MEPCOP1_64_INSN_CPSMADSLUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadslla1_h_P1, "CPSMADSLLA1_H_P1", MEPCOP1_64_INSN_CPSMADSLLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadslua1_w_P1, "CPSMADSLUA1_W_P1", MEPCOP1_64_INSN_CPSMADSLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmadslla1_w_P1, "CPSMADSLLA1_W_P1", MEPCOP1_64_INSN_CPSMADSLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbslua1_h_P1, "CPSMSBSLUA1_H_P1", MEPCOP1_64_INSN_CPSMSBSLUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbslla1_h_P1, "CPSMSBSLLA1_H_P1", MEPCOP1_64_INSN_CPSMSBSLLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbslua1_w_P1, "CPSMSBSLUA1_W_P1", MEPCOP1_64_INSN_CPSMSBSLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
- { mepcop1_64_sem_cpsmsbslla1_w_P1, "CPSMSBSLLA1_W_P1", MEPCOP1_64_INSN_CPSMSBSLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_x_invalid, "X_INVALID", MEPCOP1_64_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcop1_64_sem_cpadd3_b_P0S_P1, "CPADD3_B_P0S_P1", MEPCOP1_64_INSN_CPADD3_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpadd3_h_P0S_P1, "CPADD3_H_P0S_P1", MEPCOP1_64_INSN_CPADD3_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpadd3_w_P0S_P1, "CPADD3_W_P0S_P1", MEPCOP1_64_INSN_CPADD3_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpunpacku_b_P0S_P1, "CPUNPACKU_B_P0S_P1", MEPCOP1_64_INSN_CPUNPACKU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpunpacku_h_P0S_P1, "CPUNPACKU_H_P0S_P1", MEPCOP1_64_INSN_CPUNPACKU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpunpacku_w_P0S_P1, "CPUNPACKU_W_P0S_P1", MEPCOP1_64_INSN_CPUNPACKU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpunpackl_b_P0S_P1, "CPUNPACKL_B_P0S_P1", MEPCOP1_64_INSN_CPUNPACKL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpunpackl_h_P0S_P1, "CPUNPACKL_H_P0S_P1", MEPCOP1_64_INSN_CPUNPACKL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpunpackl_w_P0S_P1, "CPUNPACKL_W_P0S_P1", MEPCOP1_64_INSN_CPUNPACKL_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsel_P0S_P1, "CPSEL_P0S_P1", MEPCOP1_64_INSN_CPSEL_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfsftbs0_P0S_P1, "CPFSFTBS0_P0S_P1", MEPCOP1_64_INSN_CPFSFTBS0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfsftbs1_P0S_P1, "CPFSFTBS1_P0S_P1", MEPCOP1_64_INSN_CPFSFTBS1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmov_P0S_P1, "CPMOV_P0S_P1", MEPCOP1_64_INSN_CPMOV_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsz_b_P0S_P1, "CPABSZ_B_P0S_P1", MEPCOP1_64_INSN_CPABSZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsz_h_P0S_P1, "CPABSZ_H_P0S_P1", MEPCOP1_64_INSN_CPABSZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsz_w_P0S_P1, "CPABSZ_W_P0S_P1", MEPCOP1_64_INSN_CPABSZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpldz_h_P0S_P1, "CPLDZ_H_P0S_P1", MEPCOP1_64_INSN_CPLDZ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpldz_w_P0S_P1, "CPLDZ_W_P0S_P1", MEPCOP1_64_INSN_CPLDZ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpnorm_h_P0S_P1, "CPNORM_H_P0S_P1", MEPCOP1_64_INSN_CPNORM_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpnorm_w_P0S_P1, "CPNORM_W_P0S_P1", MEPCOP1_64_INSN_CPNORM_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cphaddu_b_P0S_P1, "CPHADDU_B_P0S_P1", MEPCOP1_64_INSN_CPHADDU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cphadd_b_P0S_P1, "CPHADD_B_P0S_P1", MEPCOP1_64_INSN_CPHADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cphadd_h_P0S_P1, "CPHADD_H_P0S_P1", MEPCOP1_64_INSN_CPHADD_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cphadd_w_P0S_P1, "CPHADD_W_P0S_P1", MEPCOP1_64_INSN_CPHADD_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpccadd_b_P0S_P1, "CPCCADD_B_P0S_P1", MEPCOP1_64_INSN_CPCCADD_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRSTCOPY, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpbcast_b_P0S_P1, "CPBCAST_B_P0S_P1", MEPCOP1_64_INSN_CPBCAST_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpbcast_h_P0S_P1, "CPBCAST_H_P0S_P1", MEPCOP1_64_INSN_CPBCAST_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpbcast_w_P0S_P1, "CPBCAST_W_P0S_P1", MEPCOP1_64_INSN_CPBCAST_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextuu_b_P0S_P1, "CPEXTUU_B_P0S_P1", MEPCOP1_64_INSN_CPEXTUU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextu_b_P0S_P1, "CPEXTU_B_P0S_P1", MEPCOP1_64_INSN_CPEXTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextuu_h_P0S_P1, "CPEXTUU_H_P0S_P1", MEPCOP1_64_INSN_CPEXTUU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextu_h_P0S_P1, "CPEXTU_H_P0S_P1", MEPCOP1_64_INSN_CPEXTU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextlu_b_P0S_P1, "CPEXTLU_B_P0S_P1", MEPCOP1_64_INSN_CPEXTLU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextl_b_P0S_P1, "CPEXTL_B_P0S_P1", MEPCOP1_64_INSN_CPEXTL_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextlu_h_P0S_P1, "CPEXTLU_H_P0S_P1", MEPCOP1_64_INSN_CPEXTLU_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4UHI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextl_h_P0S_P1, "CPEXTL_H_P0S_P1", MEPCOP1_64_INSN_CPEXTL_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcastub_h_P0S_P1, "CPCASTUB_H_P0S_P1", MEPCOP1_64_INSN_CPCASTUB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcastb_h_P0S_P1, "CPCASTB_H_P0S_P1", MEPCOP1_64_INSN_CPCASTB_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcastub_w_P0S_P1, "CPCASTUB_W_P0S_P1", MEPCOP1_64_INSN_CPCASTUB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcastb_w_P0S_P1, "CPCASTB_W_P0S_P1", MEPCOP1_64_INSN_CPCASTB_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcastuh_w_P0S_P1, "CPCASTUH_W_P0S_P1", MEPCOP1_64_INSN_CPCASTUH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcasth_w_P0S_P1, "CPCASTH_W_P0S_P1", MEPCOP1_64_INSN_CPCASTH_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdcastuw_P0S_P1, "CDCASTUW_P0S_P1", MEPCOP1_64_INSN_CDCASTUW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdcastw_P0S_P1, "CDCASTW_P0S_P1", MEPCOP1_64_INSN_CDCASTW_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovfrcsar0_P0S_P1, "CPMOVFRCSAR0_P0S_P1", MEPCOP1_64_INSN_CPMOVFRCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovfrcsar1_P0S_P1, "CPMOVFRCSAR1_P0S_P1", MEPCOP1_64_INSN_CPMOVFRCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovfrcc_P0S_P1, "CPMOVFRCC_P0S_P1", MEPCOP1_64_INSN_CPMOVFRCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovtocsar0_P0S_P1, "CPMOVTOCSAR0_P0S_P1", MEPCOP1_64_INSN_CPMOVTOCSAR0_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovtocsar1_P0S_P1, "CPMOVTOCSAR1_P0S_P1", MEPCOP1_64_INSN_CPMOVTOCSAR1_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovtocc_P0S_P1, "CPMOVTOCC_P0S_P1", MEPCOP1_64_INSN_CPMOVTOCC_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpeqz_b_P0S_P1, "CPCMPEQZ_B_P0S_P1", MEPCOP1_64_INSN_CPCMPEQZ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpeq_b_P0S_P1, "CPCMPEQ_B_P0S_P1", MEPCOP1_64_INSN_CPCMPEQ_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpeq_h_P0S_P1, "CPCMPEQ_H_P0S_P1", MEPCOP1_64_INSN_CPCMPEQ_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpeq_w_P0S_P1, "CPCMPEQ_W_P0S_P1", MEPCOP1_64_INSN_CPCMPEQ_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpne_b_P0S_P1, "CPCMPNE_B_P0S_P1", MEPCOP1_64_INSN_CPCMPNE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpne_h_P0S_P1, "CPCMPNE_H_P0S_P1", MEPCOP1_64_INSN_CPCMPNE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpne_w_P0S_P1, "CPCMPNE_W_P0S_P1", MEPCOP1_64_INSN_CPCMPNE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpgtu_b_P0S_P1, "CPCMPGTU_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGTU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpgt_b_P0S_P1, "CPCMPGT_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGT_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpgt_h_P0S_P1, "CPCMPGT_H_P0S_P1", MEPCOP1_64_INSN_CPCMPGT_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpgtu_w_P0S_P1, "CPCMPGTU_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGTU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpgt_w_P0S_P1, "CPCMPGT_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGT_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpgeu_b_P0S_P1, "CPCMPGEU_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGEU_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpge_b_P0S_P1, "CPCMPGE_B_P0S_P1", MEPCOP1_64_INSN_CPCMPGE_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpge_h_P0S_P1, "CPCMPGE_H_P0S_P1", MEPCOP1_64_INSN_CPCMPGE_H_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpgeu_w_P0S_P1, "CPCMPGEU_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGEU_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpcmpge_w_P0S_P1, "CPCMPGE_W_P0S_P1", MEPCOP1_64_INSN_CPCMPGE_W_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfsftbi_P0_P1, "CPFSFTBI_P0_P1", MEPCOP1_64_INSN_CPFSFTBI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpeq_b_P0_P1, "CPACMPEQ_B_P0_P1", MEPCOP1_64_INSN_CPACMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpeq_h_P0_P1, "CPACMPEQ_H_P0_P1", MEPCOP1_64_INSN_CPACMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpeq_w_P0_P1, "CPACMPEQ_W_P0_P1", MEPCOP1_64_INSN_CPACMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpne_b_P0_P1, "CPACMPNE_B_P0_P1", MEPCOP1_64_INSN_CPACMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpne_h_P0_P1, "CPACMPNE_H_P0_P1", MEPCOP1_64_INSN_CPACMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpne_w_P0_P1, "CPACMPNE_W_P0_P1", MEPCOP1_64_INSN_CPACMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpgtu_b_P0_P1, "CPACMPGTU_B_P0_P1", MEPCOP1_64_INSN_CPACMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpgt_b_P0_P1, "CPACMPGT_B_P0_P1", MEPCOP1_64_INSN_CPACMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpgt_h_P0_P1, "CPACMPGT_H_P0_P1", MEPCOP1_64_INSN_CPACMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpgtu_w_P0_P1, "CPACMPGTU_W_P0_P1", MEPCOP1_64_INSN_CPACMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpgt_w_P0_P1, "CPACMPGT_W_P0_P1", MEPCOP1_64_INSN_CPACMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpgeu_b_P0_P1, "CPACMPGEU_B_P0_P1", MEPCOP1_64_INSN_CPACMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpge_b_P0_P1, "CPACMPGE_B_P0_P1", MEPCOP1_64_INSN_CPACMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpge_h_P0_P1, "CPACMPGE_H_P0_P1", MEPCOP1_64_INSN_CPACMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpgeu_w_P0_P1, "CPACMPGEU_W_P0_P1", MEPCOP1_64_INSN_CPACMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacmpge_w_P0_P1, "CPACMPGE_W_P0_P1", MEPCOP1_64_INSN_CPACMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpeq_b_P0_P1, "CPOCMPEQ_B_P0_P1", MEPCOP1_64_INSN_CPOCMPEQ_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpeq_h_P0_P1, "CPOCMPEQ_H_P0_P1", MEPCOP1_64_INSN_CPOCMPEQ_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpeq_w_P0_P1, "CPOCMPEQ_W_P0_P1", MEPCOP1_64_INSN_CPOCMPEQ_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpne_b_P0_P1, "CPOCMPNE_B_P0_P1", MEPCOP1_64_INSN_CPOCMPNE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpne_h_P0_P1, "CPOCMPNE_H_P0_P1", MEPCOP1_64_INSN_CPOCMPNE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpne_w_P0_P1, "CPOCMPNE_W_P0_P1", MEPCOP1_64_INSN_CPOCMPNE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpgtu_b_P0_P1, "CPOCMPGTU_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGTU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpgt_b_P0_P1, "CPOCMPGT_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGT_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpgt_h_P0_P1, "CPOCMPGT_H_P0_P1", MEPCOP1_64_INSN_CPOCMPGT_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpgtu_w_P0_P1, "CPOCMPGTU_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGTU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpgt_w_P0_P1, "CPOCMPGT_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGT_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpgeu_b_P0_P1, "CPOCMPGEU_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGEU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpge_b_P0_P1, "CPOCMPGE_B_P0_P1", MEPCOP1_64_INSN_CPOCMPGE_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpge_h_P0_P1, "CPOCMPGE_H_P0_P1", MEPCOP1_64_INSN_CPOCMPGE_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpgeu_w_P0_P1, "CPOCMPGEU_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGEU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpocmpge_w_P0_P1, "CPOCMPGE_W_P0_P1", MEPCOP1_64_INSN_CPOCMPGE_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdadd3_P0_P1, "CDADD3_P0_P1", MEPCOP1_64_INSN_CDADD3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsub3_b_P0_P1, "CPSUB3_B_P0_P1", MEPCOP1_64_INSN_CPSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsub3_h_P0_P1, "CPSUB3_H_P0_P1", MEPCOP1_64_INSN_CPSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsub3_w_P0_P1, "CPSUB3_W_P0_P1", MEPCOP1_64_INSN_CPSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdsub3_P0_P1, "CDSUB3_P0_P1", MEPCOP1_64_INSN_CDSUB3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsadd3_h_P0_P1, "CPSADD3_H_P0_P1", MEPCOP1_64_INSN_CPSADD3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsadd3_w_P0_P1, "CPSADD3_W_P0_P1", MEPCOP1_64_INSN_CPSADD3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssub3_h_P0_P1, "CPSSUB3_H_P0_P1", MEPCOP1_64_INSN_CPSSUB3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssub3_w_P0_P1, "CPSSUB3_W_P0_P1", MEPCOP1_64_INSN_CPSSUB3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextuaddu3_b_P0_P1, "CPEXTUADDU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextuadd3_b_P0_P1, "CPEXTUADD3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextladdu3_b_P0_P1, "CPEXTLADDU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLADDU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextladd3_b_P0_P1, "CPEXTLADD3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLADD3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextusubu3_b_P0_P1, "CPEXTUSUBU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextusub3_b_P0_P1, "CPEXTUSUB3_B_P0_P1", MEPCOP1_64_INSN_CPEXTUSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextlsubu3_b_P0_P1, "CPEXTLSUBU3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLSUBU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpextlsub3_b_P0_P1, "CPEXTLSUB3_B_P0_P1", MEPCOP1_64_INSN_CPEXTLSUB3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaveu3_b_P0_P1, "CPAVEU3_B_P0_P1", MEPCOP1_64_INSN_CPAVEU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpave3_b_P0_P1, "CPAVE3_B_P0_P1", MEPCOP1_64_INSN_CPAVE3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpave3_h_P0_P1, "CPAVE3_H_P0_P1", MEPCOP1_64_INSN_CPAVE3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpave3_w_P0_P1, "CPAVE3_W_P0_P1", MEPCOP1_64_INSN_CPAVE3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddsru3_b_P0_P1, "CPADDSRU3_B_P0_P1", MEPCOP1_64_INSN_CPADDSRU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddsr3_b_P0_P1, "CPADDSR3_B_P0_P1", MEPCOP1_64_INSN_CPADDSR3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddsr3_h_P0_P1, "CPADDSR3_H_P0_P1", MEPCOP1_64_INSN_CPADDSR3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddsr3_w_P0_P1, "CPADDSR3_W_P0_P1", MEPCOP1_64_INSN_CPADDSR3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsu3_b_P0_P1, "CPABSU3_B_P0_P1", MEPCOP1_64_INSN_CPABSU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabs3_b_P0_P1, "CPABS3_B_P0_P1", MEPCOP1_64_INSN_CPABS3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabs3_h_P0_P1, "CPABS3_H_P0_P1", MEPCOP1_64_INSN_CPABS3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpand3_P0_P1, "CPAND3_P0_P1", MEPCOP1_64_INSN_CPAND3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpor3_P0_P1, "CPOR3_P0_P1", MEPCOP1_64_INSN_CPOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpnor3_P0_P1, "CPNOR3_P0_P1", MEPCOP1_64_INSN_CPNOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpxor3_P0_P1, "CPXOR3_P0_P1", MEPCOP1_64_INSN_CPXOR3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_VECT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppacku_b_P0_P1, "CPPACKU_B_P0_P1", MEPCOP1_64_INSN_CPPACKU_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppack_b_P0_P1, "CPPACK_B_P0_P1", MEPCOP1_64_INSN_CPPACK_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppack_h_P0_P1, "CPPACK_H_P0_P1", MEPCOP1_64_INSN_CPPACK_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmaxu3_b_P0_P1, "CPMAXU3_B_P0_P1", MEPCOP1_64_INSN_CPMAXU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmax3_b_P0_P1, "CPMAX3_B_P0_P1", MEPCOP1_64_INSN_CPMAX3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmax3_h_P0_P1, "CPMAX3_H_P0_P1", MEPCOP1_64_INSN_CPMAX3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmaxu3_w_P0_P1, "CPMAXU3_W_P0_P1", MEPCOP1_64_INSN_CPMAXU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmax3_w_P0_P1, "CPMAX3_W_P0_P1", MEPCOP1_64_INSN_CPMAX3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpminu3_b_P0_P1, "CPMINU3_B_P0_P1", MEPCOP1_64_INSN_CPMINU3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmin3_b_P0_P1, "CPMIN3_B_P0_P1", MEPCOP1_64_INSN_CPMIN3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmin3_h_P0_P1, "CPMIN3_H_P0_P1", MEPCOP1_64_INSN_CPMIN3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpminu3_w_P0_P1, "CPMINU3_W_P0_P1", MEPCOP1_64_INSN_CPMINU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmin3_w_P0_P1, "CPMIN3_W_P0_P1", MEPCOP1_64_INSN_CPMIN3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrl3_b_P0_P1, "CPSRL3_B_P0_P1", MEPCOP1_64_INSN_CPSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssrl3_b_P0_P1, "CPSSRL3_B_P0_P1", MEPCOP1_64_INSN_CPSSRL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrl3_h_P0_P1, "CPSRL3_H_P0_P1", MEPCOP1_64_INSN_CPSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssrl3_h_P0_P1, "CPSSRL3_H_P0_P1", MEPCOP1_64_INSN_CPSSRL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrl3_w_P0_P1, "CPSRL3_W_P0_P1", MEPCOP1_64_INSN_CPSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssrl3_w_P0_P1, "CPSSRL3_W_P0_P1", MEPCOP1_64_INSN_CPSSRL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdsrl3_P0_P1, "CDSRL3_P0_P1", MEPCOP1_64_INSN_CDSRL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsra3_b_P0_P1, "CPSRA3_B_P0_P1", MEPCOP1_64_INSN_CPSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssra3_b_P0_P1, "CPSSRA3_B_P0_P1", MEPCOP1_64_INSN_CPSSRA3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsra3_h_P0_P1, "CPSRA3_H_P0_P1", MEPCOP1_64_INSN_CPSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssra3_h_P0_P1, "CPSSRA3_H_P0_P1", MEPCOP1_64_INSN_CPSSRA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsra3_w_P0_P1, "CPSRA3_W_P0_P1", MEPCOP1_64_INSN_CPSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssra3_w_P0_P1, "CPSSRA3_W_P0_P1", MEPCOP1_64_INSN_CPSSRA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdsra3_P0_P1, "CDSRA3_P0_P1", MEPCOP1_64_INSN_CDSRA3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsll3_b_P0_P1, "CPSLL3_B_P0_P1", MEPCOP1_64_INSN_CPSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssll3_b_P0_P1, "CPSSLL3_B_P0_P1", MEPCOP1_64_INSN_CPSSLL3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsll3_h_P0_P1, "CPSLL3_H_P0_P1", MEPCOP1_64_INSN_CPSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssll3_h_P0_P1, "CPSSLL3_H_P0_P1", MEPCOP1_64_INSN_CPSSLL3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsll3_w_P0_P1, "CPSLL3_W_P0_P1", MEPCOP1_64_INSN_CPSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssll3_w_P0_P1, "CPSSLL3_W_P0_P1", MEPCOP1_64_INSN_CPSSLL3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdsll3_P0_P1, "CDSLL3_P0_P1", MEPCOP1_64_INSN_CDSLL3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsla3_h_P0_P1, "CPSLA3_H_P0_P1", MEPCOP1_64_INSN_CPSLA3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsla3_w_P0_P1, "CPSLA3_W_P0_P1", MEPCOP1_64_INSN_CPSLA3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrli3_b_P0_P1, "CPSRLI3_B_P0_P1", MEPCOP1_64_INSN_CPSRLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrli3_h_P0_P1, "CPSRLI3_H_P0_P1", MEPCOP1_64_INSN_CPSRLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrli3_w_P0_P1, "CPSRLI3_W_P0_P1", MEPCOP1_64_INSN_CPSRLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdsrli3_P0_P1, "CDSRLI3_P0_P1", MEPCOP1_64_INSN_CDSRLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrai3_b_P0_P1, "CPSRAI3_B_P0_P1", MEPCOP1_64_INSN_CPSRAI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrai3_h_P0_P1, "CPSRAI3_H_P0_P1", MEPCOP1_64_INSN_CPSRAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrai3_w_P0_P1, "CPSRAI3_W_P0_P1", MEPCOP1_64_INSN_CPSRAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdsrai3_P0_P1, "CDSRAI3_P0_P1", MEPCOP1_64_INSN_CDSRAI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpslli3_b_P0_P1, "CPSLLI3_B_P0_P1", MEPCOP1_64_INSN_CPSLLI3_B_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpslli3_h_P0_P1, "CPSLLI3_H_P0_P1", MEPCOP1_64_INSN_CPSLLI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpslli3_w_P0_P1, "CPSLLI3_W_P0_P1", MEPCOP1_64_INSN_CPSLLI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdslli3_P0_P1, "CDSLLI3_P0_P1", MEPCOP1_64_INSN_CDSLLI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpslai3_h_P0_P1, "CPSLAI3_H_P0_P1", MEPCOP1_64_INSN_CPSLAI3_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpslai3_w_P0_P1, "CPSLAI3_W_P0_P1", MEPCOP1_64_INSN_CPSLAI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpclipiu3_w_P0_P1, "CPCLIPIU3_W_P0_P1", MEPCOP1_64_INSN_CPCLIPIU3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpclipi3_w_P0_P1, "CPCLIPI3_W_P0_P1", MEPCOP1_64_INSN_CPCLIPI3_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdclipiu3_P0_P1, "CDCLIPIU3_P0_P1", MEPCOP1_64_INSN_CDCLIPIU3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdclipi3_P0_P1, "CDCLIPI3_P0_P1", MEPCOP1_64_INSN_CDCLIPI3_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovi_h_P0_P1, "CPMOVI_H_P0_P1", MEPCOP1_64_INSN_CPMOVI_H_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmoviu_w_P0_P1, "CPMOVIU_W_P0_P1", MEPCOP1_64_INSN_CPMOVIU_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2USI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovi_w_P0_P1, "CPMOVI_W_P0_P1", MEPCOP1_64_INSN_CPMOVI_W_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdmoviu_P0_P1, "CDMOVIU_P0_P1", MEPCOP1_64_INSN_CDMOVIU_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cdmovi_P0_P1, "CDMOVI_P0_P1", MEPCOP1_64_INSN_CDMOVI_P0_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc" }, CPTYPE_CP_DATA_BUS_INT, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_c1nop_P1, "C1NOP_P1", MEPCOP1_64_INSN_C1NOP_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovi_b_P0S_P1, "CPMOVI_B_P0S_P1", MEPCOP1_64_INSN_CPMOVI_B_P0S_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x24" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P0S)|(1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpadda1u_b_P1, "CPADDA1U_B_P1", MEPCOP1_64_INSN_CPADDA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpadda1_b_P1, "CPADDA1_B_P1", MEPCOP1_64_INSN_CPADDA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddua1_h_P1, "CPADDUA1_H_P1", MEPCOP1_64_INSN_CPADDUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddla1_h_P1, "CPADDLA1_H_P1", MEPCOP1_64_INSN_CPADDLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddaca1u_b_P1, "CPADDACA1U_B_P1", MEPCOP1_64_INSN_CPADDACA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddaca1_b_P1, "CPADDACA1_B_P1", MEPCOP1_64_INSN_CPADDACA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddacua1_h_P1, "CPADDACUA1_H_P1", MEPCOP1_64_INSN_CPADDACUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaddacla1_h_P1, "CPADDACLA1_H_P1", MEPCOP1_64_INSN_CPADDACLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsuba1u_b_P1, "CPSUBA1U_B_P1", MEPCOP1_64_INSN_CPSUBA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsuba1_b_P1, "CPSUBA1_B_P1", MEPCOP1_64_INSN_CPSUBA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsubua1_h_P1, "CPSUBUA1_H_P1", MEPCOP1_64_INSN_CPSUBUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsubla1_h_P1, "CPSUBLA1_H_P1", MEPCOP1_64_INSN_CPSUBLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsubaca1u_b_P1, "CPSUBACA1U_B_P1", MEPCOP1_64_INSN_CPSUBACA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsubaca1_b_P1, "CPSUBACA1_B_P1", MEPCOP1_64_INSN_CPSUBACA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsubacua1_h_P1, "CPSUBACUA1_H_P1", MEPCOP1_64_INSN_CPSUBACUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsubacla1_h_P1, "CPSUBACLA1_H_P1", MEPCOP1_64_INSN_CPSUBACLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsa1u_b_P1, "CPABSA1U_B_P1", MEPCOP1_64_INSN_CPABSA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsa1_b_P1, "CPABSA1_B_P1", MEPCOP1_64_INSN_CPABSA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsua1_h_P1, "CPABSUA1_H_P1", MEPCOP1_64_INSN_CPABSUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpabsla1_h_P1, "CPABSLA1_H_P1", MEPCOP1_64_INSN_CPABSLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsada1u_b_P1, "CPSADA1U_B_P1", MEPCOP1_64_INSN_CPSADA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsada1_b_P1, "CPSADA1_B_P1", MEPCOP1_64_INSN_CPSADA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsadua1_h_P1, "CPSADUA1_H_P1", MEPCOP1_64_INSN_CPSADUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsadla1_h_P1, "CPSADLA1_H_P1", MEPCOP1_64_INSN_CPSADLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpseta1_h_P1, "CPSETA1_H_P1", MEPCOP1_64_INSN_CPSETA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsetua1_w_P1, "CPSETUA1_W_P1", MEPCOP1_64_INSN_CPSETUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsetla1_w_P1, "CPSETLA1_W_P1", MEPCOP1_64_INSN_CPSETLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmova1_b_P1, "CPMOVA1_B_P1", MEPCOP1_64_INSN_CPMOVA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovua1_h_P1, "CPMOVUA1_H_P1", MEPCOP1_64_INSN_CPMOVUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovla1_h_P1, "CPMOVLA1_H_P1", MEPCOP1_64_INSN_CPMOVLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovuua1_w_P1, "CPMOVUUA1_W_P1", MEPCOP1_64_INSN_CPMOVUUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovula1_w_P1, "CPMOVULA1_W_P1", MEPCOP1_64_INSN_CPMOVULA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovlua1_w_P1, "CPMOVLUA1_W_P1", MEPCOP1_64_INSN_CPMOVLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovlla1_w_P1, "CPMOVLLA1_W_P1", MEPCOP1_64_INSN_CPMOVLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppacka1u_b_P1, "CPPACKA1U_B_P1", MEPCOP1_64_INSN_CPPACKA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppacka1_b_P1, "CPPACKA1_B_P1", MEPCOP1_64_INSN_CPPACKA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppackua1_h_P1, "CPPACKUA1_H_P1", MEPCOP1_64_INSN_CPPACKUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppackla1_h_P1, "CPPACKLA1_H_P1", MEPCOP1_64_INSN_CPPACKLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppackua1_w_P1, "CPPACKUA1_W_P1", MEPCOP1_64_INSN_CPPACKUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cppackla1_w_P1, "CPPACKLA1_W_P1", MEPCOP1_64_INSN_CPPACKLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovhua1_w_P1, "CPMOVHUA1_W_P1", MEPCOP1_64_INSN_CPMOVHUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmovhla1_w_P1, "CPMOVHLA1_W_P1", MEPCOP1_64_INSN_CPMOVHLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_FIRST, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacsuma1_P1, "CPACSUMA1_P1", MEPCOP1_64_INSN_CPACSUMA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpaccpa1_P1, "CPACCPA1_P1", MEPCOP1_64_INSN_CPACCPA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpacswp_P1, "CPACSWP_P1", MEPCOP1_64_INSN_CPACSWP_P1, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrla1_P1, "CPSRLA1_P1", MEPCOP1_64_INSN_CPSRLA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsraa1_P1, "CPSRAA1_P1", MEPCOP1_64_INSN_CPSRAA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpslla1_P1, "CPSLLA1_P1", MEPCOP1_64_INSN_CPSLLA1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsrlia1_1_p1, "CPSRLIA1_1_P1", MEPCOP1_64_INSN_CPSRLIA1_1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsraia1_1_p1, "CPSRAIA1_1_P1", MEPCOP1_64_INSN_CPSRAIA1_1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsllia1_1_p1, "CPSLLIA1_1_P1", MEPCOP1_64_INSN_CPSLLIA1_1_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulia1s0u_b_P1, "CPFMULIA1S0U_B_P1", MEPCOP1_64_INSN_CPFMULIA1S0U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulia1s0_b_P1, "CPFMULIA1S0_B_P1", MEPCOP1_64_INSN_CPFMULIA1S0_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmuliua1s0_h_P1, "CPFMULIUA1S0_H_P1", MEPCOP1_64_INSN_CPFMULIUA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulila1s0_h_P1, "CPFMULILA1S0_H_P1", MEPCOP1_64_INSN_CPFMULILA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadia1s0u_b_P1, "CPFMADIA1S0U_B_P1", MEPCOP1_64_INSN_CPFMADIA1S0U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadia1s0_b_P1, "CPFMADIA1S0_B_P1", MEPCOP1_64_INSN_CPFMADIA1S0_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadiua1s0_h_P1, "CPFMADIUA1S0_H_P1", MEPCOP1_64_INSN_CPFMADIUA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadila1s0_h_P1, "CPFMADILA1S0_H_P1", MEPCOP1_64_INSN_CPFMADILA1S0_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulia1s1u_b_P1, "CPFMULIA1S1U_B_P1", MEPCOP1_64_INSN_CPFMULIA1S1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulia1s1_b_P1, "CPFMULIA1S1_B_P1", MEPCOP1_64_INSN_CPFMULIA1S1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmuliua1s1_h_P1, "CPFMULIUA1S1_H_P1", MEPCOP1_64_INSN_CPFMULIUA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulila1s1_h_P1, "CPFMULILA1S1_H_P1", MEPCOP1_64_INSN_CPFMULILA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadia1s1u_b_P1, "CPFMADIA1S1U_B_P1", MEPCOP1_64_INSN_CPFMADIA1S1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadia1s1_b_P1, "CPFMADIA1S1_B_P1", MEPCOP1_64_INSN_CPFMADIA1S1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadiua1s1_h_P1, "CPFMADIUA1S1_H_P1", MEPCOP1_64_INSN_CPFMADIUA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadila1s1_h_P1, "CPFMADILA1S1_H_P1", MEPCOP1_64_INSN_CPFMADILA1S1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamulia1u_b_P1, "CPAMULIA1U_B_P1", MEPCOP1_64_INSN_CPAMULIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamulia1_b_P1, "CPAMULIA1_B_P1", MEPCOP1_64_INSN_CPAMULIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamuliua1_h_P1, "CPAMULIUA1_H_P1", MEPCOP1_64_INSN_CPAMULIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamulila1_h_P1, "CPAMULILA1_H_P1", MEPCOP1_64_INSN_CPAMULILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamadia1u_b_P1, "CPAMADIA1U_B_P1", MEPCOP1_64_INSN_CPAMADIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamadia1_b_P1, "CPAMADIA1_B_P1", MEPCOP1_64_INSN_CPAMADIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamadiua1_h_P1, "CPAMADIUA1_H_P1", MEPCOP1_64_INSN_CPAMADIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpamadila1_h_P1, "CPAMADILA1_H_P1", MEPCOP1_64_INSN_CPAMADILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulia1u_b_P1, "CPFMULIA1U_B_P1", MEPCOP1_64_INSN_CPFMULIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulia1_b_P1, "CPFMULIA1_B_P1", MEPCOP1_64_INSN_CPFMULIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmuliua1_h_P1, "CPFMULIUA1_H_P1", MEPCOP1_64_INSN_CPFMULIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmulila1_h_P1, "CPFMULILA1_H_P1", MEPCOP1_64_INSN_CPFMULILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadia1u_b_P1, "CPFMADIA1U_B_P1", MEPCOP1_64_INSN_CPFMADIA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadia1_b_P1, "CPFMADIA1_B_P1", MEPCOP1_64_INSN_CPFMADIA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadiua1_h_P1, "CPFMADIUA1_H_P1", MEPCOP1_64_INSN_CPFMADIUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpfmadila1_h_P1, "CPFMADILA1_H_P1", MEPCOP1_64_INSN_CPFMADILA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssqa1u_b_P1, "CPSSQA1U_B_P1", MEPCOP1_64_INSN_CPSSQA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssqa1_b_P1, "CPSSQA1_B_P1", MEPCOP1_64_INSN_CPSSQA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssda1u_b_P1, "CPSSDA1U_B_P1", MEPCOP1_64_INSN_CPSSDA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpssda1_b_P1, "CPSSDA1_B_P1", MEPCOP1_64_INSN_CPSSDA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmula1u_b_P1, "CPMULA1U_B_P1", MEPCOP1_64_INSN_CPMULA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmula1_b_P1, "CPMULA1_B_P1", MEPCOP1_64_INSN_CPMULA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulua1_h_P1, "CPMULUA1_H_P1", MEPCOP1_64_INSN_CPMULUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulla1_h_P1, "CPMULLA1_H_P1", MEPCOP1_64_INSN_CPMULLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulua1u_w_P1, "CPMULUA1U_W_P1", MEPCOP1_64_INSN_CPMULUA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulla1u_w_P1, "CPMULLA1U_W_P1", MEPCOP1_64_INSN_CPMULLA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulua1_w_P1, "CPMULUA1_W_P1", MEPCOP1_64_INSN_CPMULUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulla1_w_P1, "CPMULLA1_W_P1", MEPCOP1_64_INSN_CPMULLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmada1u_b_P1, "CPMADA1U_B_P1", MEPCOP1_64_INSN_CPMADA1U_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8UQI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmada1_b_P1, "CPMADA1_B_P1", MEPCOP1_64_INSN_CPMADA1_B_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V8QI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmadua1_h_P1, "CPMADUA1_H_P1", MEPCOP1_64_INSN_CPMADUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmadla1_h_P1, "CPMADLA1_H_P1", MEPCOP1_64_INSN_CPMADLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmadua1u_w_P1, "CPMADUA1U_W_P1", MEPCOP1_64_INSN_CPMADUA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmadla1u_w_P1, "CPMADLA1U_W_P1", MEPCOP1_64_INSN_CPMADLA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmadua1_w_P1, "CPMADUA1_W_P1", MEPCOP1_64_INSN_CPMADUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmadla1_w_P1, "CPMADLA1_W_P1", MEPCOP1_64_INSN_CPMADLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmsbua1_h_P1, "CPMSBUA1_H_P1", MEPCOP1_64_INSN_CPMSBUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmsbla1_h_P1, "CPMSBLA1_H_P1", MEPCOP1_64_INSN_CPMSBLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmsbua1u_w_P1, "CPMSBUA1U_W_P1", MEPCOP1_64_INSN_CPMSBUA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmsbla1u_w_P1, "CPMSBLA1U_W_P1", MEPCOP1_64_INSN_CPMSBLA1U_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2USI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmsbua1_w_P1, "CPMSBUA1_W_P1", MEPCOP1_64_INSN_CPMSBUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmsbla1_w_P1, "CPMSBLA1_W_P1", MEPCOP1_64_INSN_CPMSBLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadua1_h_P1, "CPSMADUA1_H_P1", MEPCOP1_64_INSN_CPSMADUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadla1_h_P1, "CPSMADLA1_H_P1", MEPCOP1_64_INSN_CPSMADLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadua1_w_P1, "CPSMADUA1_W_P1", MEPCOP1_64_INSN_CPSMADUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadla1_w_P1, "CPSMADLA1_W_P1", MEPCOP1_64_INSN_CPSMADLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbua1_h_P1, "CPSMSBUA1_H_P1", MEPCOP1_64_INSN_CPSMSBUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbla1_h_P1, "CPSMSBLA1_H_P1", MEPCOP1_64_INSN_CPSMSBLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbua1_w_P1, "CPSMSBUA1_W_P1", MEPCOP1_64_INSN_CPSMSBUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbla1_w_P1, "CPSMSBLA1_W_P1", MEPCOP1_64_INSN_CPSMSBLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulslua1_h_P1, "CPMULSLUA1_H_P1", MEPCOP1_64_INSN_CPMULSLUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulslla1_h_P1, "CPMULSLLA1_H_P1", MEPCOP1_64_INSN_CPMULSLLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulslua1_w_P1, "CPMULSLUA1_W_P1", MEPCOP1_64_INSN_CPMULSLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpmulslla1_w_P1, "CPMULSLLA1_W_P1", MEPCOP1_64_INSN_CPMULSLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadslua1_h_P1, "CPSMADSLUA1_H_P1", MEPCOP1_64_INSN_CPSMADSLUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadslla1_h_P1, "CPSMADSLLA1_H_P1", MEPCOP1_64_INSN_CPSMADSLLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadslua1_w_P1, "CPSMADSLUA1_W_P1", MEPCOP1_64_INSN_CPSMADSLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmadslla1_w_P1, "CPSMADSLLA1_W_P1", MEPCOP1_64_INSN_CPSMADSLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbslua1_h_P1, "CPSMSBSLUA1_H_P1", MEPCOP1_64_INSN_CPSMSBSLUA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbslla1_h_P1, "CPSMSBSLLA1_H_P1", MEPCOP1_64_INSN_CPSMSBSLLA1_H_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V4HI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbslua1_w_P1, "CPSMSBSLUA1_W_P1", MEPCOP1_64_INSN_CPSMSBSLUA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
+ { mepcop1_64_sem_cpsmsbslla1_w_P1, "CPSMSBSLLA1_W_P1", MEPCOP1_64_INSN_CPSMSBSLLA1_W_P1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\x4" }, CPTYPE_V2SI, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_P1) } },
};
@@ -381,6 +381,10 @@ mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P
static void
mepcop1_64_extract_sfmt_cpfsftbi_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
static void
+mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpssub3_h_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
mepcop1_64_extract_sfmt_cpsrli3_b_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
static void
mepcop1_64_extract_sfmt_cpsrli3_h_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
@@ -397,11 +401,51 @@ mepcop1_64_extract_sfmt_c1nop_P1 (mepcop
static void
mepcop1_64_extract_sfmt_cpmovi_b_P0S_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
static void
+mepcop1_64_extract_sfmt_cpadda1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpaddua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpaddla1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpacsuma1_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpaccpa1_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpacswp_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpsrla1_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
mepcop1_64_extract_sfmt_cpsrlia1_1_p1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
static void
mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
static void
+mepcop1_64_extract_sfmt_cpfmuliua1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmulila1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmadiua1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmadila1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmuliua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmulila1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmadia1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmadiua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
+static void
+mepcop1_64_extract_sfmt_cpfmadila1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn);
// Fetch & decode instruction
void
@@ -961,15 +1005,15 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfff801ff) == 0x980010)
- { itype = MEPCOP1_64_INSN_CPACMPEQ_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPEQ_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfff801ff) == 0x980030)
- { itype = MEPCOP1_64_INSN_CPACMPEQ_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPEQ_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfff801ff) == 0x980050)
- { itype = MEPCOP1_64_INSN_CPACMPEQ_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPEQ_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -988,15 +1032,15 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfff801ff) == 0x980090)
- { itype = MEPCOP1_64_INSN_CPACMPNE_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPNE_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfff801ff) == 0x9800b0)
- { itype = MEPCOP1_64_INSN_CPACMPNE_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPNE_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfff801ff) == 0x9800d0)
- { itype = MEPCOP1_64_INSN_CPACMPNE_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPNE_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1019,23 +1063,23 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
if ((entire_insn & 0xfff801ff) == 0x980100)
- { itype = MEPCOP1_64_INSN_CPACMPGTU_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGTU_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 9 :
if ((entire_insn & 0xfff801ff) == 0x980110)
- { itype = MEPCOP1_64_INSN_CPACMPGT_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGT_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
if ((entire_insn & 0xfff801ff) == 0x980130)
- { itype = MEPCOP1_64_INSN_CPACMPGT_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGT_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
if ((entire_insn & 0xfff801ff) == 0x980140)
- { itype = MEPCOP1_64_INSN_CPACMPGTU_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGTU_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 13 :
if ((entire_insn & 0xfff801ff) == 0x980150)
- { itype = MEPCOP1_64_INSN_CPACMPGT_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGT_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1058,23 +1102,23 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
if ((entire_insn & 0xfff801ff) == 0x980180)
- { itype = MEPCOP1_64_INSN_CPACMPGEU_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGEU_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 9 :
if ((entire_insn & 0xfff801ff) == 0x980190)
- { itype = MEPCOP1_64_INSN_CPACMPGE_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGE_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
if ((entire_insn & 0xfff801ff) == 0x9801b0)
- { itype = MEPCOP1_64_INSN_CPACMPGE_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGE_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
if ((entire_insn & 0xfff801ff) == 0x9801c0)
- { itype = MEPCOP1_64_INSN_CPACMPGEU_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGEU_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 13 :
if ((entire_insn & 0xfff801ff) == 0x9801d0)
- { itype = MEPCOP1_64_INSN_CPACMPGE_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACMPGE_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1296,35 +1340,35 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
if ((entire_insn & 0xfff801ff) == 0xc00000)
- { itype = MEPCOP1_64_INSN_CPADDA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDA1U_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 9 :
if ((entire_insn & 0xfff801ff) == 0xc00010)
- { itype = MEPCOP1_64_INSN_CPADDA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDA1_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 10 :
if ((entire_insn & 0xfff801ff) == 0xc00020)
- { itype = MEPCOP1_64_INSN_CPADDUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDUA1_H_P1; mepcop1_64_extract_sfmt_cpaddua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
if ((entire_insn & 0xfff801ff) == 0xc00030)
- { itype = MEPCOP1_64_INSN_CPADDLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDLA1_H_P1; mepcop1_64_extract_sfmt_cpaddla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
if ((entire_insn & 0xfff801ff) == 0xc00040)
- { itype = MEPCOP1_64_INSN_CPADDACA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDACA1U_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 13 :
if ((entire_insn & 0xfff801ff) == 0xc00050)
- { itype = MEPCOP1_64_INSN_CPADDACA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDACA1_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 14 :
if ((entire_insn & 0xfff801ff) == 0xc00060)
- { itype = MEPCOP1_64_INSN_CPADDACUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDACUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 15 :
if ((entire_insn & 0xfff801ff) == 0xc00070)
- { itype = MEPCOP1_64_INSN_CPADDACLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPADDACLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1347,35 +1391,35 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
if ((entire_insn & 0xfff801ff) == 0xc00080)
- { itype = MEPCOP1_64_INSN_CPSUBA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBA1U_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 9 :
if ((entire_insn & 0xfff801ff) == 0xc00090)
- { itype = MEPCOP1_64_INSN_CPSUBA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBA1_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 10 :
if ((entire_insn & 0xfff801ff) == 0xc000a0)
- { itype = MEPCOP1_64_INSN_CPSUBUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBUA1_H_P1; mepcop1_64_extract_sfmt_cpaddua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
if ((entire_insn & 0xfff801ff) == 0xc000b0)
- { itype = MEPCOP1_64_INSN_CPSUBLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBLA1_H_P1; mepcop1_64_extract_sfmt_cpaddla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
if ((entire_insn & 0xfff801ff) == 0xc000c0)
- { itype = MEPCOP1_64_INSN_CPSUBACA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBACA1U_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 13 :
if ((entire_insn & 0xfff801ff) == 0xc000d0)
- { itype = MEPCOP1_64_INSN_CPSUBACA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBACA1_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 14 :
if ((entire_insn & 0xfff801ff) == 0xc000e0)
- { itype = MEPCOP1_64_INSN_CPSUBACUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBACUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 15 :
if ((entire_insn & 0xfff801ff) == 0xc000f0)
- { itype = MEPCOP1_64_INSN_CPSUBACLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSUBACLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1398,35 +1442,35 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 8 :
if ((entire_insn & 0xfff801ff) == 0xc00100)
- { itype = MEPCOP1_64_INSN_CPABSA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPABSA1U_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 9 :
if ((entire_insn & 0xfff801ff) == 0xc00110)
- { itype = MEPCOP1_64_INSN_CPABSA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPABSA1_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 10 :
if ((entire_insn & 0xfff801ff) == 0xc00120)
- { itype = MEPCOP1_64_INSN_CPABSUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPABSUA1_H_P1; mepcop1_64_extract_sfmt_cpaddua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
if ((entire_insn & 0xfff801ff) == 0xc00130)
- { itype = MEPCOP1_64_INSN_CPABSLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPABSLA1_H_P1; mepcop1_64_extract_sfmt_cpaddla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
if ((entire_insn & 0xfff801ff) == 0xc00140)
- { itype = MEPCOP1_64_INSN_CPSADA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSADA1U_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 13 :
if ((entire_insn & 0xfff801ff) == 0xc00150)
- { itype = MEPCOP1_64_INSN_CPSADA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSADA1_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 14 :
if ((entire_insn & 0xfff801ff) == 0xc00160)
- { itype = MEPCOP1_64_INSN_CPSADUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSADUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 15 :
if ((entire_insn & 0xfff801ff) == 0xc00170)
- { itype = MEPCOP1_64_INSN_CPSADLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSADLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1449,15 +1493,15 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 11 :
if ((entire_insn & 0xfff801ff) == 0xc001b0)
- { itype = MEPCOP1_64_INSN_CPSETA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSETA1_H_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 12 :
if ((entire_insn & 0xfff801ff) == 0xc001c0)
- { itype = MEPCOP1_64_INSN_CPSETUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSETUA1_W_P1; mepcop1_64_extract_sfmt_cpaddua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 13 :
if ((entire_insn & 0xfff801ff) == 0xc001d0)
- { itype = MEPCOP1_64_INSN_CPSETLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSETLA1_W_P1; mepcop1_64_extract_sfmt_cpaddla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1564,27 +1608,27 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 48 :
if ((entire_insn & 0xffffffff) == 0xc82000)
- { itype = MEPCOP1_64_INSN_CPACSUMA1_P1; mepcop1_64_extract_sfmt_c1nop_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACSUMA1_P1; mepcop1_64_extract_sfmt_cpacsuma1_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 49 :
if ((entire_insn & 0xffffffff) == 0xc82200)
- { itype = MEPCOP1_64_INSN_CPACCPA1_P1; mepcop1_64_extract_sfmt_c1nop_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACCPA1_P1; mepcop1_64_extract_sfmt_cpaccpa1_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 50 :
if ((entire_insn & 0xffffffff) == 0xc82400)
- { itype = MEPCOP1_64_INSN_CPACSWP_P1; mepcop1_64_extract_sfmt_c1nop_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPACSWP_P1; mepcop1_64_extract_sfmt_cpacswp_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 56 :
if ((entire_insn & 0xfff83fff) == 0xc83000)
- { itype = MEPCOP1_64_INSN_CPSRLA1_P1; mepcop1_64_extract_sfmt_cpmovtocsar0_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSRLA1_P1; mepcop1_64_extract_sfmt_cpsrla1_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 57 :
if ((entire_insn & 0xfff83fff) == 0xc83200)
- { itype = MEPCOP1_64_INSN_CPSRAA1_P1; mepcop1_64_extract_sfmt_cpmovtocsar0_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSRAA1_P1; mepcop1_64_extract_sfmt_cpsrla1_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 58 :
if ((entire_insn & 0xfff83fff) == 0xc83400)
- { itype = MEPCOP1_64_INSN_CPSLLA1_P1; mepcop1_64_extract_sfmt_cpmovtocsar0_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSLLA1_P1; mepcop1_64_extract_sfmt_cpsrla1_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 60 :
if ((entire_insn & 0xfffffe0f) == 0xc83800)
@@ -1775,7 +1819,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xf8018f) == 0xe00100)
- { itype = MEPCOP1_64_INSN_CPFMULIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmuliua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1791,7 +1835,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xf8018f) == 0xe00180)
- { itype = MEPCOP1_64_INSN_CPFMULILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulila1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1807,7 +1851,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xf8018f) == 0xe80000)
- { itype = MEPCOP1_64_INSN_CPFMADIA1U_B_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1U_B_P1; mepcop1_64_extract_sfmt_cpfmadia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1823,7 +1867,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xf8018f) == 0xe80080)
- { itype = MEPCOP1_64_INSN_CPFMADIA1_B_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1_B_P1; mepcop1_64_extract_sfmt_cpfmadia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1839,7 +1883,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xf8018f) == 0xe80100)
- { itype = MEPCOP1_64_INSN_CPFMADIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmadiua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1855,7 +1899,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xf8018f) == 0xe80180)
- { itype = MEPCOP1_64_INSN_CPFMADILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADILA1_H_P1; mepcop1_64_extract_sfmt_cpfmadila1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1867,19 +1911,19 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0xf00000)
- { itype = MEPCOP1_64_INSN_CPSSQA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSSQA1U_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0xf00010)
- { itype = MEPCOP1_64_INSN_CPSSQA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSSQA1_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0xf00040)
- { itype = MEPCOP1_64_INSN_CPSSDA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSSDA1U_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0xf00050)
- { itype = MEPCOP1_64_INSN_CPSSDA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSSDA1_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1891,35 +1935,35 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0xf00080)
- { itype = MEPCOP1_64_INSN_CPMULA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULA1U_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0xf00090)
- { itype = MEPCOP1_64_INSN_CPMULA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULA1_B_P1; mepcop1_64_extract_sfmt_cpadda1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0xf000a0)
- { itype = MEPCOP1_64_INSN_CPMULUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULUA1_H_P1; mepcop1_64_extract_sfmt_cpaddua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0xf000b0)
- { itype = MEPCOP1_64_INSN_CPMULLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULLA1_H_P1; mepcop1_64_extract_sfmt_cpaddla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfff801ff) == 0xf000c0)
- { itype = MEPCOP1_64_INSN_CPMULUA1U_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULUA1U_W_P1; mepcop1_64_extract_sfmt_cpaddua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfff801ff) == 0xf000d0)
- { itype = MEPCOP1_64_INSN_CPMULLA1U_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULLA1U_W_P1; mepcop1_64_extract_sfmt_cpaddla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfff801ff) == 0xf000e0)
- { itype = MEPCOP1_64_INSN_CPMULUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULUA1_W_P1; mepcop1_64_extract_sfmt_cpaddua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfff801ff) == 0xf000f0)
- { itype = MEPCOP1_64_INSN_CPMULLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULLA1_W_P1; mepcop1_64_extract_sfmt_cpaddla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1931,35 +1975,35 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0xf00100)
- { itype = MEPCOP1_64_INSN_CPMADA1U_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADA1U_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0xf00110)
- { itype = MEPCOP1_64_INSN_CPMADA1_B_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADA1_B_P1; mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0xf00120)
- { itype = MEPCOP1_64_INSN_CPMADUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0xf00130)
- { itype = MEPCOP1_64_INSN_CPMADLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfff801ff) == 0xf00140)
- { itype = MEPCOP1_64_INSN_CPMADUA1U_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADUA1U_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfff801ff) == 0xf00150)
- { itype = MEPCOP1_64_INSN_CPMADLA1U_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADLA1U_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfff801ff) == 0xf00160)
- { itype = MEPCOP1_64_INSN_CPMADUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADUA1_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfff801ff) == 0xf00170)
- { itype = MEPCOP1_64_INSN_CPMADLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMADLA1_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -1971,27 +2015,27 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 2 :
if ((entire_insn & 0xfff801ff) == 0xf001a0)
- { itype = MEPCOP1_64_INSN_CPMSBUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMSBUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0xf001b0)
- { itype = MEPCOP1_64_INSN_CPMSBLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMSBLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfff801ff) == 0xf001c0)
- { itype = MEPCOP1_64_INSN_CPMSBUA1U_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMSBUA1U_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfff801ff) == 0xf001d0)
- { itype = MEPCOP1_64_INSN_CPMSBLA1U_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMSBLA1U_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xfff801ff) == 0xf001e0)
- { itype = MEPCOP1_64_INSN_CPMSBUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMSBUA1_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xfff801ff) == 0xf001f0)
- { itype = MEPCOP1_64_INSN_CPMSBLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMSBLA1_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2042,27 +2086,27 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xf801ff) == 0xf80020)
- { itype = MEPCOP1_64_INSN_CPFMULIUA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULIUA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmuliua1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xf801ff) == 0xf80030)
- { itype = MEPCOP1_64_INSN_CPFMULILA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULILA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmulila1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xf801ff) == 0xf80040)
- { itype = MEPCOP1_64_INSN_CPFMADIA1S0U_B_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1S0U_B_P1; mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xf801ff) == 0xf80050)
- { itype = MEPCOP1_64_INSN_CPFMADIA1S0_B_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1S0_B_P1; mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xf801ff) == 0xf80060)
- { itype = MEPCOP1_64_INSN_CPFMADIUA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIUA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmadiua1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xf801ff) == 0xf80070)
- { itype = MEPCOP1_64_INSN_CPFMADILA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADILA1S0_H_P1; mepcop1_64_extract_sfmt_cpfmadila1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2113,27 +2157,27 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xf801ff) == 0xf800a0)
- { itype = MEPCOP1_64_INSN_CPFMULIUA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULIUA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmuliua1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xf801ff) == 0xf800b0)
- { itype = MEPCOP1_64_INSN_CPFMULILA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULILA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmulila1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xf801ff) == 0xf800c0)
- { itype = MEPCOP1_64_INSN_CPFMADIA1S1U_B_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1S1U_B_P1; mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xf801ff) == 0xf800d0)
- { itype = MEPCOP1_64_INSN_CPFMADIA1S1_B_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1S1_B_P1; mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xf801ff) == 0xf800e0)
- { itype = MEPCOP1_64_INSN_CPFMADIUA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIUA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmadiua1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xf801ff) == 0xf800f0)
- { itype = MEPCOP1_64_INSN_CPFMADILA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADILA1S1_H_P1; mepcop1_64_extract_sfmt_cpfmadila1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2184,27 +2228,27 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xf801ff) == 0xf80120)
- { itype = MEPCOP1_64_INSN_CPAMULIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPAMULIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmuliua1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xf801ff) == 0xf80130)
- { itype = MEPCOP1_64_INSN_CPAMULILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPAMULILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulila1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xf801ff) == 0xf80140)
- { itype = MEPCOP1_64_INSN_CPAMADIA1U_B_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPAMADIA1U_B_P1; mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xf801ff) == 0xf80150)
- { itype = MEPCOP1_64_INSN_CPAMADIA1_B_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPAMADIA1_B_P1; mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 6 :
if ((entire_insn & 0xf801ff) == 0xf80160)
- { itype = MEPCOP1_64_INSN_CPAMADIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPAMADIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmadiua1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 7 :
if ((entire_insn & 0xf801ff) == 0xf80170)
- { itype = MEPCOP1_64_INSN_CPAMADILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPAMADILA1_H_P1; mepcop1_64_extract_sfmt_cpfmadila1s0_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2216,15 +2260,15 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x1980010)
- { itype = MEPCOP1_64_INSN_CPOCMPEQ_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPEQ_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x1980030)
- { itype = MEPCOP1_64_INSN_CPOCMPEQ_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPEQ_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0x1980050)
- { itype = MEPCOP1_64_INSN_CPOCMPEQ_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPEQ_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2236,15 +2280,15 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x1980090)
- { itype = MEPCOP1_64_INSN_CPOCMPNE_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPNE_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x19800b0)
- { itype = MEPCOP1_64_INSN_CPOCMPNE_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPNE_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0x19800d0)
- { itype = MEPCOP1_64_INSN_CPOCMPNE_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPNE_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2256,23 +2300,23 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x1980100)
- { itype = MEPCOP1_64_INSN_CPOCMPGTU_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGTU_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x1980110)
- { itype = MEPCOP1_64_INSN_CPOCMPGT_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGT_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0x1980130)
- { itype = MEPCOP1_64_INSN_CPOCMPGT_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGT_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfff801ff) == 0x1980140)
- { itype = MEPCOP1_64_INSN_CPOCMPGTU_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGTU_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfff801ff) == 0x1980150)
- { itype = MEPCOP1_64_INSN_CPOCMPGT_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGT_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -2284,23 +2328,23 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x1980180)
- { itype = MEPCOP1_64_INSN_CPOCMPGEU_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGEU_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x1980190)
- { itype = MEPCOP1_64_INSN_CPOCMPGE_B_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGE_B_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0x19801b0)
- { itype = MEPCOP1_64_INSN_CPOCMPGE_H_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGE_H_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 4 :
if ((entire_insn & 0xfff801ff) == 0x19801c0)
- { itype = MEPCOP1_64_INSN_CPOCMPGEU_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGEU_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 5 :
if ((entire_insn & 0xfff801ff) == 0x19801d0)
- { itype = MEPCOP1_64_INSN_CPOCMPGE_W_P0_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPOCMPGE_W_P0_P1; mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -3028,7 +3072,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
case 1970 : /* fall through */
case 2034 :
if ((entire_insn & 0xf8018f) == 0xe00100)
- { itype = MEPCOP1_64_INSN_CPFMULIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmuliua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 115 : /* fall through */
case 179 : /* fall through */
@@ -3062,7 +3106,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
case 1971 : /* fall through */
case 2035 :
if ((entire_insn & 0xf8018f) == 0xe00180)
- { itype = MEPCOP1_64_INSN_CPFMULILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMULILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulila1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 116 : /* fall through */
case 180 : /* fall through */
@@ -3096,7 +3140,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
case 1972 : /* fall through */
case 2036 :
if ((entire_insn & 0xf8018f) == 0xe80000)
- { itype = MEPCOP1_64_INSN_CPFMADIA1U_B_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1U_B_P1; mepcop1_64_extract_sfmt_cpfmadia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 117 : /* fall through */
case 181 : /* fall through */
@@ -3130,7 +3174,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
case 1973 : /* fall through */
case 2037 :
if ((entire_insn & 0xf8018f) == 0xe80080)
- { itype = MEPCOP1_64_INSN_CPFMADIA1_B_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIA1_B_P1; mepcop1_64_extract_sfmt_cpfmadia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 118 : /* fall through */
case 182 : /* fall through */
@@ -3164,7 +3208,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
case 1974 : /* fall through */
case 2038 :
if ((entire_insn & 0xf8018f) == 0xe80100)
- { itype = MEPCOP1_64_INSN_CPFMADIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADIUA1_H_P1; mepcop1_64_extract_sfmt_cpfmadiua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 119 : /* fall through */
case 183 : /* fall through */
@@ -3198,7 +3242,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
case 1975 : /* fall through */
case 2039 :
if ((entire_insn & 0xf8018f) == 0xe80180)
- { itype = MEPCOP1_64_INSN_CPFMADILA1_H_P1; mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPFMADILA1_H_P1; mepcop1_64_extract_sfmt_cpfmadila1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 122 :
{
@@ -3207,19 +3251,19 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x1f00120)
- { itype = MEPCOP1_64_INSN_CPSMADUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x1f00130)
- { itype = MEPCOP1_64_INSN_CPSMADLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0x1f00160)
- { itype = MEPCOP1_64_INSN_CPSMADUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADUA1_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0x1f00170)
- { itype = MEPCOP1_64_INSN_CPSMADLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADLA1_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -3231,19 +3275,19 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x1f001a0)
- { itype = MEPCOP1_64_INSN_CPSMSBUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x1f001b0)
- { itype = MEPCOP1_64_INSN_CPSMSBLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0x1f001e0)
- { itype = MEPCOP1_64_INSN_CPSMSBUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBUA1_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0x1f001f0)
- { itype = MEPCOP1_64_INSN_CPSMSBLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBLA1_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -3274,19 +3318,19 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x2f000a0)
- { itype = MEPCOP1_64_INSN_CPMULSLUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULSLUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x2f000b0)
- { itype = MEPCOP1_64_INSN_CPMULSLLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULSLLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0x2f000e0)
- { itype = MEPCOP1_64_INSN_CPMULSLUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULSLUA1_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0x2f000f0)
- { itype = MEPCOP1_64_INSN_CPMULSLLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPMULSLLA1_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -3317,19 +3361,19 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x3f00120)
- { itype = MEPCOP1_64_INSN_CPSMADSLUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADSLUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x3f00130)
- { itype = MEPCOP1_64_INSN_CPSMADSLLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADSLLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0x3f00160)
- { itype = MEPCOP1_64_INSN_CPSMADSLUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADSLUA1_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0x3f00170)
- { itype = MEPCOP1_64_INSN_CPSMADSLLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMADSLLA1_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -3341,19 +3385,19 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff801ff) == 0x3f001a0)
- { itype = MEPCOP1_64_INSN_CPSMSBSLUA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBSLUA1_H_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff801ff) == 0x3f001b0)
- { itype = MEPCOP1_64_INSN_CPSMSBSLLA1_H_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBSLLA1_H_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 2 :
if ((entire_insn & 0xfff801ff) == 0x3f001e0)
- { itype = MEPCOP1_64_INSN_CPSMSBSLUA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBSLUA1_W_P1; mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 3 :
if ((entire_insn & 0xfff801ff) == 0x3f001f0)
- { itype = MEPCOP1_64_INSN_CPSMSBSLLA1_W_P1; mepcop1_64_extract_sfmt_cpcmpeqz_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSMSBSLLA1_W_P1; mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
default : itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
}
@@ -3546,7 +3590,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff8000f) == 0xea00000)
- { itype = MEPCOP1_64_INSN_CPSSUB3_H_P0_P1; mepcop1_64_extract_sfmt_cpadd3_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSSUB3_H_P0_P1; mepcop1_64_extract_sfmt_cpssub3_h_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff8000f) == 0x4ea00000)
@@ -3565,7 +3609,7 @@ mepcop1_64_scache::decode (mep_ext1_cpu*
{
case 0 :
if ((entire_insn & 0xfff8000f) == 0xfa00000)
- { itype = MEPCOP1_64_INSN_CPSSUB3_W_P0_P1; mepcop1_64_extract_sfmt_cpadd3_b_P0S_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
+ { itype = MEPCOP1_64_INSN_CPSSUB3_W_P0_P1; mepcop1_64_extract_sfmt_cpssub3_h_P0_P1 (this, current_cpu, pc, base_insn, entire_insn); goto done; }
itype = MEPCOP1_64_INSN_X_INVALID; mepcop1_64_extract_sfmt_empty (this, current_cpu, pc, base_insn, entire_insn); goto done;
case 1 :
if ((entire_insn & 0xfff8000f) == 0x2fa00000)
@@ -4103,6 +4147,68 @@ mepcop1_64_extract_sfmt_cpfsftbi_P0_P1 (
}
void
+mepcop1_64_extract_sfmt_cpacmpeq_b_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpacmpeq_b_P0_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpssub3_h_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfsftbi_P0_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_5u23;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_5u23 = EXTRACT_MSB0_UINT (insn, 32, 23, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_5u23) = f_ivc2_5u23;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpssub3_h_P0_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_5u23:0x" << hex << f_ivc2_5u23 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
mepcop1_64_extract_sfmt_cpsrli3_b_P0_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
mepcop1_64_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cpfsftbi_P0_P1.f
@@ -4355,20 +4461,24 @@ mepcop1_64_extract_sfmt_cpmovi_b_P0S_P1
}
void
-mepcop1_64_extract_sfmt_cpsrlia1_1_p1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+mepcop1_64_extract_sfmt_cpadda1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
mepcop1_64_insn_word insn = entire_insn;
-#define FLD(f) abuf->fields.sfmt_cdsrli3_P0_P1.f
- UINT f_ivc2_5u23;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
- f_ivc2_5u23 = EXTRACT_MSB0_UINT (insn, 32, 23, 5);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
/* Record the fields for the semantic handler. */
- FLD (f_ivc2_5u23) = f_ivc2_5u23;
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
if (UNLIKELY(current_cpu->trace_extract_p))
{
current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_cpsrlia1_1_p1)\t"
- << " f_ivc2_5u23:0x" << hex << f_ivc2_5u23 << dec
+ << "0x" << hex << pc << dec << " (sfmt_cpadda1u_b_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
<< endl;
}
@@ -4380,28 +4490,24 @@ mepcop1_64_extract_sfmt_cpsrlia1_1_p1 (m
}
void
-mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+mepcop1_64_extract_sfmt_cpaddua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
mepcop1_64_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
- INT f_ivc2_8s0;
UINT f_ivc2_5u13;
UINT f_ivc2_5u18;
- f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
/* Record the fields for the semantic handler. */
FLD (f_ivc2_5u18) = f_ivc2_5u18;
FLD (f_ivc2_5u13) = f_ivc2_5u13;
- FLD (f_ivc2_8s0) = f_ivc2_8s0;
if (UNLIKELY(current_cpu->trace_extract_p))
{
current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_cpfmulia1s0u_b_P1)\t"
+ << "0x" << hex << pc << dec << " (sfmt_cpaddua1_h_P1)\t"
<< " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
<< " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
- << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
<< endl;
}
@@ -4413,28 +4519,640 @@ mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P
}
void
-mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+mepcop1_64_extract_sfmt_cpaddla1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
mepcop1_64_insn_word insn = entire_insn;
#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
- INT f_ivc2_8s0;
UINT f_ivc2_5u13;
UINT f_ivc2_5u18;
- UINT f_ivc2_3u25;
- f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
- f_ivc2_3u25 = EXTRACT_MSB0_UINT (insn, 32, 25, 3);
/* Record the fields for the semantic handler. */
FLD (f_ivc2_5u18) = f_ivc2_5u18;
FLD (f_ivc2_5u13) = f_ivc2_5u13;
- FLD (f_ivc2_3u25) = f_ivc2_3u25;
- FLD (f_ivc2_8s0) = f_ivc2_8s0;
if (UNLIKELY(current_cpu->trace_extract_p))
{
current_cpu->trace_stream
- << "0x" << hex << pc << dec << " (sfmt_cpfmulia1u_b_P1)\t"
+ << "0x" << hex << pc << dec << " (sfmt_cpaddla1_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpaddaca1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddaca1u_b_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpaddacua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddacua1_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpaddacla1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaddacla1_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpacsuma1_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpacsuma1_P1)\t"
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpaccpa1_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpaccpa1_P1)\t"
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpacswp_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.fmt_empty.f
+
+
+ /* Record the fields for the semantic handler. */
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpacswp_P1)\t"
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpsrla1_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpmovi_b_P0S_P1.f
+ UINT f_ivc2_5u13;
+
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpsrla1_P1)\t"
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpsrlia1_1_p1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cdsrli3_P0_P1.f
+ UINT f_ivc2_5u23;
+
+ f_ivc2_5u23 = EXTRACT_MSB0_UINT (insn, 32, 23, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u23) = f_ivc2_5u23;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpsrlia1_1_p1)\t"
+ << " f_ivc2_5u23:0x" << hex << f_ivc2_5u23 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmulia1s0u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmulia1s0u_b_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmuliua1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmuliua1s0_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmulila1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmulila1s0_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmadia1s0u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmadia1s0u_b_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmadiua1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmadiua1s0_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmadila1s0_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmadila1s0_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmulia1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_3u25;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_3u25 = EXTRACT_MSB0_UINT (insn, 32, 25, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_3u25) = f_ivc2_3u25;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmulia1u_b_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_3u25:0x" << hex << f_ivc2_3u25 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmuliua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_3u25;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_3u25 = EXTRACT_MSB0_UINT (insn, 32, 25, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_3u25) = f_ivc2_3u25;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmuliua1_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_3u25:0x" << hex << f_ivc2_3u25 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmulila1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_3u25;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_3u25 = EXTRACT_MSB0_UINT (insn, 32, 25, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_3u25) = f_ivc2_3u25;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmulila1_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_3u25:0x" << hex << f_ivc2_3u25 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmadia1u_b_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_3u25;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_3u25 = EXTRACT_MSB0_UINT (insn, 32, 25, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_3u25) = f_ivc2_3u25;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmadia1u_b_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_3u25:0x" << hex << f_ivc2_3u25 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmadiua1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_3u25;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_3u25 = EXTRACT_MSB0_UINT (insn, 32, 25, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_3u25) = f_ivc2_3u25;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmadiua1_h_P1)\t"
+ << " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
+ << " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
+ << " f_ivc2_3u25:0x" << hex << f_ivc2_3u25 << dec
+ << " f_ivc2_8s0:0x" << hex << f_ivc2_8s0 << dec
+ << endl;
+ }
+
+ /* Record the fields for profiling. */
+ if (UNLIKELY (current_cpu->trace_counter_p || current_cpu->final_insn_count_p))
+ {
+ }
+#undef FLD
+}
+
+void
+mepcop1_64_extract_sfmt_cpfmadila1_h_P1 (mepcop1_64_scache* abuf, mep_ext1_cpu* current_cpu, PCADDR pc, mepcop1_64_insn_word base_insn, mepcop1_64_insn_word entire_insn){
+ mepcop1_64_insn_word insn = entire_insn;
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ INT f_ivc2_8s0;
+ UINT f_ivc2_5u13;
+ UINT f_ivc2_5u18;
+ UINT f_ivc2_3u25;
+
+ f_ivc2_8s0 = EXTRACT_MSB0_INT (insn, 32, 0, 8);
+ f_ivc2_5u13 = EXTRACT_MSB0_UINT (insn, 32, 13, 5);
+ f_ivc2_5u18 = EXTRACT_MSB0_UINT (insn, 32, 18, 5);
+ f_ivc2_3u25 = EXTRACT_MSB0_UINT (insn, 32, 25, 3);
+
+ /* Record the fields for the semantic handler. */
+ FLD (f_ivc2_5u18) = f_ivc2_5u18;
+ FLD (f_ivc2_5u13) = f_ivc2_5u13;
+ FLD (f_ivc2_3u25) = f_ivc2_3u25;
+ FLD (f_ivc2_8s0) = f_ivc2_8s0;
+ if (UNLIKELY(current_cpu->trace_extract_p))
+ {
+ current_cpu->trace_stream
+ << "0x" << hex << pc << dec << " (sfmt_cpfmadila1_h_P1)\t"
<< " f_ivc2_5u18:0x" << hex << f_ivc2_5u18 << dec
<< " f_ivc2_5u13:0x" << hex << f_ivc2_5u13 << dec
<< " f_ivc2_3u25:0x" << hex << f_ivc2_3u25 << dec
Index: sid/component/cgen-cpu/mep/mep-cop1-64-sem.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cop1-64-sem.cxx,v
retrieving revision 1.2
diff -p -U3 -r1.2 mep-cop1-64-sem.cxx
--- sid/component/cgen-cpu/mep/mep-cop1-64-sem.cxx 22 May 2009 17:37:44 -0000 1.2
+++ sid/component/cgen-cpu/mep/mep-cop1-64-sem.cxx 24 Jun 2009 02:59:30 -0000
@@ -704,7 +704,12 @@ mepcop1_64_sem_cpccadd_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpccadd_b (pc, FLD (f_ivc2_5u13));
+ {
+ DI opval = current_cpu->ivc2_cpccadd_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u13) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_cr64_set (FLD (f_ivc2_5u13), opval);
+ }
}
current_cpu->done_insn (npc, status);
@@ -1386,6 +1391,12 @@ mepcop1_64_sem_cpcmpeqz_b_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeqz_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1408,6 +1419,12 @@ mepcop1_64_sem_cpcmpeq_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1430,6 +1447,12 @@ mepcop1_64_sem_cpcmpeq_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1452,6 +1475,12 @@ mepcop1_64_sem_cpcmpeq_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpeq_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1474,6 +1503,12 @@ mepcop1_64_sem_cpcmpne_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1496,6 +1531,12 @@ mepcop1_64_sem_cpcmpne_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1518,6 +1559,12 @@ mepcop1_64_sem_cpcmpne_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpne_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1540,6 +1587,12 @@ mepcop1_64_sem_cpcmpgtu_b_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgtu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1562,6 +1615,12 @@ mepcop1_64_sem_cpcmpgt_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1584,6 +1643,12 @@ mepcop1_64_sem_cpcmpgt_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1606,6 +1671,12 @@ mepcop1_64_sem_cpcmpgtu_w_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgtu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1628,6 +1699,12 @@ mepcop1_64_sem_cpcmpgt_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgt_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1650,6 +1727,12 @@ mepcop1_64_sem_cpcmpgeu_b_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgeu_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1672,6 +1755,12 @@ mepcop1_64_sem_cpcmpge_b_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1694,6 +1783,12 @@ mepcop1_64_sem_cpcmpge_h_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1716,6 +1811,12 @@ mepcop1_64_sem_cpcmpgeu_w_P0S_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpgeu_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -1738,6 +1839,12 @@ mepcop1_64_sem_cpcmpge_w_P0S_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 1) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 1), opval);
+ }
current_cpu->ivc2_cpcmpge_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -2681,6 +2788,12 @@ mepcop1_64_sem_cpssub3_h_P0_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
{
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 4) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 4), opval);
+ }
+ {
DI opval = current_cpu->ivc2_cpssub3_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u23) << ']' << ":=0x" << hex << opval << dec << " ";
@@ -2708,6 +2821,12 @@ mepcop1_64_sem_cpssub3_w_P0_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
{
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 4) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 4), opval);
+ }
+ {
DI opval = current_cpu->ivc2_cpssub3_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
if (UNLIKELY(current_cpu->trace_result_p))
current_cpu->trace_stream << "cr64" << '[' << FLD (f_ivc2_5u23) << ']' << ":=0x" << hex << opval << dec << " ";
@@ -4997,6 +5116,54 @@ mepcop1_64_sem_cpadda1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpadda1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5019,6 +5186,54 @@ mepcop1_64_sem_cpadda1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpadda1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5041,6 +5256,30 @@ mepcop1_64_sem_cpaddua1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpaddua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5063,6 +5302,30 @@ mepcop1_64_sem_cpaddla1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpaddla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5085,6 +5348,60 @@ mepcop1_64_sem_cpaddaca1u_b_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpaddaca1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5107,6 +5424,60 @@ mepcop1_64_sem_cpaddaca1_b_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpaddaca1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5129,6 +5500,36 @@ mepcop1_64_sem_cpaddacua1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpaddacua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5151,6 +5552,36 @@ mepcop1_64_sem_cpaddacla1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpaddacla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5173,6 +5604,54 @@ mepcop1_64_sem_cpsuba1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsuba1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5195,20 +5674,68 @@ mepcop1_64_sem_cpsuba1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpsuba1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
-}
-
- current_cpu->done_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** cpsubua1_h_P1: cpsubua1.h $crqp,$crpp
-
-sem_status
-mepcop1_64_sem_cpsubua1_h_P1 (mep_ext1_cpu* current_cpu, mepcop1_64_scache* sem)
-{
-#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+current_cpu->ivc2_cpsuba1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** cpsubua1_h_P1: cpsubua1.h $crqp,$crpp
+
+sem_status
+mepcop1_64_sem_cpsubua1_h_P1 (mep_ext1_cpu* current_cpu, mepcop1_64_scache* sem)
+{
+#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
sem_status status = SEM_STATUS_NORMAL;
mepcop1_64_scache* abuf = sem;
unsigned long long written = 0;
@@ -5217,6 +5744,30 @@ mepcop1_64_sem_cpsubua1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsubua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5239,6 +5790,30 @@ mepcop1_64_sem_cpsubla1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpsubla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5261,6 +5836,60 @@ mepcop1_64_sem_cpsubaca1u_b_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubaca1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5283,6 +5912,60 @@ mepcop1_64_sem_cpsubaca1_b_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubaca1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5305,6 +5988,36 @@ mepcop1_64_sem_cpsubacua1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubacua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5327,6 +6040,36 @@ mepcop1_64_sem_cpsubacla1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsubacla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5349,6 +6092,54 @@ mepcop1_64_sem_cpabsa1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpabsa1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5371,6 +6162,54 @@ mepcop1_64_sem_cpabsa1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpabsa1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5393,6 +6232,30 @@ mepcop1_64_sem_cpabsua1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpabsua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5415,6 +6278,30 @@ mepcop1_64_sem_cpabsla1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpabsla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5437,6 +6324,60 @@ mepcop1_64_sem_cpsada1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsada1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5459,17 +6400,71 @@ mepcop1_64_sem_cpsada1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
-current_cpu->ivc2_cpsada1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
-}
-
- current_cpu->done_insn (npc, status);
- return status;
-#undef FLD
-}
-
-// ********** cpsadua1_h_P1: cpsadua1.h $crqp,$crpp
-
-sem_status
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
+current_cpu->ivc2_cpsada1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
+}
+
+ current_cpu->done_insn (npc, status);
+ return status;
+#undef FLD
+}
+
+// ********** cpsadua1_h_P1: cpsadua1.h $crqp,$crpp
+
+sem_status
mepcop1_64_sem_cpsadua1_h_P1 (mep_ext1_cpu* current_cpu, mepcop1_64_scache* sem)
{
#define FLD(f) abuf->fields.sfmt_cpfmulia1u_b_P1.f
@@ -5481,6 +6476,36 @@ mepcop1_64_sem_cpsadua1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsadua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5503,6 +6528,36 @@ mepcop1_64_sem_cpsadla1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsadla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5525,6 +6580,54 @@ mepcop1_64_sem_cpseta1_h_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpseta1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5547,6 +6650,30 @@ mepcop1_64_sem_cpsetua1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsetua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5569,6 +6696,30 @@ mepcop1_64_sem_cpsetla1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpsetla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -5996,6 +7147,60 @@ mepcop1_64_sem_cpacsuma1_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpacsuma1 (pc);
}
@@ -6018,6 +7223,54 @@ mepcop1_64_sem_cpaccpa1_P1 (mep_ext1_cpu
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpaccpa1 (pc);
}
@@ -6040,6 +7293,102 @@ mepcop1_64_sem_cpacswp_P1 (mep_ext1_cpu*
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 16) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 16), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 17) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 17), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 18) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 18), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 19) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 19), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 20) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 20), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 21) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 21), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 22) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 22), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 23) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 23), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpacswp (pc);
}
@@ -6062,6 +7411,54 @@ mepcop1_64_sem_cpsrla1_P1 (mep_ext1_cpu*
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsrla1 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
}
@@ -6084,6 +7481,54 @@ mepcop1_64_sem_cpsraa1_P1 (mep_ext1_cpu*
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsraa1 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
}
@@ -6106,6 +7551,54 @@ mepcop1_64_sem_cpslla1_P1 (mep_ext1_cpu*
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpslla1 (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)]);
}
@@ -6128,6 +7621,54 @@ mepcop1_64_sem_cpsrlia1_1_p1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsrlia1 (pc, FLD (f_ivc2_5u23));
}
@@ -6150,6 +7691,54 @@ mepcop1_64_sem_cpsraia1_1_p1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsraia1 (pc, FLD (f_ivc2_5u23));
}
@@ -6172,6 +7761,54 @@ mepcop1_64_sem_cpsllia1_1_p1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpsllia1 (pc, FLD (f_ivc2_5u23));
}
@@ -6194,6 +7831,54 @@ mepcop1_64_sem_cpfmulia1s0u_b_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmulia1s0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6216,6 +7901,54 @@ mepcop1_64_sem_cpfmulia1s0_b_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmulia1s0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6238,6 +7971,30 @@ mepcop1_64_sem_cpfmuliua1s0_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmuliua1s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6260,6 +8017,30 @@ mepcop1_64_sem_cpfmulila1s0_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpfmulila1s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6282,6 +8063,60 @@ mepcop1_64_sem_cpfmadia1s0u_b_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadia1s0u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6304,6 +8139,60 @@ mepcop1_64_sem_cpfmadia1s0_b_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadia1s0_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6326,6 +8215,36 @@ mepcop1_64_sem_cpfmadiua1s0_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadiua1s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6348,6 +8267,36 @@ mepcop1_64_sem_cpfmadila1s0_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadila1s0_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6370,6 +8319,54 @@ mepcop1_64_sem_cpfmulia1s1u_b_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmulia1s1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6392,6 +8389,54 @@ mepcop1_64_sem_cpfmulia1s1_b_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmulia1s1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6414,6 +8459,30 @@ mepcop1_64_sem_cpfmuliua1s1_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmuliua1s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6436,6 +8505,30 @@ mepcop1_64_sem_cpfmulila1s1_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpfmulila1s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6458,6 +8551,60 @@ mepcop1_64_sem_cpfmadia1s1u_b_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadia1s1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6480,6 +8627,60 @@ mepcop1_64_sem_cpfmadia1s1_b_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadia1s1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6502,6 +8703,36 @@ mepcop1_64_sem_cpfmadiua1s1_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadiua1s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6524,6 +8755,36 @@ mepcop1_64_sem_cpfmadila1s1_h_P1 (mep_ex
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadila1s1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6546,6 +8807,54 @@ mepcop1_64_sem_cpamulia1u_b_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpamulia1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6568,6 +8877,54 @@ mepcop1_64_sem_cpamulia1_b_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpamulia1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6590,6 +8947,30 @@ mepcop1_64_sem_cpamuliua1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpamuliua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6612,6 +8993,30 @@ mepcop1_64_sem_cpamulila1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpamulila1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6634,6 +9039,60 @@ mepcop1_64_sem_cpamadia1u_b_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpamadia1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6656,6 +9115,60 @@ mepcop1_64_sem_cpamadia1_b_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpamadia1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6678,6 +9191,36 @@ mepcop1_64_sem_cpamadiua1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpamadiua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6700,6 +9243,36 @@ mepcop1_64_sem_cpamadila1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpamadila1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_8s0));
}
@@ -6722,6 +9295,54 @@ mepcop1_64_sem_cpfmulia1u_b_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmulia1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6744,6 +9365,54 @@ mepcop1_64_sem_cpfmulia1_b_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmulia1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6766,6 +9435,30 @@ mepcop1_64_sem_cpfmuliua1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpfmuliua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6788,6 +9481,30 @@ mepcop1_64_sem_cpfmulila1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpfmulila1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6810,6 +9527,60 @@ mepcop1_64_sem_cpfmadia1u_b_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadia1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6832,6 +9603,60 @@ mepcop1_64_sem_cpfmadia1_b_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadia1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6854,6 +9679,36 @@ mepcop1_64_sem_cpfmadiua1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadiua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6876,6 +9731,36 @@ mepcop1_64_sem_cpfmadila1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpfmadila1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)], FLD (f_ivc2_3u25), FLD (f_ivc2_8s0));
}
@@ -6898,6 +9783,54 @@ mepcop1_64_sem_cpssqa1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpssqa1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -6920,6 +9853,54 @@ mepcop1_64_sem_cpssqa1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpssqa1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -6942,6 +9923,54 @@ mepcop1_64_sem_cpssda1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpssda1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -6964,6 +9993,54 @@ mepcop1_64_sem_cpssda1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpssda1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -6986,6 +10063,54 @@ mepcop1_64_sem_cpmula1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmula1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7008,6 +10133,54 @@ mepcop1_64_sem_cpmula1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmula1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7030,6 +10203,30 @@ mepcop1_64_sem_cpmulua1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmulua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7052,6 +10249,30 @@ mepcop1_64_sem_cpmulla1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpmulla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7074,6 +10295,30 @@ mepcop1_64_sem_cpmulua1u_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmulua1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7096,6 +10341,30 @@ mepcop1_64_sem_cpmulla1u_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpmulla1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7118,6 +10387,30 @@ mepcop1_64_sem_cpmulua1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
current_cpu->ivc2_cpmulua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7140,6 +10433,30 @@ mepcop1_64_sem_cpmulla1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
current_cpu->ivc2_cpmulla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7162,6 +10479,60 @@ mepcop1_64_sem_cpmada1u_b_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmada1u_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7184,6 +10555,60 @@ mepcop1_64_sem_cpmada1_b_P1 (mep_ext1_cp
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmada1_b (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7206,6 +10631,36 @@ mepcop1_64_sem_cpmadua1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7228,6 +10683,36 @@ mepcop1_64_sem_cpmadla1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7250,6 +10735,36 @@ mepcop1_64_sem_cpmadua1u_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadua1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7272,6 +10787,36 @@ mepcop1_64_sem_cpmadla1u_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadla1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7294,6 +10839,36 @@ mepcop1_64_sem_cpmadua1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7316,6 +10891,36 @@ mepcop1_64_sem_cpmadla1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmadla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7338,6 +10943,36 @@ mepcop1_64_sem_cpmsbua1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7360,6 +10995,36 @@ mepcop1_64_sem_cpmsbla1_h_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7382,6 +11047,36 @@ mepcop1_64_sem_cpmsbua1u_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbua1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7404,6 +11099,36 @@ mepcop1_64_sem_cpmsbla1u_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbla1u_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7426,6 +11151,36 @@ mepcop1_64_sem_cpmsbua1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7448,6 +11203,36 @@ mepcop1_64_sem_cpmsbla1_w_P1 (mep_ext1_c
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmsbla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7470,6 +11255,36 @@ mepcop1_64_sem_cpsmadua1_h_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7492,6 +11307,36 @@ mepcop1_64_sem_cpsmadla1_h_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7514,6 +11359,36 @@ mepcop1_64_sem_cpsmadua1_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7536,6 +11411,36 @@ mepcop1_64_sem_cpsmadla1_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7558,6 +11463,36 @@ mepcop1_64_sem_cpsmsbua1_h_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7580,6 +11515,36 @@ mepcop1_64_sem_cpsmsbla1_h_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7602,6 +11567,36 @@ mepcop1_64_sem_cpsmsbua1_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7624,6 +11619,36 @@ mepcop1_64_sem_cpsmsbla1_w_P1 (mep_ext1_
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7646,6 +11671,36 @@ mepcop1_64_sem_cpmulslua1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7668,6 +11723,36 @@ mepcop1_64_sem_cpmulslla1_h_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7690,6 +11775,36 @@ mepcop1_64_sem_cpmulslua1_w_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7712,6 +11827,36 @@ mepcop1_64_sem_cpmulslla1_w_P1 (mep_ext1
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpmulslla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7734,6 +11879,36 @@ mepcop1_64_sem_cpsmadslua1_h_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7756,6 +11931,36 @@ mepcop1_64_sem_cpsmadslla1_h_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7778,6 +11983,36 @@ mepcop1_64_sem_cpsmadslua1_w_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7800,6 +12035,36 @@ mepcop1_64_sem_cpsmadslla1_w_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmadslla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7822,6 +12087,36 @@ mepcop1_64_sem_cpsmsbslua1_h_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslua1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7844,6 +12139,36 @@ mepcop1_64_sem_cpsmsbslla1_h_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslla1_h (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7866,6 +12191,36 @@ mepcop1_64_sem_cpsmsbslua1_w_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 28) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 28), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 29) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 29), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 30) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 30), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 31) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 31), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslua1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
@@ -7888,6 +12243,36 @@ mepcop1_64_sem_cpsmsbslla1_w_P1 (mep_ext
{
current_cpu->check_option_cp (pc);
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 24) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 24), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 25) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 25), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 26) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 26), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 27) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 27), opval);
+ }
+ {
+ SI opval = 0;
+ if (UNLIKELY(current_cpu->trace_result_p))
+ current_cpu->trace_stream << "ccr-ivc2" << '[' << ((UINT) 7) << ']' << ":=0x" << hex << opval << dec << " ";
+ current_cpu->h_ccr_ivc2_set (((UINT) 7), opval);
+ }
current_cpu->ivc2_cpsmsbslla1_w (pc, current_cpu->hardware.h_cr64[FLD (f_ivc2_5u13)], current_cpu->hardware.h_cr64[FLD (f_ivc2_5u18)]);
}
Index: sid/component/cgen-cpu/mep/mep-core1-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-core1-decode.cxx,v
retrieving revision 1.5
diff -p -U3 -r1.5 mep-core1-decode.cxx
--- sid/component/cgen-cpu/mep/mep-core1-decode.cxx 30 Apr 2009 21:18:37 -0000 1.5
+++ sid/component/cgen-cpu/mep/mep-core1-decode.cxx 24 Jun 2009 02:59:30 -0000
@@ -22,230 +22,230 @@ using namespace mep_ext1; // FIXME: name
mepcore1_idesc mepcore1_idesc::idesc_table[MEPCORE1_INSN_RI_26 + 1] =
{
- { mepcore1_sem_x_invalid, "X_INVALID", MEPCORE1_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x40" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_stcb_r, "STCB_R", MEPCORE1_INSN_STCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ldcb_r, "LDCB_R", MEPCORE1_INSN_LDCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_pref, "PREF", MEPCORE1_INSN_PREF, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_prefd, "PREFD", MEPCORE1_INSN_PREFD, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_casb3, "CASB3", MEPCORE1_INSN_CASB3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_cash3, "CASH3", MEPCORE1_INSN_CASH3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_casw3, "CASW3", MEPCORE1_INSN_CASW3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sbcp, "SBCP", MEPCORE1_INSN_SBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbcp, "LBCP", MEPCORE1_INSN_LBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbucp, "LBUCP", MEPCORE1_INSN_LBUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_shcp, "SHCP", MEPCORE1_INSN_SHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhcp, "LHCP", MEPCORE1_INSN_LHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhucp, "LHUCP", MEPCORE1_INSN_LHUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbucpa, "LBUCPA", MEPCORE1_INSN_LBUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhucpa, "LHUCPA", MEPCORE1_INSN_LHUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbucpm0, "LBUCPM0", MEPCORE1_INSN_LBUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhucpm0, "LHUCPM0", MEPCORE1_INSN_LHUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbucpm1, "LBUCPM1", MEPCORE1_INSN_LBUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhucpm1, "LHUCPM1", MEPCORE1_INSN_LHUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_uci, "UCI", MEPCORE1_INSN_UCI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_dsp, "DSP", MEPCORE1_INSN_DSP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sb, "SB", MEPCORE1_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sh, "SH", MEPCORE1_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sw, "SW", MEPCORE1_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lb, "LB", MEPCORE1_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lh, "LH", MEPCORE1_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lw, "LW", MEPCORE1_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbu, "LBU", MEPCORE1_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhu, "LHU", MEPCORE1_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sw_sp, "SW_SP", MEPCORE1_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lw_sp, "LW_SP", MEPCORE1_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sb_tp, "SB_TP", MEPCORE1_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sh_tp, "SH_TP", MEPCORE1_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sw_tp, "SW_TP", MEPCORE1_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lb_tp, "LB_TP", MEPCORE1_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lh_tp, "LH_TP", MEPCORE1_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lw_tp, "LW_TP", MEPCORE1_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbu_tp, "LBU_TP", MEPCORE1_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhu_tp, "LHU_TP", MEPCORE1_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sb16, "SB16", MEPCORE1_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sh16, "SH16", MEPCORE1_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sw16, "SW16", MEPCORE1_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lb16, "LB16", MEPCORE1_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lh16, "LH16", MEPCORE1_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lw16, "LW16", MEPCORE1_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbu16, "LBU16", MEPCORE1_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhu16, "LHU16", MEPCORE1_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sw24, "SW24", MEPCORE1_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lw24, "LW24", MEPCORE1_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_extb, "EXTB", MEPCORE1_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_exth, "EXTH", MEPCORE1_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_extub, "EXTUB", MEPCORE1_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_extuh, "EXTUH", MEPCORE1_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ssarb, "SSARB", MEPCORE1_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_mov, "MOV", MEPCORE1_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_movi8, "MOVI8", MEPCORE1_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_movi16, "MOVI16", MEPCORE1_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_movu24, "MOVU24", MEPCORE1_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_movu16, "MOVU16", MEPCORE1_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_movh, "MOVH", MEPCORE1_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_add3, "ADD3", MEPCORE1_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_add, "ADD", MEPCORE1_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_add3i, "ADD3I", MEPCORE1_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_advck3, "ADVCK3", MEPCORE1_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sub, "SUB", MEPCORE1_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sbvck3, "SBVCK3", MEPCORE1_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_neg, "NEG", MEPCORE1_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_slt3, "SLT3", MEPCORE1_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sltu3, "SLTU3", MEPCORE1_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_slt3i, "SLT3I", MEPCORE1_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sltu3i, "SLTU3I", MEPCORE1_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sl1ad3, "SL1AD3", MEPCORE1_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sl2ad3, "SL2AD3", MEPCORE1_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_add3x, "ADD3X", MEPCORE1_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_slt3x, "SLT3X", MEPCORE1_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sltu3x, "SLTU3X", MEPCORE1_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_or, "OR", MEPCORE1_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_and, "AND", MEPCORE1_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_xor, "XOR", MEPCORE1_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_nor, "NOR", MEPCORE1_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_or3, "OR3", MEPCORE1_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_and3, "AND3", MEPCORE1_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_xor3, "XOR3", MEPCORE1_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sra, "SRA", MEPCORE1_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_srl, "SRL", MEPCORE1_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sll, "SLL", MEPCORE1_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_srai, "SRAI", MEPCORE1_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_srli, "SRLI", MEPCORE1_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_slli, "SLLI", MEPCORE1_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sll3, "SLL3", MEPCORE1_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_fsft, "FSFT", MEPCORE1_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bra, "BRA", MEPCORE1_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_beqz, "BEQZ", MEPCORE1_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bnez, "BNEZ", MEPCORE1_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_beqi, "BEQI", MEPCORE1_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bnei, "BNEI", MEPCORE1_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_blti, "BLTI", MEPCORE1_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bgei, "BGEI", MEPCORE1_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_beq, "BEQ", MEPCORE1_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bne, "BNE", MEPCORE1_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bsr12, "BSR12", MEPCORE1_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bsr24, "BSR24", MEPCORE1_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_jmp, "JMP", MEPCORE1_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_jmp24, "JMP24", MEPCORE1_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_jsr, "JSR", MEPCORE1_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ret, "RET", MEPCORE1_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_repeat, "REPEAT", MEPCORE1_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_erepeat, "EREPEAT", MEPCORE1_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_stc_lp, "STC_LP", MEPCORE1_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_stc_hi, "STC_HI", MEPCORE1_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_stc_lo, "STC_LO", MEPCORE1_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_stc, "STC", MEPCORE1_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ldc_lp, "LDC_LP", MEPCORE1_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ldc_hi, "LDC_HI", MEPCORE1_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ldc_lo, "LDC_LO", MEPCORE1_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ldc, "LDC", MEPCORE1_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_di, "DI", MEPCORE1_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ei, "EI", MEPCORE1_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_reti, "RETI", MEPCORE1_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_halt, "HALT", MEPCORE1_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sleep, "SLEEP", MEPCORE1_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_swi, "SWI", MEPCORE1_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_break, "BREAK", MEPCORE1_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_syncm, "SYNCM", MEPCORE1_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_stcb, "STCB", MEPCORE1_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ldcb, "LDCB", MEPCORE1_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bsetm, "BSETM", MEPCORE1_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bclrm, "BCLRM", MEPCORE1_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bnotm, "BNOTM", MEPCORE1_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_btstm, "BTSTM", MEPCORE1_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_tas, "TAS", MEPCORE1_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_cache, "CACHE", MEPCORE1_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_mul, "MUL", MEPCORE1_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_mulu, "MULU", MEPCORE1_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_mulr, "MULR", MEPCORE1_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_mulru, "MULRU", MEPCORE1_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_madd, "MADD", MEPCORE1_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_maddu, "MADDU", MEPCORE1_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_maddr, "MADDR", MEPCORE1_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_maddru, "MADDRU", MEPCORE1_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_div, "DIV", MEPCORE1_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_divu, "DIVU", MEPCORE1_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_dret, "DRET", MEPCORE1_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_dbreak, "DBREAK", MEPCORE1_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ldz, "LDZ", MEPCORE1_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_abs, "ABS", MEPCORE1_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ave, "AVE", MEPCORE1_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_min, "MIN", MEPCORE1_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_max, "MAX", MEPCORE1_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_minu, "MINU", MEPCORE1_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_maxu, "MAXU", MEPCORE1_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_clip, "CLIP", MEPCORE1_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_clipu, "CLIPU", MEPCORE1_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sadd, "SADD", MEPCORE1_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ssub, "SSUB", MEPCORE1_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_saddu, "SADDU", MEPCORE1_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ssubu, "SSUBU", MEPCORE1_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_swcp, "SWCP", MEPCORE1_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lwcp, "LWCP", MEPCORE1_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_smcp, "SMCP", MEPCORE1_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lmcp, "LMCP", MEPCORE1_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_swcpi, "SWCPI", MEPCORE1_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lwcpi, "LWCPI", MEPCORE1_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_smcpi, "SMCPI", MEPCORE1_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lmcpi, "LMCPI", MEPCORE1_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_swcp16, "SWCP16", MEPCORE1_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lwcp16, "LWCP16", MEPCORE1_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_smcp16, "SMCP16", MEPCORE1_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lmcp16, "LMCP16", MEPCORE1_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sbcpa, "SBCPA", MEPCORE1_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbcpa, "LBCPA", MEPCORE1_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_shcpa, "SHCPA", MEPCORE1_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhcpa, "LHCPA", MEPCORE1_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_swcpa, "SWCPA", MEPCORE1_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lwcpa, "LWCPA", MEPCORE1_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_smcpa, "SMCPA", MEPCORE1_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lmcpa, "LMCPA", MEPCORE1_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sbcpm0, "SBCPM0", MEPCORE1_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbcpm0, "LBCPM0", MEPCORE1_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_shcpm0, "SHCPM0", MEPCORE1_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhcpm0, "LHCPM0", MEPCORE1_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_swcpm0, "SWCPM0", MEPCORE1_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lwcpm0, "LWCPM0", MEPCORE1_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_smcpm0, "SMCPM0", MEPCORE1_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lmcpm0, "LMCPM0", MEPCORE1_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sbcpm1, "SBCPM1", MEPCORE1_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lbcpm1, "LBCPM1", MEPCORE1_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_shcpm1, "SHCPM1", MEPCORE1_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lhcpm1, "LHCPM1", MEPCORE1_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_swcpm1, "SWCPM1", MEPCORE1_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lwcpm1, "LWCPM1", MEPCORE1_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_smcpm1, "SMCPM1", MEPCORE1_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_lmcpm1, "LMCPM1", MEPCORE1_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bcpeq, "BCPEQ", MEPCORE1_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bcpne, "BCPNE", MEPCORE1_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bcpat, "BCPAT", MEPCORE1_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bcpaf, "BCPAF", MEPCORE1_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_synccp, "SYNCCP", MEPCORE1_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_jsrv, "JSRV", MEPCORE1_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_bsrv, "BSRV", MEPCORE1_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_sim_syscall, "SIM_SYSCALL", MEPCORE1_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_0, "RI_0", MEPCORE1_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_1, "RI_1", MEPCORE1_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_2, "RI_2", MEPCORE1_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_3, "RI_3", MEPCORE1_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_4, "RI_4", MEPCORE1_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_5, "RI_5", MEPCORE1_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_6, "RI_6", MEPCORE1_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_7, "RI_7", MEPCORE1_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_8, "RI_8", MEPCORE1_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_9, "RI_9", MEPCORE1_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_10, "RI_10", MEPCORE1_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_11, "RI_11", MEPCORE1_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_12, "RI_12", MEPCORE1_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_13, "RI_13", MEPCORE1_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_14, "RI_14", MEPCORE1_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_15, "RI_15", MEPCORE1_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_17, "RI_17", MEPCORE1_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_20, "RI_20", MEPCORE1_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_21, "RI_21", MEPCORE1_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_22, "RI_22", MEPCORE1_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_23, "RI_23", MEPCORE1_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mepcore1_sem_ri_26, "RI_26", MEPCORE1_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_x_invalid, "X_INVALID", MEPCORE1_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x40" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_stcb_r, "STCB_R", MEPCORE1_INSN_STCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ldcb_r, "LDCB_R", MEPCORE1_INSN_LDCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_pref, "PREF", MEPCORE1_INSN_PREF, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_prefd, "PREFD", MEPCORE1_INSN_PREFD, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_casb3, "CASB3", MEPCORE1_INSN_CASB3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_cash3, "CASH3", MEPCORE1_INSN_CASH3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_casw3, "CASW3", MEPCORE1_INSN_CASW3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sbcp, "SBCP", MEPCORE1_INSN_SBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbcp, "LBCP", MEPCORE1_INSN_LBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbucp, "LBUCP", MEPCORE1_INSN_LBUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_shcp, "SHCP", MEPCORE1_INSN_SHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhcp, "LHCP", MEPCORE1_INSN_LHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhucp, "LHUCP", MEPCORE1_INSN_LHUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbucpa, "LBUCPA", MEPCORE1_INSN_LBUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhucpa, "LHUCPA", MEPCORE1_INSN_LHUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbucpm0, "LBUCPM0", MEPCORE1_INSN_LBUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhucpm0, "LHUCPM0", MEPCORE1_INSN_LHUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbucpm1, "LBUCPM1", MEPCORE1_INSN_LBUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhucpm1, "LHUCPM1", MEPCORE1_INSN_LHUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_uci, "UCI", MEPCORE1_INSN_UCI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_dsp, "DSP", MEPCORE1_INSN_DSP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sb, "SB", MEPCORE1_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sh, "SH", MEPCORE1_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sw, "SW", MEPCORE1_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lb, "LB", MEPCORE1_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lh, "LH", MEPCORE1_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lw, "LW", MEPCORE1_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbu, "LBU", MEPCORE1_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhu, "LHU", MEPCORE1_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sw_sp, "SW_SP", MEPCORE1_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lw_sp, "LW_SP", MEPCORE1_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sb_tp, "SB_TP", MEPCORE1_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sh_tp, "SH_TP", MEPCORE1_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sw_tp, "SW_TP", MEPCORE1_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lb_tp, "LB_TP", MEPCORE1_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lh_tp, "LH_TP", MEPCORE1_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lw_tp, "LW_TP", MEPCORE1_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbu_tp, "LBU_TP", MEPCORE1_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhu_tp, "LHU_TP", MEPCORE1_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sb16, "SB16", MEPCORE1_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sh16, "SH16", MEPCORE1_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sw16, "SW16", MEPCORE1_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lb16, "LB16", MEPCORE1_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lh16, "LH16", MEPCORE1_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lw16, "LW16", MEPCORE1_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbu16, "LBU16", MEPCORE1_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhu16, "LHU16", MEPCORE1_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sw24, "SW24", MEPCORE1_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lw24, "LW24", MEPCORE1_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_extb, "EXTB", MEPCORE1_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_exth, "EXTH", MEPCORE1_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_extub, "EXTUB", MEPCORE1_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_extuh, "EXTUH", MEPCORE1_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ssarb, "SSARB", MEPCORE1_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_mov, "MOV", MEPCORE1_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_movi8, "MOVI8", MEPCORE1_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_movi16, "MOVI16", MEPCORE1_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_movu24, "MOVU24", MEPCORE1_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_movu16, "MOVU16", MEPCORE1_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_movh, "MOVH", MEPCORE1_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_add3, "ADD3", MEPCORE1_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_add, "ADD", MEPCORE1_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_add3i, "ADD3I", MEPCORE1_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_advck3, "ADVCK3", MEPCORE1_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sub, "SUB", MEPCORE1_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sbvck3, "SBVCK3", MEPCORE1_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_neg, "NEG", MEPCORE1_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_slt3, "SLT3", MEPCORE1_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sltu3, "SLTU3", MEPCORE1_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_slt3i, "SLT3I", MEPCORE1_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sltu3i, "SLTU3I", MEPCORE1_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sl1ad3, "SL1AD3", MEPCORE1_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sl2ad3, "SL2AD3", MEPCORE1_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_add3x, "ADD3X", MEPCORE1_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_slt3x, "SLT3X", MEPCORE1_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sltu3x, "SLTU3X", MEPCORE1_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_or, "OR", MEPCORE1_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_and, "AND", MEPCORE1_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_xor, "XOR", MEPCORE1_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_nor, "NOR", MEPCORE1_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_or3, "OR3", MEPCORE1_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_and3, "AND3", MEPCORE1_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_xor3, "XOR3", MEPCORE1_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sra, "SRA", MEPCORE1_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_srl, "SRL", MEPCORE1_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sll, "SLL", MEPCORE1_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_srai, "SRAI", MEPCORE1_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_srli, "SRLI", MEPCORE1_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_slli, "SLLI", MEPCORE1_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sll3, "SLL3", MEPCORE1_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_fsft, "FSFT", MEPCORE1_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bra, "BRA", MEPCORE1_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_beqz, "BEQZ", MEPCORE1_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bnez, "BNEZ", MEPCORE1_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_beqi, "BEQI", MEPCORE1_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bnei, "BNEI", MEPCORE1_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_blti, "BLTI", MEPCORE1_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bgei, "BGEI", MEPCORE1_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_beq, "BEQ", MEPCORE1_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bne, "BNE", MEPCORE1_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bsr12, "BSR12", MEPCORE1_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bsr24, "BSR24", MEPCORE1_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_jmp, "JMP", MEPCORE1_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_jmp24, "JMP24", MEPCORE1_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_jsr, "JSR", MEPCORE1_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ret, "RET", MEPCORE1_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_repeat, "REPEAT", MEPCORE1_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_erepeat, "EREPEAT", MEPCORE1_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_stc_lp, "STC_LP", MEPCORE1_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_stc_hi, "STC_HI", MEPCORE1_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_stc_lo, "STC_LO", MEPCORE1_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_stc, "STC", MEPCORE1_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ldc_lp, "LDC_LP", MEPCORE1_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ldc_hi, "LDC_HI", MEPCORE1_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ldc_lo, "LDC_LO", MEPCORE1_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ldc, "LDC", MEPCORE1_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_di, "DI", MEPCORE1_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ei, "EI", MEPCORE1_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_reti, "RETI", MEPCORE1_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_halt, "HALT", MEPCORE1_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sleep, "SLEEP", MEPCORE1_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_swi, "SWI", MEPCORE1_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_break, "BREAK", MEPCORE1_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_syncm, "SYNCM", MEPCORE1_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_stcb, "STCB", MEPCORE1_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ldcb, "LDCB", MEPCORE1_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bsetm, "BSETM", MEPCORE1_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bclrm, "BCLRM", MEPCORE1_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bnotm, "BNOTM", MEPCORE1_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_btstm, "BTSTM", MEPCORE1_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_tas, "TAS", MEPCORE1_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_cache, "CACHE", MEPCORE1_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_mul, "MUL", MEPCORE1_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_mulu, "MULU", MEPCORE1_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_mulr, "MULR", MEPCORE1_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_mulru, "MULRU", MEPCORE1_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_madd, "MADD", MEPCORE1_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_maddu, "MADDU", MEPCORE1_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_maddr, "MADDR", MEPCORE1_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_maddru, "MADDRU", MEPCORE1_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_div, "DIV", MEPCORE1_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_divu, "DIVU", MEPCORE1_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_dret, "DRET", MEPCORE1_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_dbreak, "DBREAK", MEPCORE1_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ldz, "LDZ", MEPCORE1_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_abs, "ABS", MEPCORE1_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ave, "AVE", MEPCORE1_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_min, "MIN", MEPCORE1_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_max, "MAX", MEPCORE1_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_minu, "MINU", MEPCORE1_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_maxu, "MAXU", MEPCORE1_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_clip, "CLIP", MEPCORE1_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_clipu, "CLIPU", MEPCORE1_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sadd, "SADD", MEPCORE1_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ssub, "SSUB", MEPCORE1_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_saddu, "SADDU", MEPCORE1_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ssubu, "SSUBU", MEPCORE1_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_swcp, "SWCP", MEPCORE1_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lwcp, "LWCP", MEPCORE1_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_smcp, "SMCP", MEPCORE1_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lmcp, "LMCP", MEPCORE1_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_swcpi, "SWCPI", MEPCORE1_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lwcpi, "LWCPI", MEPCORE1_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_smcpi, "SMCPI", MEPCORE1_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lmcpi, "LMCPI", MEPCORE1_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_swcp16, "SWCP16", MEPCORE1_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lwcp16, "LWCP16", MEPCORE1_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_smcp16, "SMCP16", MEPCORE1_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lmcp16, "LMCP16", MEPCORE1_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sbcpa, "SBCPA", MEPCORE1_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbcpa, "LBCPA", MEPCORE1_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_shcpa, "SHCPA", MEPCORE1_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhcpa, "LHCPA", MEPCORE1_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_swcpa, "SWCPA", MEPCORE1_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lwcpa, "LWCPA", MEPCORE1_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_smcpa, "SMCPA", MEPCORE1_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lmcpa, "LMCPA", MEPCORE1_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sbcpm0, "SBCPM0", MEPCORE1_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbcpm0, "LBCPM0", MEPCORE1_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_shcpm0, "SHCPM0", MEPCORE1_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhcpm0, "LHCPM0", MEPCORE1_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_swcpm0, "SWCPM0", MEPCORE1_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lwcpm0, "LWCPM0", MEPCORE1_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_smcpm0, "SMCPM0", MEPCORE1_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lmcpm0, "LMCPM0", MEPCORE1_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sbcpm1, "SBCPM1", MEPCORE1_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lbcpm1, "LBCPM1", MEPCORE1_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_shcpm1, "SHCPM1", MEPCORE1_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lhcpm1, "LHCPM1", MEPCORE1_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_swcpm1, "SWCPM1", MEPCORE1_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lwcpm1, "LWCPM1", MEPCORE1_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_smcpm1, "SMCPM1", MEPCORE1_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_lmcpm1, "LMCPM1", MEPCORE1_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bcpeq, "BCPEQ", MEPCORE1_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bcpne, "BCPNE", MEPCORE1_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bcpat, "BCPAT", MEPCORE1_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bcpaf, "BCPAF", MEPCORE1_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_synccp, "SYNCCP", MEPCORE1_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_jsrv, "JSRV", MEPCORE1_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_bsrv, "BSRV", MEPCORE1_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_sim_syscall, "SIM_SYSCALL", MEPCORE1_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_0, "RI_0", MEPCORE1_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_1, "RI_1", MEPCORE1_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_2, "RI_2", MEPCORE1_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_3, "RI_3", MEPCORE1_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_4, "RI_4", MEPCORE1_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_5, "RI_5", MEPCORE1_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_6, "RI_6", MEPCORE1_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_7, "RI_7", MEPCORE1_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_8, "RI_8", MEPCORE1_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_9, "RI_9", MEPCORE1_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_10, "RI_10", MEPCORE1_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_11, "RI_11", MEPCORE1_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_12, "RI_12", MEPCORE1_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_13, "RI_13", MEPCORE1_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_14, "RI_14", MEPCORE1_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_15, "RI_15", MEPCORE1_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_17, "RI_17", MEPCORE1_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_20, "RI_20", MEPCORE1_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_21, "RI_21", MEPCORE1_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_22, "RI_22", MEPCORE1_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_23, "RI_23", MEPCORE1_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mepcore1_sem_ri_26, "RI_26", MEPCORE1_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
};
Index: sid/component/cgen-cpu/mep/mep-cpu.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-cpu.h,v
retrieving revision 1.3
diff -p -U3 -r1.3 mep-cpu.h
--- sid/component/cgen-cpu/mep/mep-cpu.h 30 Apr 2009 21:18:37 -0000 1.3
+++ sid/component/cgen-cpu/mep/mep-cpu.h 24 Jun 2009 02:59:30 -0000
@@ -100,8 +100,8 @@ public:
inline void h_cr_ivc2_set (UINT regno, DI newval) { current_cpu->h_cr64_set (regno, newval);
}
- inline DI h_ccr_ivc2_get (UINT regno) const { return current_cpu->h_ccr_get (regno); }
- inline void h_ccr_ivc2_set (UINT regno, DI newval) { current_cpu->h_ccr_set (regno, newval);
+ inline SI h_ccr_ivc2_get (UINT regno) const { return current_cpu->h_ccr_get (regno); }
+ inline void h_ccr_ivc2_set (UINT regno, SI newval) { current_cpu->h_ccr_set (regno, newval);
}
#undef current_cpu
Index: sid/component/cgen-cpu/mep/mep-decode.cxx
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-decode.cxx,v
retrieving revision 1.5
diff -p -U3 -r1.5 mep-decode.cxx
--- sid/component/cgen-cpu/mep/mep-decode.cxx 30 Apr 2009 21:18:37 -0000 1.5
+++ sid/component/cgen-cpu/mep/mep-decode.cxx 24 Jun 2009 02:59:30 -0000
@@ -22,230 +22,230 @@ using namespace mep_basic; // FIXME: nam
mep_idesc mep_idesc::idesc_table[MEP_INSN_RI_26 + 1] =
{
- { mep_sem_x_invalid, "X_INVALID", MEP_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_stcb_r, "STCB_R", MEP_INSN_STCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ldcb_r, "LDCB_R", MEP_INSN_LDCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_pref, "PREF", MEP_INSN_PREF, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_prefd, "PREFD", MEP_INSN_PREFD, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_casb3, "CASB3", MEP_INSN_CASB3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_cash3, "CASH3", MEP_INSN_CASH3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_casw3, "CASW3", MEP_INSN_CASW3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sbcp, "SBCP", MEP_INSN_SBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbcp, "LBCP", MEP_INSN_LBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbucp, "LBUCP", MEP_INSN_LBUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_shcp, "SHCP", MEP_INSN_SHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhcp, "LHCP", MEP_INSN_LHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhucp, "LHUCP", MEP_INSN_LHUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbucpa, "LBUCPA", MEP_INSN_LBUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhucpa, "LHUCPA", MEP_INSN_LHUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbucpm0, "LBUCPM0", MEP_INSN_LBUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhucpm0, "LHUCPM0", MEP_INSN_LHUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbucpm1, "LBUCPM1", MEP_INSN_LBUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhucpm1, "LHUCPM1", MEP_INSN_LHUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_uci, "UCI", MEP_INSN_UCI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_dsp, "DSP", MEP_INSN_DSP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sb, "SB", MEP_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sh, "SH", MEP_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sw, "SW", MEP_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lb, "LB", MEP_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lh, "LH", MEP_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lw, "LW", MEP_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbu, "LBU", MEP_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhu, "LHU", MEP_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sw_sp, "SW_SP", MEP_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lw_sp, "LW_SP", MEP_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sb_tp, "SB_TP", MEP_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sh_tp, "SH_TP", MEP_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sw_tp, "SW_TP", MEP_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lb_tp, "LB_TP", MEP_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lh_tp, "LH_TP", MEP_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lw_tp, "LW_TP", MEP_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbu_tp, "LBU_TP", MEP_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhu_tp, "LHU_TP", MEP_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sb16, "SB16", MEP_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sh16, "SH16", MEP_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sw16, "SW16", MEP_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lb16, "LB16", MEP_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lh16, "LH16", MEP_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lw16, "LW16", MEP_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbu16, "LBU16", MEP_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhu16, "LHU16", MEP_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sw24, "SW24", MEP_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lw24, "LW24", MEP_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_extb, "EXTB", MEP_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_exth, "EXTH", MEP_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_extub, "EXTUB", MEP_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_extuh, "EXTUH", MEP_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ssarb, "SSARB", MEP_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_mov, "MOV", MEP_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_movi8, "MOVI8", MEP_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_movi16, "MOVI16", MEP_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_movu24, "MOVU24", MEP_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_movu16, "MOVU16", MEP_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_movh, "MOVH", MEP_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_add3, "ADD3", MEP_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_add, "ADD", MEP_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_add3i, "ADD3I", MEP_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_advck3, "ADVCK3", MEP_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sub, "SUB", MEP_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sbvck3, "SBVCK3", MEP_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_neg, "NEG", MEP_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_slt3, "SLT3", MEP_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sltu3, "SLTU3", MEP_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_slt3i, "SLT3I", MEP_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sltu3i, "SLTU3I", MEP_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sl1ad3, "SL1AD3", MEP_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sl2ad3, "SL2AD3", MEP_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_add3x, "ADD3X", MEP_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_slt3x, "SLT3X", MEP_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sltu3x, "SLTU3X", MEP_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_or, "OR", MEP_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_and, "AND", MEP_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_xor, "XOR", MEP_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_nor, "NOR", MEP_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_or3, "OR3", MEP_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_and3, "AND3", MEP_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_xor3, "XOR3", MEP_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sra, "SRA", MEP_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_srl, "SRL", MEP_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sll, "SLL", MEP_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_srai, "SRAI", MEP_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_srli, "SRLI", MEP_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_slli, "SLLI", MEP_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sll3, "SLL3", MEP_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_fsft, "FSFT", MEP_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bra, "BRA", MEP_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_beqz, "BEQZ", MEP_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bnez, "BNEZ", MEP_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_beqi, "BEQI", MEP_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bnei, "BNEI", MEP_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_blti, "BLTI", MEP_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bgei, "BGEI", MEP_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_beq, "BEQ", MEP_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bne, "BNE", MEP_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bsr12, "BSR12", MEP_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bsr24, "BSR24", MEP_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_jmp, "JMP", MEP_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_jmp24, "JMP24", MEP_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_jsr, "JSR", MEP_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ret, "RET", MEP_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_repeat, "REPEAT", MEP_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_erepeat, "EREPEAT", MEP_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_stc_lp, "STC_LP", MEP_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_stc_hi, "STC_HI", MEP_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_stc_lo, "STC_LO", MEP_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_stc, "STC", MEP_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ldc_lp, "LDC_LP", MEP_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ldc_hi, "LDC_HI", MEP_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ldc_lo, "LDC_LO", MEP_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ldc, "LDC", MEP_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_di, "DI", MEP_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ei, "EI", MEP_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_reti, "RETI", MEP_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_halt, "HALT", MEP_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sleep, "SLEEP", MEP_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_swi, "SWI", MEP_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_break, "BREAK", MEP_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_syncm, "SYNCM", MEP_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_stcb, "STCB", MEP_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ldcb, "LDCB", MEP_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bsetm, "BSETM", MEP_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bclrm, "BCLRM", MEP_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bnotm, "BNOTM", MEP_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_btstm, "BTSTM", MEP_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_tas, "TAS", MEP_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_cache, "CACHE", MEP_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_mul, "MUL", MEP_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_mulu, "MULU", MEP_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_mulr, "MULR", MEP_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_mulru, "MULRU", MEP_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_madd, "MADD", MEP_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_maddu, "MADDU", MEP_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_maddr, "MADDR", MEP_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_maddru, "MADDRU", MEP_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_div, "DIV", MEP_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_divu, "DIVU", MEP_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_dret, "DRET", MEP_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_dbreak, "DBREAK", MEP_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ldz, "LDZ", MEP_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_abs, "ABS", MEP_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ave, "AVE", MEP_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_min, "MIN", MEP_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_max, "MAX", MEP_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_minu, "MINU", MEP_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_maxu, "MAXU", MEP_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_clip, "CLIP", MEP_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_clipu, "CLIPU", MEP_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sadd, "SADD", MEP_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ssub, "SSUB", MEP_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_saddu, "SADDU", MEP_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ssubu, "SSUBU", MEP_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_swcp, "SWCP", MEP_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lwcp, "LWCP", MEP_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_smcp, "SMCP", MEP_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lmcp, "LMCP", MEP_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_swcpi, "SWCPI", MEP_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lwcpi, "LWCPI", MEP_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_smcpi, "SMCPI", MEP_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lmcpi, "LMCPI", MEP_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_swcp16, "SWCP16", MEP_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lwcp16, "LWCP16", MEP_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_smcp16, "SMCP16", MEP_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lmcp16, "LMCP16", MEP_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sbcpa, "SBCPA", MEP_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbcpa, "LBCPA", MEP_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_shcpa, "SHCPA", MEP_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhcpa, "LHCPA", MEP_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_swcpa, "SWCPA", MEP_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lwcpa, "LWCPA", MEP_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_smcpa, "SMCPA", MEP_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lmcpa, "LMCPA", MEP_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sbcpm0, "SBCPM0", MEP_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbcpm0, "LBCPM0", MEP_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_shcpm0, "SHCPM0", MEP_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhcpm0, "LHCPM0", MEP_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_swcpm0, "SWCPM0", MEP_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lwcpm0, "LWCPM0", MEP_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_smcpm0, "SMCPM0", MEP_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lmcpm0, "LMCPM0", MEP_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sbcpm1, "SBCPM1", MEP_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lbcpm1, "LBCPM1", MEP_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_shcpm1, "SHCPM1", MEP_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lhcpm1, "LHCPM1", MEP_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_swcpm1, "SWCPM1", MEP_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lwcpm1, "LWCPM1", MEP_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_smcpm1, "SMCPM1", MEP_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_lmcpm1, "LMCPM1", MEP_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bcpeq, "BCPEQ", MEP_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bcpne, "BCPNE", MEP_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bcpat, "BCPAT", MEP_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bcpaf, "BCPAF", MEP_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_synccp, "SYNCCP", MEP_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_jsrv, "JSRV", MEP_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_bsrv, "BSRV", MEP_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_sim_syscall, "SIM_SYSCALL", MEP_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_0, "RI_0", MEP_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_1, "RI_1", MEP_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_2, "RI_2", MEP_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_3, "RI_3", MEP_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_4, "RI_4", MEP_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_5, "RI_5", MEP_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_6, "RI_6", MEP_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_7, "RI_7", MEP_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_8, "RI_8", MEP_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_9, "RI_9", MEP_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_10, "RI_10", MEP_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_11, "RI_11", MEP_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_12, "RI_12", MEP_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_13, "RI_13", MEP_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_14, "RI_14", MEP_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_15, "RI_15", MEP_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_17, "RI_17", MEP_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_20, "RI_20", MEP_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_21, "RI_21", MEP_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_22, "RI_22", MEP_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_23, "RI_23", MEP_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
- { mep_sem_ri_26, "RI_26", MEP_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_x_invalid, "X_INVALID", MEP_INSN_X_INVALID, { 0|(1<<CGEN_INSN_VIRTUAL), (1<<MACH_BASE), { 1, "\x80" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_stcb_r, "STCB_R", MEP_INSN_STCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ldcb_r, "LDCB_R", MEP_INSN_LDCB_R, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_pref, "PREF", MEP_INSN_PREF, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_prefd, "PREFD", MEP_INSN_PREFD, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_casb3, "CASB3", MEP_INSN_CASB3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_cash3, "CASH3", MEP_INSN_CASH3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_casw3, "CASW3", MEP_INSN_CASW3, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN)|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sbcp, "SBCP", MEP_INSN_SBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbcp, "LBCP", MEP_INSN_LBCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbucp, "LBUCP", MEP_INSN_LBUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_shcp, "SHCP", MEP_INSN_SHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhcp, "LHCP", MEP_INSN_LHCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhucp, "LHUCP", MEP_INSN_LHUCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbucpa, "LBUCPA", MEP_INSN_LBUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhucpa, "LHUCPA", MEP_INSN_LHUCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbucpm0, "LBUCPM0", MEP_INSN_LBUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhucpm0, "LHUCPM0", MEP_INSN_LHUCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbucpm1, "LBUCPM1", MEP_INSN_LBUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhucpm1, "LHUCPM1", MEP_INSN_LHUCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_uci, "UCI", MEP_INSN_UCI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_dsp, "DSP", MEP_INSN_DSP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_C5), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sb, "SB", MEP_INSN_SB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sh, "SH", MEP_INSN_SH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sw, "SW", MEP_INSN_SW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lb, "LB", MEP_INSN_LB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lh, "LH", MEP_INSN_LH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lw, "LW", MEP_INSN_LW, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbu, "LBU", MEP_INSN_LBU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhu, "LHU", MEP_INSN_LHU, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sw_sp, "SW_SP", MEP_INSN_SW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lw_sp, "LW_SP", MEP_INSN_LW_SP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sb_tp, "SB_TP", MEP_INSN_SB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sh_tp, "SH_TP", MEP_INSN_SH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sw_tp, "SW_TP", MEP_INSN_SW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lb_tp, "LB_TP", MEP_INSN_LB_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lh_tp, "LH_TP", MEP_INSN_LH_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lw_tp, "LW_TP", MEP_INSN_LW_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbu_tp, "LBU_TP", MEP_INSN_LBU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhu_tp, "LHU_TP", MEP_INSN_LHU_TP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sb16, "SB16", MEP_INSN_SB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sh16, "SH16", MEP_INSN_SH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sw16, "SW16", MEP_INSN_SW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lb16, "LB16", MEP_INSN_LB16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lh16, "LH16", MEP_INSN_LH16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lw16, "LW16", MEP_INSN_LW16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbu16, "LBU16", MEP_INSN_LBU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhu16, "LHU16", MEP_INSN_LHU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sw24, "SW24", MEP_INSN_SW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lw24, "LW24", MEP_INSN_LW24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_extb, "EXTB", MEP_INSN_EXTB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_exth, "EXTH", MEP_INSN_EXTH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_extub, "EXTUB", MEP_INSN_EXTUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_extuh, "EXTUH", MEP_INSN_EXTUH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ssarb, "SSARB", MEP_INSN_SSARB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_mov, "MOV", MEP_INSN_MOV, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_movi8, "MOVI8", MEP_INSN_MOVI8, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_movi16, "MOVI16", MEP_INSN_MOVI16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_movu24, "MOVU24", MEP_INSN_MOVU24, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_movu16, "MOVU16", MEP_INSN_MOVU16, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_movh, "MOVH", MEP_INSN_MOVH, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_add3, "ADD3", MEP_INSN_ADD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_add, "ADD", MEP_INSN_ADD, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_add3i, "ADD3I", MEP_INSN_ADD3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_advck3, "ADVCK3", MEP_INSN_ADVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sub, "SUB", MEP_INSN_SUB, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sbvck3, "SBVCK3", MEP_INSN_SBVCK3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_neg, "NEG", MEP_INSN_NEG, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_slt3, "SLT3", MEP_INSN_SLT3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sltu3, "SLTU3", MEP_INSN_SLTU3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_slt3i, "SLT3I", MEP_INSN_SLT3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sltu3i, "SLTU3I", MEP_INSN_SLTU3I, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sl1ad3, "SL1AD3", MEP_INSN_SL1AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sl2ad3, "SL2AD3", MEP_INSN_SL2AD3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_add3x, "ADD3X", MEP_INSN_ADD3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_slt3x, "SLT3X", MEP_INSN_SLT3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sltu3x, "SLTU3X", MEP_INSN_SLTU3X, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_or, "OR", MEP_INSN_OR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_and, "AND", MEP_INSN_AND, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_xor, "XOR", MEP_INSN_XOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_nor, "NOR", MEP_INSN_NOR, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_or3, "OR3", MEP_INSN_OR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_and3, "AND3", MEP_INSN_AND3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_xor3, "XOR3", MEP_INSN_XOR3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sra, "SRA", MEP_INSN_SRA, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_srl, "SRL", MEP_INSN_SRL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sll, "SLL", MEP_INSN_SLL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_srai, "SRAI", MEP_INSN_SRAI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_srli, "SRLI", MEP_INSN_SRLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_slli, "SLLI", MEP_INSN_SLLI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sll3, "SLL3", MEP_INSN_SLL3, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_fsft, "FSFT", MEP_INSN_FSFT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bra, "BRA", MEP_INSN_BRA, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_beqz, "BEQZ", MEP_INSN_BEQZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bnez, "BNEZ", MEP_INSN_BNEZ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_beqi, "BEQI", MEP_INSN_BEQI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bnei, "BNEI", MEP_INSN_BNEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_blti, "BLTI", MEP_INSN_BLTI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bgei, "BGEI", MEP_INSN_BGEI, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_beq, "BEQ", MEP_INSN_BEQ, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bne, "BNE", MEP_INSN_BNE, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bsr12, "BSR12", MEP_INSN_BSR12, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bsr24, "BSR24", MEP_INSN_BSR24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_jmp, "JMP", MEP_INSN_JMP, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_jmp24, "JMP24", MEP_INSN_JMP24, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_jsr, "JSR", MEP_INSN_JSR, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ret, "RET", MEP_INSN_RET, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_repeat, "REPEAT", MEP_INSN_REPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_erepeat, "EREPEAT", MEP_INSN_EREPEAT, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_stc_lp, "STC_LP", MEP_INSN_STC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_stc_hi, "STC_HI", MEP_INSN_STC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_stc_lo, "STC_LO", MEP_INSN_STC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_stc, "STC", MEP_INSN_STC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ldc_lp, "LDC_LP", MEP_INSN_LDC_LP, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ldc_hi, "LDC_HI", MEP_INSN_LDC_HI, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ldc_lo, "LDC_LO", MEP_INSN_LDC_LO, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ldc, "LDC", MEP_INSN_LDC, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 2, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_di, "DI", MEP_INSN_DI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ei, "EI", MEP_INSN_EI, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_reti, "RETI", MEP_INSN_RETI, { 0|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_halt, "HALT", MEP_INSN_HALT, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sleep, "SLEEP", MEP_INSN_SLEEP, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_swi, "SWI", MEP_INSN_SWI, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_break, "BREAK", MEP_INSN_BREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_syncm, "SYNCM", MEP_INSN_SYNCM, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_stcb, "STCB", MEP_INSN_STCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ldcb, "LDCB", MEP_INSN_LDCB, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bsetm, "BSETM", MEP_INSN_BSETM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bclrm, "BCLRM", MEP_INSN_BCLRM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bnotm, "BNOTM", MEP_INSN_BNOTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_btstm, "BTSTM", MEP_INSN_BTSTM, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_tas, "TAS", MEP_INSN_TAS, { 0|(1<<CGEN_INSN_OPTIONAL_BIT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_cache, "CACHE", MEP_INSN_CACHE, { 0|(1<<CGEN_INSN_VOLATILE), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_mul, "MUL", MEP_INSN_MUL, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_mulu, "MULU", MEP_INSN_MULU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_mulr, "MULR", MEP_INSN_MULR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_mulru, "MULRU", MEP_INSN_MULRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_madd, "MADD", MEP_INSN_MADD, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_maddu, "MADDU", MEP_INSN_MADDU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_maddr, "MADDR", MEP_INSN_MADDR, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_maddru, "MADDRU", MEP_INSN_MADDRU, { 0|(1<<CGEN_INSN_OPTIONAL_MUL_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 3, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_div, "DIV", MEP_INSN_DIV, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_divu, "DIVU", MEP_INSN_DIVU, { 0|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DIV_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 34, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_dret, "DRET", MEP_INSN_DRET, { 0|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN)|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_dbreak, "DBREAK", MEP_INSN_DBREAK, { 0|(1<<CGEN_INSN_VOLATILE)|(1<<CGEN_INSN_MAY_TRAP)|(1<<CGEN_INSN_OPTIONAL_DEBUG_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ldz, "LDZ", MEP_INSN_LDZ, { 0|(1<<CGEN_INSN_OPTIONAL_LDZ_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_abs, "ABS", MEP_INSN_ABS, { 0|(1<<CGEN_INSN_OPTIONAL_ABS_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ave, "AVE", MEP_INSN_AVE, { 0|(1<<CGEN_INSN_OPTIONAL_AVE_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_min, "MIN", MEP_INSN_MIN, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_max, "MAX", MEP_INSN_MAX, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_minu, "MINU", MEP_INSN_MINU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_maxu, "MAXU", MEP_INSN_MAXU, { 0|(1<<CGEN_INSN_OPTIONAL_MINMAX_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_clip, "CLIP", MEP_INSN_CLIP, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_clipu, "CLIPU", MEP_INSN_CLIPU, { 0|(1<<CGEN_INSN_OPTIONAL_CLIP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sadd, "SADD", MEP_INSN_SADD, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ssub, "SSUB", MEP_INSN_SSUB, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_saddu, "SADDU", MEP_INSN_SADDU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ssubu, "SSUBU", MEP_INSN_SSUBU, { 0|(1<<CGEN_INSN_OPTIONAL_SAT_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_swcp, "SWCP", MEP_INSN_SWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lwcp, "LWCP", MEP_INSN_LWCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_smcp, "SMCP", MEP_INSN_SMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lmcp, "LMCP", MEP_INSN_LMCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_swcpi, "SWCPI", MEP_INSN_SWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lwcpi, "LWCPI", MEP_INSN_LWCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_smcpi, "SMCPI", MEP_INSN_SMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lmcpi, "LMCPI", MEP_INSN_LMCPI, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_swcp16, "SWCP16", MEP_INSN_SWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lwcp16, "LWCP16", MEP_INSN_LWCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_smcp16, "SMCP16", MEP_INSN_SMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lmcp16, "LMCP16", MEP_INSN_LMCP16, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sbcpa, "SBCPA", MEP_INSN_SBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbcpa, "LBCPA", MEP_INSN_LBCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_shcpa, "SHCPA", MEP_INSN_SHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhcpa, "LHCPA", MEP_INSN_LHCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_swcpa, "SWCPA", MEP_INSN_SWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lwcpa, "LWCPA", MEP_INSN_LWCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_smcpa, "SMCPA", MEP_INSN_SMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lmcpa, "LMCPA", MEP_INSN_LMCPA, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sbcpm0, "SBCPM0", MEP_INSN_SBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbcpm0, "LBCPM0", MEP_INSN_LBCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_shcpm0, "SHCPM0", MEP_INSN_SHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhcpm0, "LHCPM0", MEP_INSN_LHCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_swcpm0, "SWCPM0", MEP_INSN_SWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lwcpm0, "LWCPM0", MEP_INSN_LWCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_smcpm0, "SMCPM0", MEP_INSN_SMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lmcpm0, "LMCPM0", MEP_INSN_LMCPM0, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sbcpm1, "SBCPM1", MEP_INSN_SBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lbcpm1, "LBCPM1", MEP_INSN_LBCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_shcpm1, "SHCPM1", MEP_INSN_SHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lhcpm1, "LHCPM1", MEP_INSN_LHCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_swcpm1, "SWCPM1", MEP_INSN_SWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lwcpm1, "LWCPM1", MEP_INSN_LWCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_smcpm1, "SMCPM1", MEP_INSN_SMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_lmcpm1, "LMCPM1", MEP_INSN_LMCPM1, { 0|(1<<CGEN_INSN_OPTIONAL_CP64_INSN)|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bcpeq, "BCPEQ", MEP_INSN_BCPEQ, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bcpne, "BCPNE", MEP_INSN_BCPNE, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bcpat, "BCPAT", MEP_INSN_BCPAT, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bcpaf, "BCPAF", MEP_INSN_BCPAF, { 0|(1<<CGEN_INSN_RELAXABLE)|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_synccp, "SYNCCP", MEP_INSN_SYNCCP, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_jsrv, "JSRV", MEP_INSN_JSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_bsrv, "BSRV", MEP_INSN_BSRV, { 0|(1<<CGEN_INSN_OPTIONAL_CP_INSN)|(1<<CGEN_INSN_COND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_sim_syscall, "SIM_SYSCALL", MEP_INSN_SIM_SYSCALL, { 0, (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_0, "RI_0", MEP_INSN_RI_0, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_1, "RI_1", MEP_INSN_RI_1, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_2, "RI_2", MEP_INSN_RI_2, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_3, "RI_3", MEP_INSN_RI_3, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_4, "RI_4", MEP_INSN_RI_4, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_5, "RI_5", MEP_INSN_RI_5, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_6, "RI_6", MEP_INSN_RI_6, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_7, "RI_7", MEP_INSN_RI_7, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_8, "RI_8", MEP_INSN_RI_8, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_9, "RI_9", MEP_INSN_RI_9, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_10, "RI_10", MEP_INSN_RI_10, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_11, "RI_11", MEP_INSN_RI_11, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_12, "RI_12", MEP_INSN_RI_12, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_13, "RI_13", MEP_INSN_RI_13, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_14, "RI_14", MEP_INSN_RI_14, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_15, "RI_15", MEP_INSN_RI_15, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_17, "RI_17", MEP_INSN_RI_17, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_20, "RI_20", MEP_INSN_RI_20, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_21, "RI_21", MEP_INSN_RI_21, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_22, "RI_22", MEP_INSN_RI_22, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_23, "RI_23", MEP_INSN_RI_23, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
+ { mep_sem_ri_26, "RI_26", MEP_INSN_RI_26, { 0|(1<<CGEN_INSN_UNCOND_CTI), (1<<MACH_BASE), { 1, "\xc0" }, CPTYPE_CP_DATA_BUS_INT, CRET_VOID, 0, CONFIG_NONE, (1<<SLOTS_CORE) } },
};
Index: sid/component/cgen-cpu/mep/mep-desc.h
===================================================================
RCS file: /cvs/src/src/sid/component/cgen-cpu/mep/mep-desc.h,v
retrieving revision 1.4
diff -p -U3 -r1.4 mep-desc.h
--- sid/component/cgen-cpu/mep/mep-desc.h 30 Apr 2009 21:18:37 -0000 1.4
+++ sid/component/cgen-cpu/mep/mep-desc.h 24 Jun 2009 02:59:30 -0000
@@ -39,7 +39,8 @@ typedef enum cgen_insn_attr {
, CGEN_INSN_OPTIONAL_VLIW64, CGEN_INSN_MAY_TRAP, CGEN_INSN_VLIW_ALONE, CGEN_INSN_VLIW_NO_CORE_NOP
, CGEN_INSN_VLIW_NO_COP_NOP, CGEN_INSN_VLIW64_NO_MATCHING_NOP, CGEN_INSN_VLIW32_NO_MATCHING_NOP, CGEN_INSN_VOLATILE
, CGEN_INSN_END_BOOLS, CGEN_INSN_START_NBOOLS = 31, CGEN_INSN_MACH, CGEN_INSN_ISA
- , CGEN_INSN_LATENCY, CGEN_INSN_CONFIG, CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
+ , CGEN_INSN_CPTYPE, CGEN_INSN_CRET, CGEN_INSN_LATENCY, CGEN_INSN_CONFIG
+ , CGEN_INSN_SLOTS, CGEN_INSN_END_NBOOLS
} CGEN_INSN_ATTR;
/* Number of non-boolean elements in cgen_insn_attr. */
@@ -66,6 +67,17 @@ typedef enum cdata_attr {
, CDATA_USHORT, CDATA_CHAR, CDATA_UCHAR, CDATA_CP_DATA_BUS_INT
} CDATA_ATTR;
+/* Enum declaration for datatype to use for coprocessor values. */
+typedef enum cptype_attr {
+ CPTYPE_CP_DATA_BUS_INT, CPTYPE_VECT, CPTYPE_V2SI, CPTYPE_V4HI
+ , CPTYPE_V8QI, CPTYPE_V2USI, CPTYPE_V4UHI, CPTYPE_V8UQI
+} CPTYPE_ATTR;
+
+/* Enum declaration for Insn's intrinsic returns void, or the first argument rather than (or in addition to) passing it.. */
+typedef enum cret_attr {
+ CRET_VOID, CRET_FIRST, CRET_FIRSTCOPY
+} CRET_ATTR;
+
/* Enum declaration for . */
typedef enum config_attr {
CONFIG_NONE, CONFIG_DEFAULT
@@ -83,11 +95,15 @@ struct mep_insn_attr {
unsigned int bools;
unsigned int mach;
CGEN_BITSET isa;
+ enum cptype_attr cptype;
+ enum cret_attr cret;
int latency;
enum config_attr config;
unsigned int slots;
inline unsigned int get_mach_attr () { return mach; }
inline CGEN_BITSET get_isa_attr () { return isa; }
+ inline enum cptype_attr get_cptype_attr () { return cptype; }
+ inline enum cret_attr get_cret_attr () { return cret; }
inline int get_latency_attr () { return latency; }
inline enum config_attr get_config_attr () { return config; }
inline unsigned int get_slots_attr () { return slots; }
^ permalink raw reply [flat|nested] 2+ messages in thread
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2009-06-24 3:27 [patch] mep: ivc2 support DJ Delorie
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2009-06-24 3:14 DJ Delorie
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