From: Doug Evans <dje@sebabeach.org>
To: Dave Korn <dave.korn.cygwin@googlemail.com>
Cc: cgen@sources.redhat.com
Subject: Re: unable to find precise mode to match cpu word-bitsize 24
Date: Sun, 21 Jun 2009 23:07:00 -0000 [thread overview]
Message-ID: <4A3EBD0E.5080109@sebabeach.org> (raw)
In-Reply-To: <4A3E86AA.2080002@gmail.com>
Dave Korn wrote:
> Hello CGEN list,
>
> I'm attempting to develop a model of a CPU that has a natural 24-bit
> wordsize: 24-bit registers, 24-bit ALU, 24-bit data bus... 24-bit everything,
> and no subword or unaligned accesses - in fact, you could really call them
> 24-bit bytes, as it's the minimum addressable unit.
>
> A naive attempt to just write
>
> (define-cpu
> [ . . . ]
> (word-bitsize 24)
> [ . . . ]
> )
>
> fails with the error message from the title of this post. I've crudely hacked
> in a couple of three-quarter int modes like this:
>
> Index: mode.scm
> ===================================================================
> RCS file: /cvs/src/src/cgen/mode.scm,v
> retrieving revision 1.4
> diff -p -u -r1.4 mode.scm
> --- mode.scm 16 Jul 2003 05:35:47 -0000 1.4
> +++ mode.scm 21 Jun 2009 18:45:00 -0000
> @@ -499,6 +499,7 @@ Define a mode, all arguments specified.
>
> (dfm 'QI "8 bit byte" '() 'INT 8 1 "int" "'x'" #f #f #f)
> (dfm 'HI "16 bit int" '() 'INT 16 2 "int" "'x'" #f #f #f)
> + (dfm 'TQI "24 bit int" '() 'INT 24 3 "int" "'x'" #f #f #f)
> (dfm 'SI "32 bit int" '() 'INT 32 4 "int" "'x'" #f #f #f)
> (dfm 'DI "64 bit int" '(FN-SUPPORT) 'INT 64 8 "" "'D'" #f #f #f)
>
> @@ -506,6 +507,8 @@ Define a mode, all arguments specified.
> 8 1 "unsigned int" "'x'" (mode:lookup 'QI) #f #f)
> (dfm 'UHI "16 bit unsigned int" '() 'UINT
> 16 2 "unsigned int" "'x'" (mode:lookup 'HI) #f #f)
> + (dfm 'UTQI "24 bit unsigned int" '() 'UINT
> + 24 3 "unsigned int" "'x'" (mode:lookup 'TQI) #f #f)
> (dfm 'USI "32 bit unsigned int" '() 'UINT
> 32 4 "unsigned int" "'x'" (mode:lookup 'SI) #f #f)
> (dfm 'UDI "64 bit unsigned int" '(FN-SUPPORT) 'UINT
>
>
> just so that I can get on with writing my i-fields, but will it work? If I
> want my (simulated) pc to increment in steps of 1, not 3, should I define the
> number of bytes to 1 instead of 3? Or would I be best off redefining QI mode
> altogether? Sorry if this is a n00b question, but a bit of googling and
> grepping didn't show up anyone trying this before.
>
>
This is new ground so we can decide how we want things to look, and then
make it work.
I think(!) that we don't want to redefine QI.
For clarity's sake, the T in TQI is for "Three", right? [3 * 8 = 24]
I've been thinking that while QI,HI,SI,DI are clear, any other similarly
named modes might become problematic over time.
An alternative is I24 of course, but if one goes that route one needs to
resolve what to do about QI,etc.
[They *could* become aliases of I8, etc. and perhaps eventually be
removed entirely, at least from the application independent core.
Anything related to gcc may certainly want to use them.] This route has
the benefit of solving this problem for future weird architectures.
[And just because we add I24 doesn't mean we'd have to immediately add
all the others, e.g. I23, etc.]
Also, since it's related, I've been thinking of removing UQI, UHI, etc.
They were a useful internal implementation detail at one point, but I
think they've become more of a problem than a help.
[But we needn't block this discussion on what happens with that.]
I'd be curious to hear what others think.
next prev parent reply other threads:[~2009-06-21 23:07 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-06-21 19:02 Dave Korn
2009-06-21 23:07 ` Doug Evans [this message]
2009-06-22 0:05 ` Dave Korn
2009-06-22 17:05 ` Doug Evans
2009-07-04 23:35 ` Dave Korn
2009-07-14 5:59 ` Doug Evans
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