From: Doug Evans <dje@sebabeach.org>
To: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Cc: Dave Korn <dave.korn.cygwin@googlemail.com>,
cgen <cgen@sources.redhat.com>
Subject: Re: cgen->sim question
Date: Wed, 28 Oct 2009 16:40:00 -0000 [thread overview]
Message-ID: <4AE873E8.6030909@sebabeach.org> (raw)
In-Reply-To: <bc64b4640910261312m5a0203au30a3807dd02fe6e6@mail.gmail.com>
Dmitry Eremin-Solenikov wrote:
> Hello,
>
> On Mon, Oct 26, 2009 at 7:12 PM, Doug Evans <dje@sebabeach.org> wrote:
>
>> Dave Korn wrote:
>>
>>> Dmitry Eremin-Solenikov wrote:
>>>
>>>
>>>> Hello,
>>>>
>>>> I have a question regarding generating sim code from cgen description.
>>>>
>>>> I have an instruction operand instantiated from field with type h-addr.
>>>> If in the semantics part of the instruction I try to access the operandr
>>>> as an address: '(mem QI ddaddr)', I get an error from cgen:
>>>>
>>>> simplify.inc:131:3: op:new-mode: invalid mode for operand `ddaddr': USI
>>>>
>>>> This is the definition of ddaddr:
>>>>
>>>> (dif f-dd-1 "1-byte direct address at 1 position" (ABS-ADDR) 8 8 0 8 UINT
>>>> #f #f)
>>>> (dno ddaddr "direct address" () h-addr f-dd-1)
>>>>
>
>
>> What does the instruction definition look like?
>>
>
> Please see the attachment. The stamp-cpu (cgen-cpu-decode) fails on
> this CPU file.
>
>
I checked in this patch.
2009-10-28 Doug Evans <dje@sebabeach.org>
* cos.scm (object-assign!): New function.
* mode.scm (/mode-set-word-params!): Call it.
next prev parent reply other threads:[~2009-10-28 16:40 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-10-26 10:45 Dmitry Eremin-Solenikov
2009-10-26 12:26 ` Dave Korn
2009-10-26 16:13 ` Doug Evans
2009-10-26 20:13 ` Dmitry Eremin-Solenikov
2009-10-27 7:39 ` Doug Evans
2009-10-28 16:40 ` Doug Evans [this message]
2009-10-30 21:59 ` Dmitry Eremin-Solenikov
2009-10-27 18:06 ` Dave Korn
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