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From: Peter.Targett@arccores.com
To: cgen@sources.redhat.com
Subject: Re: supporting mixed 16/32-bit ISA's
Date: Tue, 22 Jan 2002 08:56:00 -0000	[thread overview]
Message-ID: <OFFF0C6A91.B901A853-ON80256B49.005BAA63@risccores.com> (raw)


> > I'm particularly interested in CGEN's ability to describe mixed 16/32
> > bit ISA's. We have a new ISA at ARC which has a truely intermixed
> > 16/32 instruction set - basically, can I describe the ISA in CGEN?
>
> > The 32-bit instructions (and long immediates that can form part of an
> > instruction) are actually stored half-word endianized.
>
> I'm not sure what you mean by "half-word endianized".  Please clarify.

So the following pretend 32-bit instruction opcode "0x12345678" is stored:

     little-endian -> 34127856
     big-endian    -> 12345678

> I did a 16/32 port last year, though unfortunately it's proprietary,
> so it's not in the public repo.

Thanks for the snippets - I will investigate these.

Peter.

             reply	other threads:[~2002-01-22 16:56 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2002-01-22  8:56 Peter.Targett [this message]
  -- strict thread matches above, loose matches on Subject: below --
2002-01-22  3:57 Peter.Targett
2002-01-22  8:27 ` Greg McGary

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