Re: supporting mixed 16/32-bit ISA's

[Greg McGary <greg@mcgary.org>]

Peter.Targett@arccores.com writes:

> I'm particularly interested in CGEN's ability to describe mixed 16/32
> bit ISA's. We have a new ISA at ARC which has a truely intermixed
> 16/32 instruction set - basically, can I describe the ISA in CGEN?

> The 32-bit instructions (and long immediates that can form part of an
> instruction) are actually stored half-word endianized.

I'm not sure what you mean by "half-word endianized".  Please clarify.

I did a 16/32 port last year, though unfortunately it's proprietary,
so it's not in the public repo.

The CPU is spec'ed with big-endian bytes, but little-endian bits (lsb
is bit 0).  However, I wrote the CGEN port with bit-endian bits (msb
is bit 0).  This worked out best since it means the base insn always
occupies bit positions 0..15 (with lsb=0, 16-bit insns would have
the base insn at bits 0..15, but for 32-bit insns, the base insn
would be at bits 16..31)

I can give you some sanitized snippets to show how the port was setup:

;;; Architecture.

(define-arch
  (name xxx)
  (default-alignment unaligned)
  (insn-lsb0? #f)
  (machs yyy)
  (isas xxx))

;;; Instruction set parameters.

(define-isa
  (name xxx)
  (default-insn-bitsize 32)
  (base-insn-bitsize 32)
  (default-insn-word-bitsize 16)
  (liw-insns 1)
  (parallel-insns 1))

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Instruction fields.

(dnf f-op6      "6-bit opcode"                  ()  0  6)
(dnf f-dst      "destination register"          ()  6  5)
(dnf f-src      "source register"               () 11  5)
(dnf f-uimm16   "16-bit unsigned immediate"     () 16 16)

(define-ifield (name f-uimm5)
  (comment "5-bit immediate")
  (start 11) (length 5) (mode UINT)
  (encode (value pc) (if SI (eq SI value -1) (const SI 0) value))
  (decode (value pc) (if SI (eq SI value 0) (const SI -1) value))
  (minval 0) (maxval 29))

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Instruction Operands.

(define-operand (name uimm5)
  (comment "5-bit immediate, unsigned with special encoding")
  (type h-uimm5)
  (index f-uimm5)
  (handlers (parse "uimm5")))

(define-operand (name uimm16hi)
  (comment "high order 16-bit immediate, unsigned")
  (type h-uimm16)
  (index f-uimm16)
  (handlers (parse "uimm16") (print "uimm16hi")))

(define-operand (name uimm16lo)
  (comment "low order 16-bit immediate, unsigned")
  (type h-uimm16)
  (index f-uimm16)
  (handlers (parse "uimm16")))

;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;; Instruction definitions.

(define-pmacro (alu-insn mnemonic comment)
  (begin
    (dni (.sym mnemonic "2i16lo") (.str comment " / 16-bit Immediate Low") ()
         (.str mnemonic " $dst,$uimm16lo")
         (+ (.sym "OP6_" (.upcase mnemonic) "I") dst (f-uimm5 30) uimm16lo)
         (nop) ())
    (dni (.sym mnemonic "2i16hi") (.str comment " / 16-bit Immediate High") ()
         (.str mnemonic " $dst,$uimm16hi")
         (+ (.sym "OP6_" (.upcase mnemonic) "I") dst (f-uimm5 31) uimm16hi)
         (nop) ())
    (dni (.sym mnemonic "2i5") (.str comment " / 5-bit Immediate") ()
         (.str mnemonic " $dst,$uimm5")
         (+ (.sym "OP6_" (.upcase mnemonic) "I") dst uimm5)
         (nop) ())))

The field f-uimm5 is restricted to the range 0..29 because 30 and 31
are reserved to designate that a 16-bit immediate follows the base
insn.  (30 means the immediate is the low 16 bits of a 32-bit word,
and 31 means it is the high 16 bits)

I need special parse handlers for immediates in order to handle %l()
and %h() modifers that pick off the low and high halves of words, and
to range check the restricted 5-bit values.  I need special print
handler for uimm16hi in order to shift the value left before printing.

As for why I have these particular values in the define-isa:
  (default-insn-bitsize 32)
  (base-insn-bitsize 32)
  (default-insn-word-bitsize 16)
I don't remember exactly, but that's what worked!  8^)

That should be enough to get you started.

Greg