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From: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
To: Doug Evans <dje@sebabeach.org>
Cc: cgen <cgen@sourceware.org>
Subject: Re: cgen -> opcodes problem
Date: Mon, 28 Dec 2009 22:59:00 -0000	[thread overview]
Message-ID: <bc64b4640912281459s296edfc6q790a41a3afc04a5b@mail.gmail.com> (raw)
In-Reply-To: <4B39014D.4000203@sebabeach.org>

On Mon, Dec 28, 2009 at 10:04 PM, Doug Evans <dje@sebabeach.org> wrote:
> Dmitry Eremin-Solenikov wrote:
>>
>> Hello all,
>>
>> I'm back to my m68hc08 binutils port done via cgen.
>> Recently I've again stumbled upon a problem with instructions,
>> whose base? length != ISA base length.
>>
>> E.g. in the attached stripped test case, the 'ttt' instruction either
>> (should be assembled as 0x9E 0xF1) is misencoded as 0xsmth 0x00.
>> Is this my fault? Or is this the expected behaviour and I should define
>> f-seccode in some other way?
>>
>> Could you please help me?
>>
>>
>
> Hi.  cgen currently doesn't handle instructions with opcode bits beyond the
> base insn size very well.  I have a sandbox with this fixed, but it'll be
> awhile (month or more?) before it all gets checked in.
>
> In the meantime, setting base-insn-bitsize to 16 may work.  [It *should*
> work, but there may be attributes of your port I haven't taken into
> account.]

I haven't dig into that, but setting base-insn-bitsize to 16 broke
disassembler badly.


-- 
With best wishes
Dmitry

  parent reply	other threads:[~2009-12-28 22:59 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2009-12-27  8:10 Dmitry Eremin-Solenikov
2009-12-28 19:04 ` Doug Evans
2009-12-28 21:30   ` Dmitry Eremin-Solenikov
2009-12-28 21:57     ` Doug Evans
2009-12-28 22:59   ` Dmitry Eremin-Solenikov [this message]
2010-02-24 14:55   ` Dmitry Eremin-Solenikov
2010-02-24 16:49     ` Doug Evans
2010-02-26 11:39       ` Dmitry Eremin-Solenikov
2010-03-05 22:15         ` Doug Evans
2010-03-05 22:48           ` Dmitry Eremin-Solenikov
2010-03-05 22:51             ` Doug Evans

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