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* Updated: cpuid 20220620
@ 2022-07-02 17:04 Cygwin cpuid Maintainer
  0 siblings, 0 replies; only message in thread
From: Cygwin cpuid Maintainer @ 2022-07-02 17:04 UTC (permalink / raw)
  To: Cygwin Announcements

The following package has been upgraded in the Cygwin distribution:

* cpuid		20220620

The program displays detailed information about the CPU(s) gathered from
the CPUID instruction, and also determines the exact model of CPU(s).

Whereas /proc/cpuinfo is like an abstract of the features important to
Linux in a system, cpuid is a standalone utility which writes a paper
expounding on every feature in each CPU's architecture and what it can
do, at about the one line per bit level.

It is updated and released frequently to stay current with Intel and
AMD information and supports other vendors' chips.

See the project home page for more information:

For information about changes since the previous Cygwin release,
see below or /usr/share/doc/cpuid/ChangeLog after installation.


* Added (synth) for (0,6),(9,7),1 Alder Lake-S B0 from Coreboot*.
* Added (synth) stepping name for (0,6),(9,7),4 Alder Lake-U G0 from
  Coreboot* (although this dubiously mixes partly contradictory info from two sources).
* Added (synth) stepping name for (0,6),(9,7),5 Alder Lake-S H0 from Coreboot*.
* Added hypervisor+4/eax (Xen) upcalls with physical IRQ vectors from Xen*.
* Added hypervisor+{0x80,0x81,0x82} (Microsoft) synthetic debugging leaves.
* Eliminated print_header(), and distributed those headers throughout
  print_reg(), frequently using the try (subleaf) number to ensure they
  are printed only once. Many headers already were like this, and it
  makes them more consistent.
* Changed (synth) for Alder Lake-S to remove K/KF suffixes, because
  other suffixes (or no suffix) are available too.
* Added (synth) for (0,6),(9,7),5 Alder Lake-S.
* Added (synth) for (0,6),(9,7),3 Alder Lake-P/H.
* Added (synth) for (0,6),(9,7),4 Alder Lake-U.
* Added 0xf/1/eax QoS monitoring counter size, both in raw form (-24
  notation) and as a synthetic leaf the determines the value from the
  raw form and family/model information.
* Added stash information to print_header() to avoid printing Xen-only
  headers for hypervisor+3 leaves of other hypervisors.
* Rewrote the handling of subleaves (tries) for legacy raw input
  files. Originally, I thought I only needed this support for those
  leaves which existed during that legacy period. But the testbeds lean
  on that support for samples from instlatx64. So now it's more general.
* For leaf 0x80000020, rewrote the rules for subleaf processing based
  on the description in AMD64 Technology Platform Quality of Service
  Extensions (pub 56375 1.03): walk the bits in the mask.
* Added 0x80000020/0/ebx bits 2 & 3, and renamed bit 1.
* Added 0x80000020/1 subleaf header.
* Added 0x80000020/2 subleaf.
* Added 0x80000020/3 subleaf.
* man: Added 56375: AMD64 Technology Platform Quality of Service
* Added 0x8000001f/eax virtual TSC_AUX supported, from Linux kernel.
* Split 7/0/ebx decoding into Intel-specific & AMD-specific versions
  (using ugly macro to avoid code duplication), differing by bit 22:
  PCOMMIT (intel) vs. RDPID/TSC_AUX (amd).
* Added 0x80000022/eax AMD perfmon V2, from Linux kernel.
* Added 0x21 TDX guest leaf, as ASCII text (e.g. "IntelTDX    ").
* Changed (synth) for AMD (10,15),(5,*) Cezanne to also mention Barcelo,
  because instlatx64 samples show that they seem to be indistinguishable
  from cpuid information.
* Added synth decoding for stepping (0,6),(11,10),2 Raptor Lake-P
  J0 from Coreboot*.
* man: Added 344425, "Architecture Specification: Intel Trust Domain
  Extensions (Intel TDX) Module".
* Removed 7/0/ecx bus lock detection LX*, Qemu* comment, because
  it now is documented in the above.
* man: Added 343754, "Intel Trust Domain CPU Architectural Extensions".
* Added 0x12/0/eax bit 7: EVERIFYREPORT2 support, from the above.
* Corrected spelling of 7/0/ecx "RDPID: read processor ID supported".
* Clarified (synth) decoding for (10,15),(11,14) Alder Lake-N, based
  on LX*. Also added A0 stepping.
* Added defined() checks around uses of __GNUC__, __GNUC_MINOR__,
  and __GNUC_PATCHLEVEL__, as suggested by Stefan Kanthak.
* Makefile: Added -Wundef to compilation options to check the above,
  although they always are defined with gcc.
* To simplify the new #if's for __builtin_clzl, added new USE_BUILTIN_CLZL
* Added (synth) decoding for (10,15),(0,1),2 Milan B2 stepping.
* Changed (0,6),(9,10) Alder Lake synth decoding stepping names,
  based on Coreboot*, evidently from Intel doc 626774. I cannot find
  that document. Perhaps it is under NDA.
* Added (0,6),(1,9) ZhangJiang synth & uarch decoding from Google_cpu_features*.
* Added (0,7),(1,11) WuDaoKou synth & uarch decoding from Google_cpu_features*.
  Also corrected (0,7),(0,11) uarch decoding.
* Added (0,7),(3,11) LuJiaZui uarch decoding from Google_cpu_features*.
  Also simplified its synth decoding.
* Added (0,7),(5,11) YongFeng synth & uarch decoding from Google_cpu_features*.
  Still somewhat speculative.
* Added hypervisor+4/eax (Microsoft) bits 15, 17, 18.
* Added hypervisor+4/ecx (Microsoft) leaf.
* Added many hypervisor+6/eax (Microsoft) fields.
* Added hypervisor+0xa/eax (Microsoft) bit 22.
* Added hypervisor+3/ebx (Microsoft) Isolation flag, from Linux kernel
* Added hypervisor+0xc/{eax,ebx} (Microsoft) leaves, from Linux kernel
* Corrected (synth) for (0,6),(9,10) Alder Lake to report Core where
  appropriate, instead of Atom always. In fact, I've seen zero instances
  of Atoms with this core, so perhaps this was an early
  misunderstanding. The (0,6),(9,7) Alder Lake-S core was added at the
  same time, also as an Atom, but was corrected much earlier. So I've
  made the same correction here.
* Added (synth) decoding for (8,15),(9,0),2 Van Gogh A2 from instlatx64 sample.
* Added (synth) decoding for (0,6),(10,10),{0-1} A0 steppings, based on
  info from Coreboot*.

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2022-07-02 17:04 Updated: cpuid 20220620 Cygwin cpuid Maintainer

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