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From: Ken Brown <kbrown@sourceware.org>
To: cygwin-cvs@sourceware.org
Subject: [newlib-cygwin] fhandler_proc.cc(format_proc_cpuinfo): fix cache size
Date: Mon, 07 Oct 2019 19:55:00 -0000 [thread overview]
Message-ID: <20191007195510.109137.qmail@sourceware.org> (raw)
https://sourceware.org/git/gitweb.cgi?p=newlib-cygwin.git;h=acc8849f844f2dbc41ef8da9687bbe1c1d5b3bdc
commit acc8849f844f2dbc41ef8da9687bbe1c1d5b3bdc
Author: Brian Inglis <Brian.Inglis@SystematicSW.ab.ca>
Date: Mon Oct 7 10:22:58 2019 -0600
fhandler_proc.cc(format_proc_cpuinfo): fix cache size
Fix cache size return code handling and make AMD/Intel code common.
Diff:
---
winsup/cygwin/fhandler_proc.cc | 45 +++++++++++++++++-------------------------
1 file changed, 18 insertions(+), 27 deletions(-)
diff --git a/winsup/cygwin/fhandler_proc.cc b/winsup/cygwin/fhandler_proc.cc
index 48476be..13cc368 100644
--- a/winsup/cygwin/fhandler_proc.cc
+++ b/winsup/cygwin/fhandler_proc.cc
@@ -744,6 +744,8 @@ format_proc_cpuinfo (void *, char *&destbuf)
int cache_size = -1,
clflush = 64,
cache_alignment = 64;
+ long (*get_cpu_cache) (int, uint32_t) = NULL;
+ uint32_t max;
if (features1 & (1 << 19)) /* CLFSH */
clflush = ((extra_info >> 8) & 0xff) << 3;
if (is_intel && family == 15)
@@ -751,45 +753,34 @@ format_proc_cpuinfo (void *, char *&destbuf)
if (is_intel)
{
extern long get_cpu_cache_intel (int sysc, uint32_t maxf);
- long cs;
-
- cs = get_cpu_cache_intel (_SC_LEVEL3_CACHE_SIZE, maxf);
- if (cs == -1)
- cs = get_cpu_cache_intel (_SC_LEVEL2_CACHE_SIZE, maxf);
- if (cs == -1)
- {
- cs = get_cpu_cache_intel (_SC_LEVEL1_ICACHE_SIZE, maxf);
- if (cs != -1)
- cache_size = cs;
- cs = get_cpu_cache_intel (_SC_LEVEL1_DCACHE_SIZE, maxf);
- if (cs != -1)
- cache_size += cs;
- }
- else
- cache_size = cs;
- if (cache_size != -1)
- cache_size >>= 10;
+ get_cpu_cache = get_cpu_cache_intel;
+ max = maxf; /* Intel uses normal cpuid levels */
}
else if (is_amd)
{
extern long get_cpu_cache_amd (int sysc, uint32_t maxe);
+ get_cpu_cache = get_cpu_cache_amd;
+ max = maxe; /* AMD uses extended cpuid levels */
+ }
+ if (get_cpu_cache)
+ {
long cs;
- cs = get_cpu_cache_amd (_SC_LEVEL3_CACHE_SIZE, maxe);
- if (cs == -1)
- cs = get_cpu_cache_amd (_SC_LEVEL2_CACHE_SIZE, maxe);
- if (cs == -1)
+ cs = get_cpu_cache (_SC_LEVEL3_CACHE_SIZE, max);
+ if (cs <= 0)
+ cs = get_cpu_cache (_SC_LEVEL2_CACHE_SIZE, max);
+ if (cs <= 0)
{
- cs = get_cpu_cache_amd (_SC_LEVEL1_ICACHE_SIZE, maxe);
- if (cs != -1)
+ cs = get_cpu_cache (_SC_LEVEL1_ICACHE_SIZE, max);
+ if (cs > 0)
cache_size = cs;
- cs = get_cpu_cache_amd (_SC_LEVEL1_DCACHE_SIZE, maxe);
- if (cs != -1)
+ cs = get_cpu_cache (_SC_LEVEL1_DCACHE_SIZE, max);
+ if (cs > 0)
cache_size += cs;
}
else
cache_size = cs;
- if (cache_size != -1)
+ if (cache_size > 0)
cache_size >>= 10;
}
bufptr += __small_sprintf (bufptr, "cpu family\t: %d\n"
reply other threads:[~2019-10-07 19:55 UTC|newest]
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