[Bug 1000681] New: PXA GPIO registers not properly configured for detecting IRQs

[Bug 1000681] New: PXA GPIO registers not properly configured for detecting IRQs

[bugzilla-daemon]

http://bugzilla.ecoscentric.com/show_bug.cgi?id=1000681

           Summary: PXA GPIO registers not properly configured for detecting
                    IRQs
           Product: eCos
           Version: CVS
          Platform: Other (please specify)
        OS/Version: HostOS: Win NT/2k/XP
            Status: UNCONFIRMED
          Severity: major
          Priority: normal
         Component: HAL
        AssignedTo: jifl@ecoscentric.com
        ReportedBy: beato@tid.es
         QAContact: ecos-bugs@ecos.sourceware.org
             Class: ---


I have been porting the code for our platform from eCos 2.0 to the latest eCos
code. This platform is based on a PXA255 microprocessor. One of the code pieces
was a driver for an external usb slave chip (ISP1581), which worked correctly
with eCos 2.0. We found that compiling against the latest code, no interrupt
was detected and our ISR was never called. The IRQ of the usb chip is connected
to GPIO 5 in the PXA. After some investigation, we found the problem: the HAL
was not setting properly PXA register GFER0: the bit to detect falling edges in
GPIO 5 was not activated. After setting GFER0 properly in our code, the ISR
finally got called. We checked the value of this register compiling against
eCos 2.0 and we found that the kernel correctly activates the bit for GPIO 5 in
GFER0 in that case. We set always:

cyg_drv_interrupt_configure([PXA_GPIO5_IRQ], false, false);

so the interrupt is active by falling edge.


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[Bug 1000681] PXA GPIO registers not properly configured for detecting IRQs

[bugzilla-daemon]

http://bugzilla.ecoscentric.com/show_bug.cgi?id=1000681





--- Comment #1 from Alfonso Sanchez <beato@tid.es>  2009-03-23 14:26:39 ---
Created an attachment (id=680)
 --> (http://bugzilla.ecoscentric.com/attachment.cgi?id=680)
Patch to pxa2x0_misc.c

There was a problem in pxa2x0_misc.c, where registers GFER1 and GRER1 where
being used for for GPIOs 2 to 31 instead of the right registers, GFER0 and
GRER0. This can cause problems for GPIOs from 2 to 63. I hope the patch gets
included in eCos 3.0, as I think it is an important bug for the PXA
architecture.


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