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* [Bug 1001133] New: STM32 SPI APB1 and APB2 bus clock frequency issue
@ 2011-01-27 13:53 bugzilla-daemon
  0 siblings, 0 replies; 2+ messages in thread
From: bugzilla-daemon @ 2011-01-27 13:53 UTC (permalink / raw)
  To: ecos-bugs

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http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001133

           Summary: STM32 SPI APB1 and APB2 bus clock frequency issue
           Product: eCos
           Version: unknown
          Platform: All
        OS/Version: Cortex-M
            Status: UNCONFIRMED
          Severity: minor
          Priority: low
         Component: SPI
        AssignedTo: unassigned@bugs.ecos.sourceware.org
        ReportedBy: martin.blaser@intefo.ch
                CC: ecos-bugs@ecos.sourceware.org
             Class: Advice Request


The STM32 SPI driver implementation calculates the bus clock frequencies APB1
and APB2 with two #define. These defines do not consider that the HSE input
clock could be divided by 2
(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE_HALF). If this option is
enabled, the frequencies are too high.

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^ permalink raw reply	[flat|nested] 2+ messages in thread

* [Bug 1001133] New: STM32 SPI APB1 and APB2 bus clock frequency issue
@ 2011-01-27 13:53 bugzilla-daemon
  0 siblings, 0 replies; 2+ messages in thread
From: bugzilla-daemon @ 2011-01-27 13:53 UTC (permalink / raw)
  To: unassigned

Please do not reply to this email. Use the web interface provided at:
http://bugs.ecos.sourceware.org/show_bug.cgi?id=1001133

           Summary: STM32 SPI APB1 and APB2 bus clock frequency issue
           Product: eCos
           Version: unknown
          Platform: All
        OS/Version: Cortex-M
            Status: UNCONFIRMED
          Severity: minor
          Priority: low
         Component: SPI
        AssignedTo: unassigned@bugs.ecos.sourceware.org
        ReportedBy: martin.blaser@intefo.ch
                CC: ecos-bugs@ecos.sourceware.org
             Class: Advice Request


The STM32 SPI driver implementation calculates the bus clock frequencies APB1
and APB2 with two #define. These defines do not consider that the HSE input
clock could be divided by 2
(CYGHWR_HAL_CORTEXM_STM32_CLOCK_PLL_SOURCE_HSE_HALF). If this option is
enabled, the frequencies are too high.

-- 
Configure bugmail: http://bugs.ecos.sourceware.org/userprefs.cgi?tab=email
------- You are receiving this mail because: -------
You are the assignee for the bug.


^ permalink raw reply	[flat|nested] 2+ messages in thread

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