[Issue 1001154] New: HAL_DISABLE_INTERRUPTS miscompile on Cortex-M3

[Issue 1001154] New: HAL_DISABLE_INTERRUPTS miscompile on Cortex-M3

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           Summary: HAL_DISABLE_INTERRUPTS miscompile on Cortex-M3
           Product: eCos
           Version: CVS
          Platform: Other (please specify)
        OS/Version: Cortex-M
            Status: UNCONFIRMED
          Severity: major
          Priority: low
         Component: HAL
        AssignedTo: unassigned@bugs.ecos.sourceware.org
        ReportedBy: stano@meduna.org
                CC: ecos-bugs@ecos.sourceware.org
             Class: Advice Request


the arm-eabi-gcc from the eCos distribution sometimes miscompiles
HAL_DISABLE_INTERRUPTS macro for Cortex-M3:

Macro:

# define HAL_DISABLE_INTERRUPTS(__old)          \
    __asm__ volatile (                          \
        "mrs    %0, basepri             \n"     \
        "mov    r1,%1                   \n"     \
        "msr    basepri,r1              \n"     \
        : "=r" (__old)                          \
        :  "r" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\
        : "r1"                                  \
        );

Code:

60133e26:    f04f 0320     mov.w    r3, #32
60133e2a:    f3ef 8311     mrs    r3, BASEPRI
60133e2e:    4619          mov    r1, r3
60133e30:    f381 8811     msr    BASEPRI, r1
60133e34:    613b          str    r3, [r7, #16]

That results in HAL_DISABLE_INTERRUPTS effectively being a nop with all kinds
of subsequent crashes.

The problem is that the output (%0) is clobbered before using the input (%1). 

Either
       :  "I" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\
or
        : "=&r" (__old)                          \
fix the problem.

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[Issue 1001154] New: HAL_DISABLE_INTERRUPTS miscompile on Cortex-M3

[bugzilla-daemon]

Please do not reply to this email. Use the web interface provided at:
http://bugzilla.ecoscentric.com/show_bug.cgi?id=1001154

           Summary: HAL_DISABLE_INTERRUPTS miscompile on Cortex-M3
           Product: eCos
           Version: CVS
          Platform: Other (please specify)
        OS/Version: Cortex-M
            Status: UNCONFIRMED
          Severity: major
          Priority: low
         Component: HAL
        AssignedTo: unassigned@bugs.ecos.sourceware.org
        ReportedBy: stano@meduna.org
                CC: ecos-bugs@ecos.sourceware.org
             Class: Advice Request


the arm-eabi-gcc from the eCos distribution sometimes miscompiles
HAL_DISABLE_INTERRUPTS macro for Cortex-M3:

Macro:

# define HAL_DISABLE_INTERRUPTS(__old)          \
    __asm__ volatile (                          \
        "mrs    %0, basepri             \n"     \
        "mov    r1,%1                   \n"     \
        "msr    basepri,r1              \n"     \
        : "=r" (__old)                          \
        :  "r" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\
        : "r1"                                  \
        );

Code:

60133e26:    f04f 0320     mov.w    r3, #32
60133e2a:    f3ef 8311     mrs    r3, BASEPRI
60133e2e:    4619          mov    r1, r3
60133e30:    f381 8811     msr    BASEPRI, r1
60133e34:    613b          str    r3, [r7, #16]

That results in HAL_DISABLE_INTERRUPTS effectively being a nop with all kinds
of subsequent crashes.

The problem is that the output (%0) is clobbered before using the input (%1). 

Either
       :  "I" (CYGNUM_HAL_CORTEXM_PRIORITY_MAX)\
or
        : "=&r" (__old)                          \
fix the problem.

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