From: Rutger Hofman <rutger@cs.vu.nl>
To: Andrew Lunn <andrew@lunn.ch>
Cc: Ross Younger <wry@ecoscentric.com>,
"ecos-devel@ecos.sourceware.org"
<ecos-devel@ecos.sourceware.org>
Subject: Re: NAND review
Date: Wed, 03 Jun 2009 12:26:00 -0000 [thread overview]
Message-ID: <4A266C50.2030301@cs.vu.nl> (raw)
In-Reply-To: <20090603104817.GC27508@lunn.ch>
Andrew Lunn wrote:
>> The philosophical question for us all is whether NAND on its own should be
>> allowed to use malloc, given that a NAND array will probably always be used
>> in conjunction with a log-structured filesystem which will chew up
>> comparatively large amounts of RAM (and, of course, RAM is forever getting
>> cheaper). Is this a corner or even N-dimensional vertex case; will it
>> necessarily always be the case that a device with NAND flash will have
>> enough RAM to support it? Do boards with NAND but not much RAM exist, and if
>> so do we care about them?
>
> The answer is yes. Simon, could you describe your board. From what i
> understand you don't have much RAM.
As I didn't want to tie the NAND user to malloc, I designed in a
pluggable allocator. Often, the application can calculate beforehand how
much memory is needed: 1) BBT, which depends on the NAND size; 2)
per-thread space for the error handling. If there is no threaded kernel,
it would be just the BBT which can be allocated statically by the
application/platform.
>>> Rutgers API allows reading/writing less than a page, eg just a few
>>> bytes. Ross's API is page based. I don't know if this is an advantage
>>> or a disadvantage.
>> This is a tough one to call. I went for simplicity and a tight mapping to
>> the hardware. One could argue that providing a bytewise API might encourage
>> programmers unfamiliar with NAND flash to use it in a bytewise manner and
>> risk prematurely wearing out their chips. (I believe MTD has something along
>> these lines. "If it looks like a hammer...")
The number of writes to a page between erases is often severely limited,
like 2 or 4. Therefore bytewise writes are not really an option.
> That is what i was thinking. Bytewise read makes more sense than
> writing. Also, if the underlying chipset does not support bytewise
> reading/writing, you end up needing a page buffer low down in the
> stack, rather up in the application where it might be reusable for
> other things when memory is tight.
The file systems I took a look at read/write a complete page. NAND chips
all support byte/word addressing, though. Like Andrew and Ross, I am not
completely certain which is the best way to go. Limiting reads and
writes to complete pages would make the code a little bit simpler in one
or two places.
Rutger
next prev parent reply other threads:[~2009-06-03 12:26 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2009-05-19 8:27 Simon Kallweit
2009-05-19 13:47 ` Ross Younger
2009-05-19 14:17 ` Andrew Lunn
2009-05-20 13:24 ` Bart Veer
2009-05-20 13:34 ` Rutger Hofman
2009-05-20 13:53 ` Andrew Lunn
2009-05-20 13:56 ` Gary Thomas
2009-05-20 14:22 ` Andrew Lunn
2009-05-20 15:22 ` Andrew Lunn
2009-05-20 15:34 ` Bart Veer
2009-05-20 13:58 ` Rutger Hofman
2009-05-20 14:16 ` Ross Younger
2009-05-20 14:21 ` Gary Thomas
2009-05-20 15:25 ` Ross Younger
2009-05-20 15:37 ` Gary Thomas
2009-05-19 16:29 ` Andrew Lunn
2009-06-03 8:51 ` Andrew Lunn
2009-06-03 10:21 ` Ross Younger
2009-06-03 10:48 ` Andrew Lunn
2009-06-03 11:52 ` Simon Kallweit
2009-06-03 12:26 ` Rutger Hofman [this message]
2009-06-03 13:33 ` Jürgen Lambrecht
2009-06-10 17:39 ` Nick Garnett
2009-06-11 11:25 ` Rutger Hofman
2009-06-13 16:31 ` Andrew Lunn
2009-06-18 14:10 ` Nick Garnett
2009-06-19 7:47 ` Andrew Lunn
2009-06-19 14:14 ` Ross Younger
2009-06-19 15:02 ` Andrew Lunn
2009-06-19 16:54 ` Jürgen Lambrecht
2009-06-29 11:09 ` Nick Garnett
2009-06-19 8:07 ` Andrew Lunn
2009-06-19 11:37 ` Daniel Morris
2009-06-19 12:06 ` Andrew Lunn
2009-05-20 1:02 ` Jonathan Larmour
2009-05-20 7:11 ` Simon Kallweit
2009-05-20 11:12 ` Rutger Hofman
2009-05-20 11:29 ` Simon Kallweit
2009-05-20 13:37 ` Rutger Hofman
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