Cortex-M Vector Table Offset

[Ilija Kocho <ilijak@siva.com.mk>]

Hello

In a course of porting eCos to Cortex-M based devices, other than STM32,
an issue occurs that must be addressed.

The problem (In following discussion I refer to ROM start-up configuration):

In current Cortex-M port the Vector Table Offset is fixed (VTOR set) by
architecture port to 0x20000000 (CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM
defined in hal/cortexm/arch/<version>/include/hal_io.h). This is the
place where it should be expected but on some devices this is not possible:

The example is NXP LPC 17xx family that has no RAM in Data (SRAM)
partition (i.e. at 0x20000000). Instead SRAM is located within Code
partition at address 0x10000000.

Proposed solution:

Define Vector Table base (CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM) in the
variant with override option for the platform: respective var_io.h
and/or plf_io.h.

Also there is apparent dependence between
CYGARC_REG_NVIC_VTOR_TBLBASE_SRAM and devices' memory configuration(s)
so we could consider some shared defines with pkgconf files and/or CDL.
This could provide flexibility useful for some other devices such as
Freescale Kinetis family.

Patch(es) should be easy and harmless. I could produce ones after
discussion.

For the end I have one question: What is use of
CYGARC_REG_NVIC_VTOR_TBLOFF(0) (hal/cortexm/arch/current/src/hal_misc.c)

Best regards
Ilija