From: Nick Garnett <nickg@ecoscentric.com>
To: "Christophe Coutand" <ccoutand@stmi.com>
Cc: "Nagaraj K" <nagaraj.kmurthy@gmail.com>,
<ecos-devel@ecos.sourceware.org>
Subject: Re: Cortex-M3 HAL interrupt-priority code bug
Date: Thu, 25 Nov 2010 12:10:00 -0000 [thread overview]
Message-ID: <m3mxoxvc2o.fsf@xl5.calivar.com> (raw)
In-Reply-To: <m3r5e9vcel.fsf@xl5.calivar.com>
Nick Garnett <nickg@ecoscentric.com> writes:
> "Christophe Coutand" <ccoutand@stmi.com> writes:
>
> > My understanding is:
> >
> > CYGNUM_HAL_CORTEXM_PRIORITY_MAX is defined equal to
> > 1<<(8-CYGNUM_HAL_CORTEXM_PRIORITY_LEVEL_BITS)
> >
> > What the eCos implementation really does is to reserved level 0 for
> > DEBUG and SVC traps. If you call hal_interrupt_set_level with level 0
> > what you will really get is a priority of 1. Nothing wrong with that?
>
> This is intensional. The Cortex-M3 prioritizes exceptions alongside
> interrupts in the same number space. If you try and throw an
> exception, such as a breakpoint, of the same, or lower, priority as
> the current level then the processor takes a Hard Fault, which is
> unrecoverable. The simplest solution to this is to set all exceptions
> to the highest priority, zero, and ensure that no interrupts have that
> priority. In practice the highest priority interrupt actually needs to
> be set to the highest real priority implemented by the CPU.
That should of course read: ...set to the *next* highest real priority...
--
Nick Garnett eCos Kernel Architect
eCosCentric Limited http://www.eCosCentric.com The eCos experts
Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571
Registered in England and Wales: Reg No: 4422071
next prev parent reply other threads:[~2010-11-25 12:10 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-25 10:34 Nagaraj K
2010-11-25 11:19 ` Nick Garnett
2010-11-25 11:26 ` Christophe Coutand
2010-11-25 12:03 ` Nick Garnett
2010-11-25 12:10 ` Nick Garnett [this message]
2010-11-25 14:29 ` Nagaraj K
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