From: Nick Garnett <nickg@ecoscentric.com>
To: Nagaraj K <nagaraj.kmurthy@gmail.com>
Cc: ecos-devel@ecos.sourceware.org
Subject: Re: Cortex-M3 HAL interrupt-priority code bug
Date: Thu, 25 Nov 2010 11:19:00 -0000 [thread overview]
Message-ID: <m3vd3lvefs.fsf@xl5.calivar.com> (raw)
In-Reply-To: <AANLkTikH4CxinV6F9SNPC1Btr1byV_HuJaOSQMAz1bAX@mail.gmail.com>
Nagaraj K <nagaraj.kmurthy@gmail.com> writes:
> I see that this function wrongly implements the priority level in
> Cortex-M3 processor. According to the Cortex-M3 data sheet, we need to
> write the priority level to the top N bits of the register where N is
> the number of priority level bits implemented in this particular
> version of the cortex variant.
The intention in the design of the hardware is that software can use a
256 level prioirity scheme on all implementations. By defining the
actual priority in terms of the top N bits of the registers, the
hardware essentially groups the 256 virtual priorities into a set of
real priorities by ignoring the less significant bits.
eCos simply follows the lead given by the hardware and implements 256
priorities. It is a good scheme and allows us to write code that will
work in all implementations.
--
Nick Garnett eCos Kernel Architect
eCosCentric Limited http://www.eCosCentric.com The eCos experts
Barnwell House, Barnwell Drive, Cambridge, UK. Tel: +44 1223 245571
Registered in England and Wales: Reg No: 4422071
next prev parent reply other threads:[~2010-11-25 11:19 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-11-25 10:34 Nagaraj K
2010-11-25 11:19 ` Nick Garnett [this message]
2010-11-25 11:26 ` Christophe Coutand
2010-11-25 12:03 ` Nick Garnett
2010-11-25 12:10 ` Nick Garnett
2010-11-25 14:29 ` Nagaraj K
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