* [ECOS]exception stack
@ 2001-02-14 8:34 james chen
0 siblings, 0 replies; only message in thread
From: james chen @ 2001-02-14 8:34 UTC (permalink / raw)
To: ecos-discuss
Hello,
In vectors.S (hal/arm/arch/current/src/vectors.S), sp register in each
ARM state had been initialized during rest vector, but in
undefined_instruction code, the first instruction is initializing the sp
register again with different stack, the undef_exception_stack is larger
than exception_stack. Is it done for special reason or other? may anyone
tell me why, thanks!
========================================================
.global start
start:
// initialize interrupt/exception environments
ldr sp,.__startup_stack
mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_IRQ_MODE)
msr cpsr,r0
ldr sp,.__exception_stack
mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_UNDEF_MODE)
msr cpsr,r0
ldr sp,.__exception_stack
// initialize CPSR (machine state register)
mov r0,#(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
msr cpsr,r0
// Note: some functions in LIBGCC1 will cause a "restore from
SPSR"!!
msr spsr,r0
// initialize stack
ldr sp,.__startup_stack
.................
//
// Exception handlers
// Assumption: get here from a Supervisor context [mode]
//
.code 32
undefined_instruction:
ldr sp,.__undef_exception_stack // get good stack
stmfd sp!,{r0,fp,ip,lr}
mrs r0,spsr
stmfd sp!,{r0}
mov ip,sp // save SP which will vanish with
// mode switch
.......
// -------------------------------------------------------------------------
// Temporary interrupt stack
.section ".bss"
// Small stacks, only used for saving information between CPU modes
__exception_stack_base:
.rept 32
.long 0
.endr
__exception_stack:
.rept 32
.long 0
.endr
__undef_exception_stack:
.........
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