[ECOS] PowerPC FEC problems

[ken king <kknhuntsville@yahoo.com>]

I have a custom MPC852T board. (note:
Custom means porting RedBoot/eCOS and checking board
out at same time!) I've gotten RedBoot up and
almost everything works except ethernet. I
started with if_fec.c. The MII interface seems to
be working correctly, MDC clock is correct
frequency, reasionable data back and forth, etc.

When running gdb and a BDM I get a
"Trace/breakpoint" when there is no break point
set -- generally a bad thing! I tracked it down
to:

fec_eth_send()
{
...........
	/* comment out next line --
	** no bad trace/breakpoint*/
	qi->fec->TxUpdate=0x10000;
......
	}

I've written some code to look at the FEC regs
before and after the offending line of code.
Before, everything looks good. After;

1-- I_EVENT reg has EB_ERR set -- FEC encountered
a bus error.

2-- Eth Control Reg has eth disabled.

If I #define for buffer descriptors to be in
external memory, then the Transfure Error Status
Reg (TESR) has IEXT set indicating a /TEA signal
was present during a external instruction fetch.
/TEA is just connected to a pull-up resistor, I've
looked at it with a scope - doesn't look shorted
to anything.

So, Long-story-short I think I getting a bus error
when the FEC DMA kicks off. Anybody seen this
before? Any ideas? What else to look for?

TIA,
KK

PS Im think of giving up on this FEC thing for a
while. I have one more PHY connected to a SCC,
would you recomend I start with the Adder or QUICC
eth driver?



		
Discover Yahoo! 
Find restaurants, movies, travel and more fun for the weekend. Check it out! 
http://discover.yahoo.com/weekend.html 


-- 
Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
and search the list archive: http://ecos.sourceware.org/ml/ecos-discuss