Re: [ECOS] PowerPC FEC problems

[Andrew Lunn <andrew@lunn.ch>]

On Thu, May 05, 2005 at 07:02:33PM -0700, ken king wrote:
> I have a custom MPC852T board. (note:
> Custom means porting RedBoot/eCOS and checking board
> out at same time!) I've gotten RedBoot up and
> almost everything works except ethernet. I
> started with if_fec.c. The MII interface seems to
> be working correctly, MDC clock is correct
> frequency, reasionable data back and forth, etc.
> 
> When running gdb and a BDM I get a
> "Trace/breakpoint" when there is no break point
> set -- generally a bad thing! I tracked it down
> to:
> 
> fec_eth_send()
> {
> ...........
> 	/* comment out next line --
> 	** no bad trace/breakpoint*/
> 	qi->fec->TxUpdate=0x10000;
> ......
> 	}
> 
> I've written some code to look at the FEC regs
> before and after the offending line of code.
> Before, everything looks good. After;
> 
> 1-- I_EVENT reg has EB_ERR set -- FEC encountered
> a bus error.
> 
> 2-- Eth Control Reg has eth disabled.
> 
> If I #define for buffer descriptors to be in
> external memory, then the Transfure Error Status
> Reg (TESR) has IEXT set indicating a /TEA signal
> was present during a external instruction fetch.
> /TEA is just connected to a pull-up resistor, I've
> looked at it with a scope - doesn't look shorted
> to anything.
> 
> So, Long-story-short I think I getting a bus error
> when the FEC DMA kicks off. Anybody seen this
> before? Any ideas? What else to look for?

Check the addresses you are using from receive and transmit buffers.
Do you remember to map the virtual addresses into bus addresses before
programming them into the ethernet device? Does memory realy exist at
the address? 

        Andrew

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