[ECOS] IXP425 Big Endian Mode

[ECOS] IXP425 Big Endian Mode

[Sujoy Ray]

Hello All,

I am just going through the redboot source code for
IXP425 and found the following line in
HAL_PLATFORM_SETUP.h

#ifdef CYGINT_HAL_ARM_BIGENDIAN
       // set big-endian
       mrc	p15, 0, r0, c1, c0, 0
       orr		r0, r0, #0x80
       mcr	p15, 0, r0, c1, c0, 0
      CPWAIT  r0
#endif

I understand that these lines are for changing the
processor mode into Big-endian. I have seen that
Redboot for IXP425 has been compiled and linked in
Big-endian mode - this I further confirmed using
objdump. But at reset IXP425 starts operation in
little endian mode. Now, in order the switch the
endianness, the processor should be able to execute
the above mentioned code and this code is in
big-endian order. Now, I have a question - how the
processor executes the above mentioned code, when it
is in little endian mode. I know for sure that there
is some way to do that because the code works fine. I
think 'am missing some basic concept - any suggestion
will be highly appreciated.

Thanks in advance,

Sujoy Ray.


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Re: [ECOS] IXP425 Big Endian Mode

[Peter Korsgaard]

On 6/10/05, Sujoy Ray <raysujoy@yahoo.com> wrote:
> big-endian order. Now, I have a question - how the
> processor executes the above mentioned code, when it
> is in little endian mode. I know for sure that there
> is some way to do that because the code works fine. I
> think 'am missing some basic concept - any suggestion
> will be highly appreciated.

big/little endian mode only matters for 8 and 16bit accesses, and the
instructions are 32bit.

See http://www.intel.com/design/network/applnots/25423701.pdf for details.

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Re: [ECOS] IXP425 Big Endian Mode

[Sujoy Ray]

Hello Peter,

Thanks for your suggestion!

I am still having one doubt -

When I compare the code(pls read elf file) compiled in
little endian mode with the one in big endian mode
using objdump - I see that bytes are swapped. E.g a
code which looks like E6000021 in little endian mode
becomes 210000E6 in big endian mode. Now, during
instruction fetch and decode cycle, how processor
decodes this big endian instruction, when the state of
the processor is in little endian? Pls note that the
processor is in little endian mode and trying to
execute a big-endian instruction. So, byte 0 for it
will be E6 of the big endian instruction, but the
correct one should be 21. 

I think 'am confused in some way. Please help me to
come out from this confusion.

Regards,
Sujoy Ray.


--- Peter Korsgaard <jacmet@gmail.com> wrote:

> On 6/10/05, Sujoy Ray <raysujoy@yahoo.com> wrote:
> > big-endian order. Now, I have a question - how the
> > processor executes the above mentioned code, when
> it
> > is in little endian mode. I know for sure that
> there
> > is some way to do that because the code works
> fine. I
> > think 'am missing some basic concept - any
> suggestion
> > will be highly appreciated.
> 
> big/little endian mode only matters for 8 and 16bit
> accesses, and the
> instructions are 32bit.
> 
> See
>
http://www.intel.com/design/network/applnots/25423701.pdf
> for details.
> 
> -- 
> Bye, Peter Korsgaard
> 


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Re: [ECOS] IXP425 Big Endian Mode

[jerzy dyrda]

 Hello All,

> Thanks for your suggestion!
>
> I am still having one doubt -
>
> When I compare the code(pls read elf file) compiled in
> little endian mode with the one in big endian mode
> using objdump - I see that bytes are swapped. E.g a
> code which looks like E6000021 in little endian mode
> becomes 210000E6 in big endian mode. Now, during
> instruction fetch and decode cycle, how processor
> decodes this big endian instruction, when the state of
> the processor is in little endian? Pls note that the
> processor is in little endian mode and trying to
> execute a big-endian instruction. So, byte 0 for it
> will be E6 of the big endian instruction, but the
> correct one should be 21.
>
> I think 'am confused in some way. Please help me to
> come out from this confusion.
#ifdef CYGINT_HAL_ARM_BIGENDIAN
       // set big-endian
       mrc      p15, 0, r0, c1, c0, 0
       orr              r0, r0, #0x80
       mcr      p15, 0, r0, c1, c0, 0
      CPWAIT  r0
#endif

If I can I explain my point of view. Above code regards external bus - before 
change this bus works in little endian address coherend mode ( see docu. 
regarding address and data cohered mode  - this is a Intel "discover"). Core 
as I saw always works in big endian mode - to run code  you must just swap 
code compiled in little endian. Please see to this discuss list - someone ask 
how to start window$ CE ( their compiler works only in little endian)

Best Regards,
jerzy

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[ECOS] IXP425 Big Endian Mode

[Sujoy Ray]

Hello ALL,
Let me thank you all for the suggestion I received on
this topic. After my hectic office schedule, I managed
to devote some time on the issue and finally I could
find the answer. I thought to share my finding with
this message board for future developers who might
have the same confusion as I had. Here are the
details:-

1) IXP425 core always boots in Little endian mode
only. If we choose Big endian mode during compilation,
we need to SWAP the bytes during program
download/flashing so that the XSCALE core can always
see the code in little endian only.

2) BIG endian mode is only related to data storage.
So, if enabled processor will read/write the data in
Big endian mode.

3) Code execution always in little endian mode only.

Any thoughts will be highly appreciated.

Thanks and regards,
Sujoy Ray.





		
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