[ECOS] MMU question - AT91RM9200

[ECOS] MMU question - AT91RM9200

[Juergen Wischer]

Hello,

I have a problem with the right setup of my mmu table.

For testing I load the Redboot ROMRAM image at 0x20300000, where it is
relocated to 0x20000000. Without mmu everything works fine.

When I enable the mmu after following initialization:
ttb_base = 0x20400000
X_ARM_MMU_SECTION(0x200,  0x200,   4,  ARM_UNCACHEABLE,  
ARM_UNBUFFERABLE,   ARM_ACCESS_PERM_RW_RW);

(macro from the AAED2000 board)

I get the problem that my code hangs at the end of the PLATFORM_SETUP1
macro. So there must be a mistake in the mmu init....

hardware:
AT91RM9200 - ARM920T core
0x20000000 - 0x21FFFFFF (RAM)

I hope there somebody out here who can help me with this problem.

Thanks,
Jürgen

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Re: [ECOS] MMU question - AT91RM9200

[Andrew Lunn]

On Thu, Jun 30, 2005 at 05:27:58PM +0200, Juergen Wischer wrote:
> Hello,
> 
> I have a problem with the right setup of my mmu table.
> 
> For testing I load the Redboot ROMRAM image at 0x20300000, where it is
> relocated to 0x20000000. Without mmu everything works fine.
> 
> When I enable the mmu after following initialization:
> ttb_base = 0x20400000
> X_ARM_MMU_SECTION(0x200,  0x200,   4,  ARM_UNCACHEABLE,  
> ARM_UNBUFFERABLE,   ARM_ACCESS_PERM_RW_RW);
> 
> (macro from the AAED2000 board)
> 
> I get the problem that my code hangs at the end of the PLATFORM_SETUP1
> macro. So there must be a mistake in the mmu init....
> 
> hardware:
> AT91RM9200 - ARM920T core
> 0x20000000 - 0x21FFFFFF (RAM)

What you want is the MMU to map the physical RAM to virtual address
0x0. You need this so that the interrupt vectors, which are at 0x0,
are in RAM not ROM so you can change them.

This also means your RedBoot must be linked so that it runs at address
0x0, not 0x20000000.

Also, the ttb_base looks wrong. It seems to be too high up in
memory. I would expect it to be low down. I know the EBSA285 setup,
which is a StrongARM. That has the reset vectors at 0x0. It then puts
the ttb in the next "page", and then Redboot's code section comes
next. I say "page" but its not strictly a page. The ttb has to start
on some specified boundary, 16Kb or something, which i cannot remember
fstright of the top of my head.

You seem to have the ttb in the middle of memory where it might get
over written by the application.

Also the ARM_UNCACHEABLE ARM_UNBUFFERABLE does not look right. You
want your RAM cachabe and bufferable for performance. I would expect
your FLASH to be UNCACHABLE and UNBUFFERABLE. Maybe you have these
mixed up?

        Andrew

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