Re: Cache and MMU support for PowerPC

Re: Cache and MMU support for PowerPC

[Fred Fierling]

Stuart Adams wrote:

> Not yet, here is the comment in hal_cache.h
>
>   // FIXME:
>   // The revision A.2 MPC860 might do all sorts of horrible things to
>   // the cache contents in a few specific (and unlikely)
>   // situations. However, as I don't feel like being bitten by these,
>   // leave caches disabled at all times.

Development of cache and MMU support is something
we'd be interested in.  Is anyone else?

--
Fred Fierling                           Tel: +1 604 444-1717
Microplex Systems Ltd.                  Fax: +1 604 444-4239
8525 Commerce Court                 mailto:fff@microplex.com
Burnaby, BC   V5A 4N3               http://www.microplex.com/

Re: Cache and MMU support for PowerPC

[Stuart Adams]

> I've gone through the on-line information but am still
> wondering if the PowerPC version of eCos includes
> support for the MPC860's cache and MMU.  Can anyone
> save me from pouring through the code to determine if
> it does?

Not yet, here is the comment in hal_cache.h

  // FIXME:
  // The revision A.2 MPC860 might do all sorts of horrible things to
  // the cache contents in a few specific (and unlikely)
  // situations. However, as I don't feel like being bitten by these,
  // leave caches disabled at all times.

Also, the MMU needs to be enabled for the cache's to work and I don't
see code for that. It's going to be board dependent anyway. Also, once
you enable the cache there are additional issues with dealing with 
the CPM to do I/O.

-- Stuart

Cache and MMU support for PowerPC

[Fred Fierling]

I've gone through the on-line information but am still
wondering if the PowerPC version of eCos includes
support for the MPC860's cache and MMU.  Can anyone
save me from pouring through the code to determine if
it does?

--
Fred Fierling                           Tel: +1 604 444-1717
Microplex Systems Ltd.                  Fax: +1 604 444-4239
8525 Commerce Court                 mailto:fff@microplex.com
Burnaby, BC   V5A 4N3               http://www.microplex.com/

Re: Cache and MMU support for PowerPC

[Jesper Skov]

>>>>> "Fred" == Fred Fierling <fff@microplex.com> writes:
Fred> I've gone through the on-line information but am still wondering
Fred> if the PowerPC version of eCos includes support for the MPC860's
Fred> cache and MMU.  Can anyone save me from pouring through the code
Fred> to determine if it does?


>>>>> "Stuart" == Stuart Adams <sja@brightstareng.com> writes:
[snip]
Stuart> Also, the MMU needs to be enabled for the cache's to work and
Stuart> I don't see code for that. It's going to be board dependent
Stuart> anyway. Also, once you enable the cache there are additional
Stuart> issues with dealing with the CPM to do I/O.


Cache support will be available soon. However, as Stuart points out,
it requires a minimal MMU setup which is board specific; we use a
Cogent board for development, so that is what will be supported to
start with. Customizing the MMU setup for other boards should be
trivial though.

The MMU setup is truly minimal, basically marking the IO memory area
of the Cogent board as Cache Inhibited, so generic MMU support (memory
protection, paging, etc.) is *not* supported yet.

Thanks, 
Jesper

Re: Cache and MMU support for PowerPC

[Stuart Adams]

> Cache support will be available soon. However, as Stuart points out,
> it requires a minimal MMU setup which is board specific; we use a
> Cogent board for development, so that is what will be supported to
> start with. Customizing the MMU setup for other boards should be
> trivial though.

  The only thing that would need to go in the board specific
  HAL would be a data structure describing the static mapping
  of Virtual to Physical Addresses and the Attributes for each
  map. The actual MMU and cache setup code can be independent.
  (Motorola's example MMU/Cache code on their web site does it this 
   way.)

> The MMU setup is truly minimal, basically marking the IO memory area
> of the Cogent board as Cache Inhibited, so generic MMU support (memory
> protection, paging, etc.) is *not* supported yet.

  What about for memory that is used as buffers by the CPM. Since the
  CPM transfers data to/from I/O devices to memory but bypasses the
cache
  you have to make sure that you don't wind up with stale data in your
  cache. 

  I don't know if its the best approach but we got around this by
creating
  two Virtual->Physical mappings for main DRAM memory - one cache
enabled,
  the other cache disabled. When ever we read/write CPM I/O buffers we
  use the cache inhibited virtual addresses. The nice thing about this
is
  that you can use malloc/free to dynamically allocate buffers for use
by
  the CPM.

-- Stuart

Re: Cache and MMU support for PowerPC

[Fred Fierling]

Jesper Skov wrote:

> The MMU setup is truly minimal, basically marking the IO memory area
> of the Cogent board as Cache Inhibited, so generic MMU support (memory
> protection, paging, etc.) is *not* supported yet.

Yes, MMU setup is trivial for small embedded systems.  I
would imagine that making eCos cache and MMU aware
isn't though.  I take it Cygnus is working on this? By "soon"
do you mean days, weeks, months? (We're drooling here!)

I'm expecting the big thrill of having cache and MMU support
will be switching off the guard bit for code space and getting
the CPU out of serial mode. Without speculative execution
the 860 dawdles.

--
Fred Fierling                           Tel: +1 604 444-1717
Microplex Systems Ltd.                  Fax: +1 604 444-4239
8525 Commerce Court                 mailto:fff@microplex.com
Burnaby, BC   V5A 4N3               http://www.microplex.com/