[ECOS] problem enabling the caches on powerpc

[ECOS] problem enabling the caches on powerpc

[saurabh prakash]

hi,
i am working on  mbx type board, with mpc860P, i had successfully worked on
similar board  in the past. but i am having problems enabling the
caches on the current
board. As soon as the macro HAL_ICACHE_ENABLE() executes, the cpu
gives an exception(SEI). To be precise the second "isync" gives an
exception. I have modified the
HAL_ICACHE_SIZE, HAL_ICACHE_LINE_SIZE, HAL_ICACHE_WAYS.... etc according to
the variant i am using but without any results. Can anybody suggest
any solution.


#define HAL_ICACHE_ENABLE()
    asm volatile ("isync;"
                  "mtspr %0, %1;"
                  "isync"   <----- Executing this gives an exception
                  : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))

thanks in advance,
saurabh prakash
Team Leader, C-DOT

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Re: [ECOS] problem enabling the caches on powerpc

[Gary Thomas]

saurabh prakash wrote:
> hi,
> i am working on  mbx type board, with mpc860P, i had successfully worked on
> similar board  in the past. but i am having problems enabling the
> caches on the current
> board. As soon as the macro HAL_ICACHE_ENABLE() executes, the cpu
> gives an exception(SEI). To be precise the second "isync" gives an
> exception. I have modified the
> HAL_ICACHE_SIZE, HAL_ICACHE_LINE_SIZE, HAL_ICACHE_WAYS.... etc according to
> the variant i am using but without any results. Can anybody suggest
> any solution.
> 
> 
> #define HAL_ICACHE_ENABLE()
>    asm volatile ("isync;"
>                  "mtspr %0, %1;"
>                  "isync"   <----- Executing this gives an exception
>                  : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))

The most likely cause is your hardware timings, in particular DRAM
setups.  When you enable the cache(s), the CPU will start using burst
access to memory.  If you've not set this up properly, exceptions will
occur.

Check your UPM tables.

-- 
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------

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Re: [ECOS] problem enabling the caches on powerpc

[saurabh prakash]

How do i test that burst acces to dram is working properly?
I have enabled the burst for the device by OR/BR registers.
The board is working with MMU disabled.

thnx in advance,
saurabh

On 6/29/06, Gary Thomas <gary@mlbassoc.com> wrote:
> saurabh prakash wrote:
> > hi,
> > i am working on  mbx type board, with mpc860P, i had successfully worked on
> > similar board  in the past. but i am having problems enabling the
> > caches on the current
> > board. As soon as the macro HAL_ICACHE_ENABLE() executes, the cpu
> > gives an exception(SEI). To be precise the second "isync" gives an
> > exception. I have modified the
> > HAL_ICACHE_SIZE, HAL_ICACHE_LINE_SIZE, HAL_ICACHE_WAYS.... etc according to
> > the variant i am using but without any results. Can anybody suggest
> > any solution.
> >
> >
> > #define HAL_ICACHE_ENABLE()
> >    asm volatile ("isync;"
> >                  "mtspr %0, %1;"
> >                  "isync"   <----- Executing this gives an exception
> >                  : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
>
> The most likely cause is your hardware timings, in particular DRAM
> setups.  When you enable the cache(s), the CPU will start using burst
> access to memory.  If you've not set this up properly, exceptions will
> occur.
>
> Check your UPM tables.
>
> --
> ------------------------------------------------------------
> Gary Thomas                 |  Consulting for the
> MLB Associates              |    Embedded world
> ------------------------------------------------------------
>

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Re: [ECOS] problem enabling the caches on powerpc

[Gary Thomas]

Please keep your replies on the mailing list so that all may benefit.
Private support is available only with a support contract.

saurabh prakash wrote:
> How do i test that burst acces to dram is working properly?
> I have enabled the burst for the device by OR/BR registers.

You'll need to check your settings carefully and may need to enlist the
aid of a hardware expert with appropriate test equipment.

Verify what you have vs other known working designs - there are many
in the eCos source tree.

> The board is working with MMU disabled.

There can be no cache/bursting with the MMU disabled, so this is expected.

> 
> thnx in advance,
> saurabh
> 
> On 6/29/06, Gary Thomas <gary@mlbassoc.com> wrote:
>> saurabh prakash wrote:
>> > hi,
>> > i am working on  mbx type board, with mpc860P, i had successfully 
>> worked on
>> > similar board  in the past. but i am having problems enabling the
>> > caches on the current
>> > board. As soon as the macro HAL_ICACHE_ENABLE() executes, the cpu
>> > gives an exception(SEI). To be precise the second "isync" gives an
>> > exception. I have modified the
>> > HAL_ICACHE_SIZE, HAL_ICACHE_LINE_SIZE, HAL_ICACHE_WAYS.... etc 
>> according to
>> > the variant i am using but without any results. Can anybody suggest
>> > any solution.
>> >
>> >
>> > #define HAL_ICACHE_ENABLE()
>> >    asm volatile ("isync;"
>> >                  "mtspr %0, %1;"
>> >                  "isync"   <----- Executing this gives an exception
>> >                  : : "I" (CYGARC_REG_IC_CST), "r" 
>> (CYGARC_REG_IC_CMD_CE))
>>
>> The most likely cause is your hardware timings, in particular DRAM
>> setups.  When you enable the cache(s), the CPU will start using burst
>> access to memory.  If you've not set this up properly, exceptions will
>> occur.
>>
>> Check your UPM tables.
>>

-- 
------------------------------------------------------------
Gary Thomas                 |  Consulting for the
MLB Associates              |    Embedded world
------------------------------------------------------------

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Before posting, please read the FAQ: http://ecos.sourceware.org/fom/ecos
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