Re: [ECOS] Hard-Realtime behaviour

[R Vamshi Krishna <vamshi@cse.iitb.ac.in>]

Continuing on the discussion, doesn't pipelining on modern processors add 
to our woes. Because then we cannot really determine if a particular 
instruction is going to 'x' cycles or 'y' cycles.


eCos does support disabling instruction and data caches, but is there any 
way that I can disable pipelines in a microprocessor. For example i386ex.


@Andrew : As we have seen most of what is necessary for hard realtime 
behaviour of eCos already is implemented. Can you help me in figuring out 
what is it that is missing that makes eCos soft real-time.


On Tue, 30 May 2006, Andrew Lunn wrote:

> On Tue, May 30, 2006 at 10:09:21AM +0200, Fabian Scheler wrote:
>>> Disable the caches. How long something takes to execute will depend on
>>> what is in the cache. If the code to be executed is still in the cache
>>> from the last time it was executied, it will execute a lot quicker
>>> than if it has to be fetches from RAM/ROM. The same applies to the
>>> data to be processed. So to be deterministic, you need to disable
>>> caches.
>>
>> In order to guarantee deadlines, the worst case has to be
>> deterministic, not the average case! In event-driven systems
>> everything should be fine as long as your worst case response time is
>> beneath your deadline, things get problematic when you use
>> time-discrete algorithms, of course, but in this case you are better
>> of using a time-driven approach, anyway.
>
> So you at least need to disable caches when you determine what the
> worst case is, assuming the cache is actually helping you.
>
>      Andrew
>
>
>

-- 
Regards,
Vamshi

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IIT Bombay
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