[ECOS] [ [ECOS] eb40a Interrupt, TC]

[ECOS] [ [ECOS] eb40a Interrupt, TC]

[Carlos Perilla]

Nick Garnett wrote:

>
> You should not be calling cyg_interrupt_enable(). This is done
> implicitly when the scheduler is started. Calling it before then can
> allow interrupts to be delivered to code that is not yet ready.
>
> The code you have posted seems fine as far as it goes. Check that you
> have used the right vector number.
>
> Your code does not show where you are setting up the timer  device. I
> suspect that this is where the problems are to be found. Have you, for
> example, set the correct interrupt enable bit for the timer mode you
> are using.
>
>
>
>  
>
Well, I got what the problem was, a missplaced bit, now I have the 
problem that the  interrupt is taking over the system.
I disabled the interrupt and created a thread that peeks on RA, and RB, 
and everything it's working.
The signal I'm measuring is 1Khz and I'm placing a Interrupt on the  
rising edge, it's too fast?
I don't think so, but I think it's more about my slow code, any ideas?


Here's the code Interrupt
cyg_uint32 interrupt_TC1_isr(
             cyg_vector_t vector,
             cyg_addrword_t data) //Based  on eCos book, pag 48
{
cyg_interrupt_mask(vector);
cyg_interrupt_acknowledge(vector);
return(CYG_ISR_HANDLED | CYG_ISR_CALL_DSR);

}
void interrupt_TC1_dsr(
            cyg_vector_t vector,
            cyg_ucount32 count,
            cyg_addrword_t data)
{
HAL_IO_REGISTER REGISTER;
cyg_semaphore_post(&TC1_data_ready);
REGISTER=TC_BASE+TC_CHANNEL1+TC_RA;
HAL_READ_UINT16(REGISTER,TC1_PERIOD);
REGISTER=TC_BASE+TC_CHANNEL1+TC_RB;
HAL_READ_UINT16(REGISTER,TC1_HIGH);
cyg_interrupt_unmask(vector);
}

And I have created in the CYG_USER_START

cyg_interrupt_enable();
cyg_interrupt_create(
             intTC1_vector,
             intTC1_priority,
             0,
             &interrupt_TC1_isr,
             &interrupt_TC1_dsr,
             &intTC1_handle,
             &intTC1);
cyg_interrupt_attach(intTC1_handle);
cyg_interrupt_unmask(intTC1_vector);

cyg_semaphore_init(&TC1_data_ready,TC1_data_ready_counter);
cyg_semaphore_init(&TC1_trans,TC1_trans_counter);
cyg_semaphore_init(&TC1_end_trans,TC1_ent_trans_counter);

And here's the configuration Code

 TC_REGISTER=0;
 TC_REGISTER=TC_REGISTER | (TC_CMR_CLSKS_MCK2<<TC_CMR_CLKS);
 TC_REGISTER=TC_REGISTER | (TC_CMR_CLKI_FALLING<<TC_CMR_CLKI);
 TC_REGISTER=TC_REGISTER | (TC_CMR_BURST_MODE<<TC_CMR_BURST);
 TC_REGISTER=TC_REGISTER | (TC_CMR_LDBSTOP_NONE<<TC_CMR_LDBSTOP);
 TC_REGISTER=TC_REGISTER | (TC_CMR_LDBDIS_NONE<<TC_CMR_LDBDIS);
 TC_REGISTER=TC_REGISTER | (TC_CMR_ETREDG_RISING_EDGE<<TC_CMR_ETRGEDG);
 TC_REGISTER=TC_REGISTER | (TC_CMR_ABETRG_TIOA<<TC_CMR_ABETRG);
 TC_REGISTER=TC_REGISTER | (TC_CMR_CPCTRG_NONE<<TC_CMR_CPCTRG);
 TC_REGISTER=TC_REGISTER | (TC_CMR_WAVE_CAPTURE<<TC_CMR_WAVE);
 TC_REGISTER=TC_REGISTER | (TC_CMR_LDRA_RISING_EDGE<<TC_CMR_LDRA);
 TC_REGISTER=TC_REGISTER | (TC_CMR_LDRB_FALLING_EDGE<<TC_CMR_LDRB);

REGISTER=TC_BASE+TC_CMR+TC_CHANNEL1;
HAL_WRITE_UINT32(REGISTER,TC_REGISTER);

 TC_REGISTER=0;
 TC_REGISTER=TC_REGISTER | (TC_IER_ENABLE<<TC_IER_LDRAS);

 REGISTER=TC_BASE+TC_IER+TC_CHANNEL1;
 HAL_WRITE_UINT32(REGISTER,TC_REGISTER);
 REGISTER=TC_BASE+TC_IDR+TC_CHANNEL1;
 HAL_WRITE_UINT32(REGISTER,~TC_REGISTER);

Te purpose of this conf is to do this
PWM
~1Khz
              ________                _________
             |                |              |                  |
       ___|                |_______|                  |_____
          RA              RB        RA
          IRQ                          IRQ
       CV=0                          CV=0



Carlos Perilla


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Re: [ECOS] [ [ECOS] eb40a Interrupt, TC]

[Nick Garnett]

Carlos Perilla <transfers@phaber.com> writes:

> Nick Garnett wrote:
> 
> >
> > You should not be calling cyg_interrupt_enable(). This is done
> > implicitly when the scheduler is started. Calling it before then can
> > allow interrupts to be delivered to code that is not yet ready.
> >
> > The code you have posted seems fine as far as it goes. Check that you
> > have used the right vector number.
> >
> > Your code does not show where you are setting up the timer  device. I
> > suspect that this is where the problems are to be found. Have you, for
> > example, set the correct interrupt enable bit for the timer mode you
> > are using.
> >
> >
> >
> >
> Well, I got what the problem was, a missplaced bit, now I have the
> problem that the  interrupt is taking over the system.
> I disabled the interrupt and created a thread that peeks on RA, and
> RB, and everything it's working.
> The signal I'm measuring is 1Khz and I'm placing a Interrupt on the
> rising edge, it's too fast?
> I don't think so, but I think it's more about my slow code, any ideas?
> 

1KHz should be perfectly acceptable -- it's the same sort of interrupt
rate as running a serial line at 9600 baud.

The most likely cause of the interrupt swamping the system is that you
are not cancelling the cause properly. Check whether there are other
things that you need to do other than read RA and RB.

Also, given that you are not calling out into other code, you probably
don't need to defer the device access to the DSR, you can do all that
in the ISR, eliminating the masking/unmasking of the interrupt.


-- 
Nick Garnett                    eCos Kernel Architect
http://www.ecoscentric.com      The eCos and RedBoot experts


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