Re: at91 watchdog on eb42

[davarn@free.fr]

[-- Attachment #1: Type: text/plain, Size: 1024 bytes --]

Here is the patch from current cvs version.
A precision: ChangeLogvar is ChangeLog from hal/arm/at91/var/current
If the patch need an assignement, let me know, i will do it quickly.

David ARNAUD
davarn@free.fr

Selon Nick Garnett <nickg@ecoscentric.com>:

> davarn@free.fr writes:
>
> > I made some ehancement to at91 watchdog code to support eb42 board
> > (AT91M42800A).
> > The patch attached is done from ecos2.0 version.
> > var_io.h is not a patch as he does not exist in ecos2.0.
> > If someone is interested , I can redo the patch from the latest cvs
> version.
>
> We would very much prefer a diff against the current repository. In
> particular some of your changes duplicate differences that are already
> there since a lot of AT91 work was done after the V2.0 release. If
> this is done then it may reduce the size of the patch to where we can
> accept it without an assignment.
>
> --
> Nick Garnett                    eCos Kernel Architect
> http://www.ecoscentric.com/     The eCos and RedBoot experts
>
>



[-- Attachment #2: ChangeLog.patch --]
[-- Type: application/octet-stream, Size: 392 bytes --]

--- ChangeLog	2004-07-29 22:41:52.000000000 +0200
+++ /opt/ecos/ecos/packages/devs/watchdog/arm/at91/current/ChangeLog	2004-07-27 23:30:26.000000000 +0200
@@ -1,3 +1,8 @@
+2004-07-27  David Arnaud  <davarn@free.fr>
+
+	* src/watchdog_at91.cxx: 
+	* cdl/watchdog_at91.cdl: Modified driver add EB42 support.
+	
 2003-05-12  Nick Garnett  <nickg@balti.calivar.com>
 
 	* src/watchdog_at91.cxx: 

[-- Attachment #3: ChangeLogvar.patch --]
[-- Type: application/octet-stream, Size: 1657 bytes --]

--- ChangeLogvar	2004-07-29 22:41:52.000000000 +0200
+++ /opt/ecos/ecos/packages/hal/arm/at91/var/current/ChangeLog	2003-11-10 17:32:40.000000000 +0100
@@ -1,43 +1,3 @@
-2004-05-24  Gratian Crisan <nelu@iv.ro>
-
-	* include/var_io.h: Added waveform mode definitions for 
-	timer/counter.
-
-2004-02-19  Daniel Néri  <daniel.neri@sigicom.se>
- 
-        * cdl/hal_arm_at91.cdl (CYGBLD_GLOBAL_CFLAGS): Honour CYGHWR_THUMB
-        and CYGBLD_ARM_ENABLE_THUMB_INTERWORK.
-	* cdl/hal_arm_at91.cdl (CYGBLD_GLOBAL_LDFLAGS): Ditto.
- 
-2004-02-18  Daniel Néri  <daniel.neri@sigicom.se>
-
-	* cdl/hal_arm_at91.cdl: Define CYGNUM_HAL_ARM_AT91_CLOCK_SPEED with
-	a default_value so it can be overridden in the platform HAL.
-	* src/hal_diag.c (cyg_hal_plf_serial_control): Properly terminate
-	variable argument processing.
-	* include/hal_diag.h: prototype for hal_at91_set_leds() to avoid
-	compiler warning.
-	
-2004-02-12  Jani Monoses <jani@iv.ro>
-
-	* cdl/hal_arm_at91.cdl: Put configuration options common to all
-	variants here. Replace
-	CYGNUM_HAL_VIRTUAL_VECTOR_CHANNELS_DEFAULT_BAUD with the two
-	separate options for console and debug channels as used by most
-	HALs.
-	* src/hal_diag.c: Implement
-	CYGINT_HAL_VIRTUAL_VECTOR_COMM_BAUD_SUPPORT so baudrate is
-	changeable from RedBoot.
-	
-2003-12-05  Andrew Lunn  <andrew.lunn@ascom.ch>
-
-	* include/hal_diag.h: hal_delay_us() is a C function.
-
-2003-12-02  Thomas Koeller  <thomas.koeller@baslerweb.com>
-
-	* include/var_io.h: Improved accuracy for baud rate divider
-	computation.
-
 2003-10-23  Thomas Koeller  <thomas.koeller@baslerweb.com>
 
 	* src/at91_misc.c: Fixed recognition of spurious

[-- Attachment #4: var_io.h.patch --]
[-- Type: application/octet-stream, Size: 4863 bytes --]

--- var_io.h	2004-07-29 22:41:52.000000000 +0200
+++ /opt/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h	2004-07-24 00:21:46.000000000 +0200
@@ -135,7 +135,7 @@
 #define AT91_US_TPR 0x38  // Transmit pointer register
 #define AT91_US_TCR 0x3c  // Transmit counter register
 
-#define AT91_US_BAUD(baud) ((CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(8*(baud))+1)/2)
+#define AT91_US_BAUD(baud) (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/(16*(baud)))
 
 //=============================================================================
 // PIO
@@ -295,8 +295,8 @@
 #define AT91_TC_CCR_CLKEN  0x01
 #define AT91_TC_CCR_CLKDIS 0x02
 #define AT91_TC_CCR_TRIG   0x04
-// Channel Mode Register
 #define AT91_TC_CMR		   0x04
+// Capture mode definitions
 #define AT91_TC_CMR_CLKS	   0
 #define AT91_TC_CMR_CLKS_MCK2      (0<<0)
 #define AT91_TC_CMR_CLKS_MCK8      (1<<0)
@@ -311,7 +311,6 @@
 #define AT91_TC_CMR_BURST_XC0      (1<<4)
 #define AT91_TC_CMR_BURST_XC1      (2<<4)
 #define AT91_TC_CMR_BURST_XC2      (3<<4)
-// Capture mode definitions
 #define AT91_TC_CMR_LDBSTOP        (1<<6)
 #define AT91_TC_CMR_LDBDIS         (1<<7)
 #define AT91_TC_CMR_TRIG_NONE      (0<<8)
@@ -329,53 +328,7 @@
 #define AT91_TC_CMR_LDRB_TIOA_NEG  (1<<16)
 #define AT91_TC_CMR_LDRB_TIOA_POS  (2<<16)
 #define AT91_TC_CMR_LDRB_TIOA_BOTH (3<<16)
-// Waveform mode definitions
-#define AT91_TC_CMR_CPCSTOP        (1<<6)
-#define AT91_TC_CMR_CPCDIS	   (1<<7)
-#define AT91_TC_CMR_EEVTEDG_NONE   (0<<8)
-#define AT91_TC_CMR_EEVTEDG_NEG    (1<<8)
-#define AT91_TC_CMR_EEVTEDG_POS    (2<<8)
-#define AT91_TC_CMR_EEVTEDG_BOTH   (3<<8)
-#define AT91_TC_CMR_EEVT_TIOB	   (0<<10)
-#define AT91_TC_CMR_EEVT_XC0       (1<<10)
-#define AT91_TC_CMR_EEVT_XC1       (2<<10)
-#define AT91_TC_CMR_EEVT_XC2       (3<<10)
-#define AT91_TC_CMR_ENETRG	   (1<<12)
-#define AT91_TC_CMR_CPCTRG	   (1<<14)
-#define AT91_TC_CMR_WAVE	   (1<<15)
-#define AT91_TC_CMR_ACPA_NONE	   (0<<16)
-#define AT91_TC_CMR_ACPA_SET	   (1<<16)
-#define AT91_TC_CMR_ACPA_CLEAR	   (2<<16)
-#define AT91_TC_CMR_ACPA_TOGGLE	   (3<<16)
-#define AT91_TC_CMR_ACPC_NONE	   (0<<18)
-#define AT91_TC_CMR_ACPC_SET	   (1<<18)
-#define AT91_TC_CMR_ACPC_CLEAR	   (2<<18)
-#define AT91_TC_CMR_ACPC_TOGGLE	   (3<<18)
-#define AT91_TC_CMR_AEEVT_NONE	   (0<<20)
-#define AT91_TC_CMR_AEEVT_SET	   (1<<20)
-#define AT91_TC_CMR_AEEVT_CLEAR	   (2<<20)
-#define AT91_TC_CMR_AEEVT_TOGGLE   (3<<20)
-#define AT91_TC_CMR_ASWTRG_NONE	   (0<<22)
-#define AT91_TC_CMR_ASWTRG_SET	   (1<<22)
-#define AT91_TC_CMR_ASWTRG_CLEAR   (2<<22)
-#define AT91_TC_CMR_ASWTRG_TOGGLE  (3<<22)
-#define AT91_TC_CMR_BCPB_NONE	   (0<<24)
-#define AT91_TC_CMR_BCPB_SET	   (1<<24)
-#define AT91_TC_CMR_BCPB_CLEAR	   (2<<24)
-#define AT91_TC_CMR_BCPB_TOGGLE	   (3<<24)
-#define AT91_TC_CMR_BCPC_NONE	   (0<<26)
-#define AT91_TC_CMR_BCPC_SET	   (1<<26)
-#define AT91_TC_CMR_BCPC_CLEAR	   (2<<26)
-#define AT91_TC_CMR_BCPC_TOGGLE	   (3<<26)
-#define AT91_TC_CMR_BEEVT_NONE	   (0<<28)
-#define AT91_TC_CMR_BEEVT_SET	   (1<<28)
-#define AT91_TC_CMR_BEEVT_CLEAR	   (2<<28)
-#define AT91_TC_CMR_BEEVT_TOGGLE   (3<<28)
-#define AT91_TC_CMR_BSWTRG_NONE	   (0<<30)
-#define AT91_TC_CMR_BSWTRG_SET	   (1<<30)
-#define AT91_TC_CMR_BSWTRG_CLEAR   (2<<30)
-#define AT91_TC_CMR_BSWTRG_TOGGLE  (3<<30)
-
+// Waveform mode definitions [missing]
 #define AT91_TC_CV      0x10
 #define AT91_TC_RA      0x14
 #define AT91_TC_RB      0x18
@@ -620,6 +573,43 @@
 //=============================================================================
 // Watchdog
 
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+#ifndef AT91_ST
+#define AT91_ST             0xFFFF8000
+#endif
+
+#define AT91_ST_CR           0x00000000
+#define AT91_ST_CR_WDRST     0x00000001
+
+#define AT91_ST_PIMR         0x00000004
+#define AT91_ST_PIMR_PIV_MSK 0x0000ffff
+
+#define AT91_ST_WDMR         0x00000008
+#define AT91_ST_WDMR_EXTEN   0x00020000
+#define AT91_ST_WDMR_RSTEN   0x00010000
+#define AT91_ST_WDMR_WDV_MSK 0x0000ffff
+
+#define AT91_ST_RTMR         0x0000000C
+#define AT91_ST_RTMR_RTP_MSK 0x0000ffff
+
+#define AT91_ST_SR           0x00000010
+#define AT91_ST_IER          0x00000014
+#define AT91_ST_IDR          0x00000018
+#define AT91_ST_IMR          0x0000001C
+
+#define AT91_ST_PITS         0x00000001
+#define AT91_ST_WDOVF        0x00000002
+#define AT91_ST_RTTINC       0x00000004
+#define AT91_ST_ALMS         0x00000008
+
+#define AT91_ST_RTAR          0x00000020
+#define AT91_ST_RTAR_ALMV_MSK 0x00ffffff
+
+#define AT91_ST_CRTR          0x00000024
+#define AT91_ST_CRTR_ALMV_MSK 0x00ffffff
+
+#else
+
 #ifndef AT91_WD
 #define AT91_WD             0xFFFF8000
 #endif
@@ -638,7 +628,7 @@
 #define AT91_WD_CR_RSTKEY   0x0000C071
 #define AT91_WD_SR          0x0C
 #define AT91_WD_SR_WDOVF    0x00000001
-
+#endif
 
 //-----------------------------------------------------------------------------
 // end of var_io.h

[-- Attachment #5: watchdog_at91.cdl.patch --]
[-- Type: application/octet-stream, Size: 5892 bytes --]

--- watchdog_at91.cdl	2004-07-29 22:41:52.000000000 +0200
+++ /opt/ecos/ecos/packages/devs/watchdog/arm/at91/current/src/watchdog_at91.cdl	1970-01-01 01:00:00.000000000 +0100
@@ -1,138 +0,0 @@
-# ====================================================================
-#
-#      watchdog_at91.cdl
-#
-#      eCos watchdog for ARM AT91 driver configuration data
-#
-# ====================================================================
-#####ECOSGPLCOPYRIGHTBEGIN####
-## -------------------------------------------
-## This file is part of eCos, the Embedded Configurable Operating System.
-## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
-## Copyright (C) 2003 Nick Garnett <nickg@calivar.com>
-##
-## eCos is free software; you can redistribute it and/or modify it under
-## the terms of the GNU General Public License as published by the Free
-## Software Foundation; either version 2 or (at your option) any later version.
-##
-## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
-## WARRANTY; without even the implied warranty of MERCHANTABILITY or
-## FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
-## for more details.
-##
-## You should have received a copy of the GNU General Public License along
-## with eCos; if not, write to the Free Software Foundation, Inc.,
-## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
-##
-## As a special exception, if other files instantiate templates or use macros
-## or inline functions from this file, or you compile this file and link it
-## with other works to produce a work based on this file, this file does not
-## by itself cause the resulting work to be covered by the GNU General Public
-## License. However the source code for this file must still be made available
-## in accordance with section (3) of the GNU General Public License.
-##
-## This exception does not invalidate any other reasons why a work based on
-## this file might be covered by the GNU General Public License.
-##
-## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
-## at http://sources.redhat.com/ecos/ecos-license/
-## -------------------------------------------
-#####ECOSGPLCOPYRIGHTEND####
-# ====================================================================
-######DESCRIPTIONBEGIN####
-#
-# Author(s):      tkoeller
-# Contributors:   tkoeller, nickg
-# Date:           2000-05-05
-#
-#####DESCRIPTIONEND####
-#
-# ====================================================================
-
-cdl_package CYGPKG_DEVICES_WATCHDOG_ARM_AT91 {
-    parent        CYGPKG_IO_WATCHDOG
-    active_if     CYGPKG_IO_WATCHDOG
-    display       "ARM AT91 watchdog driver"
-    requires      CYGPKG_HAL_ARM_AT91
-    requires      CYGPKG_KERNEL
-    hardware
-    define_header devs_watchdog_arm_at91.h
-    compile       watchdog_at91.cxx
-    implements    CYGINT_WATCHDOG_HW_IMPLEMENTATIONS
-    active_if     CYGIMP_WATCHDOG_HARDWARE
-    description   "
-      This package uses the watchdog device integrated
-      in the AT91 to execute a predefined action if the
-      application fails to call the reset function for
-      longer than a given timeout interval. This package
-      currently only supports the AT91x408xx and AT91M55800A
-      devices found on the Atmel EB40, EB40A and EB55 evaluation
-      boards. The AT91M42800 found on the EB42 is not supported
-      since it uses a totally different watchdog device."
-
-    cdl_option CYGIMP_WATCHDOG_HARDWARE {
-        parent	      CYGPKG_IO_WATCHDOG_IMPLEMENTATION
-        display       "Hardware watchdog"
-        calculated    1
-        implements    CYGINT_WATCHDOG_IMPLEMENTATIONS
-    }
-    
-    cdl_option CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS {
-      	display       	"Desired timeout value"
-	flavor        	data
-	legal_values  	1 to 2047
-	default_value 	100
-	description "
-	    This parameter controls the watchdog timeout interval.
-	    Note that you may not get the exact value requested
-	    here, the timeout interval may have to be adjusted
-	    because of hardware limitations. The actual timeout
-	    used will be the smallest possible value that is not
-	    less than this parameter."
-    }
-    
-    cdl_option CYGSEM_DEVS_WATCHDOG_ARM_AT91_RESET {
-      	display       "Generate reset on watchdog expiration"
-	flavor	      bool
-	default_value 1
-      	implements    CYGINT_WATCHDOG_RESETS_ON_TIMEOUT
-	description   "
-	  Enabling this option changes the watchdog operation mode
-	  to generate a system reset upon expiration instead of
-	  invoking an application-defined action."
-    }
-
-    cdl_component CYGPKG_DEVICES_WATCHDOG_ARM_AT91_OPTIONS {
-        display       "AT91 watchdog build options"
-        flavor	      none
-        description   "
-	    Package specific build options including control over
-	    compiler flags used only in building this package,
-	    and details of which tests are built."
-
-        cdl_option CYGPKG_DEVICES_WATCHDOG_ARM_AT91_CFLAGS_ADD {
-            display   	  "Additional compiler flags"
-            flavor    	  data
-            no_define
-            default_value { "" }
-            description   "
-                This option modifies the set of compiler flags for
-                building the watchdog device. These flags are used in addition
-                to the set of global flags."
-        }
-
-        cdl_option CYGPKG_DEVICES_WATCHDOG_ARM_AT91_CFLAGS_REMOVE {
-            display   	  "Suppressed compiler flags"
-            flavor    	  data
-            no_define
-            default_value { "" }
-            description   "
-                This option modifies the set of compiler flags for
-                building the watchdog device. These flags are removed from
-                the set of global flags if present."
-        }
-
-    }
-}
-
-# EOF watchdog_at91.cdl

[-- Attachment #6: watchdog_at91.cxx.patch --]
[-- Type: application/octet-stream, Size: 6393 bytes --]

--- watchdog_at91.cxx	2004-07-29 22:41:52.000000000 +0200
+++ /opt/ecos/ecos/packages/devs/watchdog/arm/at91/current/src/watchdog_at91.cxx	2004-07-27 23:27:23.000000000 +0200
@@ -42,8 +42,8 @@
 //#####DESCRIPTIONBEGIN####
 //
 // Author(s):    tkoeller
-// Contributors: tkoeller, nickg
-// Date:         2002-05-05
+// Contributors: tkoeller, nickg, darnaud
+// Date:         2004-07-23
 // Purpose:      Watchdog class implementation
 // Description:  Contains an implementation of the Watchdog class for use
 //               with the ATMEL AT91 watchdog timer.
@@ -73,13 +73,14 @@
 
 //==========================================================================
 
-#define MCLK_FREQUENCY_KHZ  (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
-#define MAX_TICKS     	    0x0000ffff
-#define BASE_TICKS    	    (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
 
 #if defined(CYGHWR_HAL_ARM_AT91_R40008) || \
     defined(CYGHWR_HAL_ARM_AT91_R40807)
 
+#define MCLK_FREQUENCY_KHZ  (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
+#define MAX_TICKS     	    0x0000ffff
+#define BASE_TICKS    	    (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
+
 #if   BASE_TICKS / 8 <= MAX_TICKS
 #define DIVIDER 0
 #define DIV_FACTOR 8
@@ -96,82 +97,78 @@
 #error Desired resolution beyond hardware capabilities
 #endif
 
-#elif defined(CYGHWR_HAL_ARM_AT91_M55800A)
+#define TICKS 	    ((BASE_TICKS / DIV_FACTOR) | 0xfff)
+#define RESOLUTION  ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
 
-#if   BASE_TICKS / 32 <= MAX_TICKS
-#define DIVIDER 0
-#define DIV_FACTOR 32
-#elif BASE_TICKS / 128 <= MAX_TICKS
-#define DIVIDER 1
-#define DIV_FACTOR 128
-#elif BASE_TICKS / 1024 <= MAX_TICKS
-#define DIVIDER 2
-#define DIV_FACTOR 1024
-#elif BASE_TICKS / 4096 <= MAX_TICKS
-#define DIVIDER 3
-#define DIV_FACTOR 4096
-#else
-#error Desired resolution beyond hardware capabilities
-#endif
+#elif defined(CYGHWR_HAL_ARM_AT91_M42800A)
 
+#define SCLK_FREQUENCY_HZ  32800     // Slow clock in hertz
+#define MAX_TICKS     	    0x0000ffff
+#define BASE_TICKS    	    (SCLK_FREQUENCY_HZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS/1000)
 
+#if BASE_TICKS/128  > MAX_TICKS
+#error Desired resolution beyond hardware capabilities
 #endif
 
-#define TICKS 	    ((BASE_TICKS / DIV_FACTOR) | 0xfff)
-#define RESOLUTION  ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
+#define TICKS ((BASE_TICKS / 128) & 0xffff)
+#define RESOLUTION  ((cyg_uint64) (TICKS * 128) * 1000000000 / SCLK_FREQUENCY_HZ)
+#endif
 
 //==========================================================================
-
+// Reset on watchdog expiration
 #if defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT)
 
 #define OMRVAL	(AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN)
-
-void
-Cyg_Watchdog::init_hw(void)
-{
-  CYG_REPORT_FUNCTION();
-  CYG_REPORT_FUNCARGVOID();
-  resolution = RESOLUTION;
-  CYG_REPORT_RETURN();
-}
+#define WDMRFLG (AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN)
+#define IERFLG  0
 
 #else /* defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) */
 
 //==========================================================================
+// Action on watchdog expiration
 
 #define OMRVAL	(AT91_WD_OMR_OKEY | AT91_WD_OMR_IRQEN | AT91_WD_OMR_WDEN)
+#define WDMRFLG 0
+#define IERFLG  (AT91_ST_WDOVF)
 #define INT_PRIO    7
 
 //==========================================================================
+// Private definitions
 
+static cyg_ISR    watchdog_isr;
 static Cyg_Watchdog *wd;
 
+
 //==========================================================================
 
-static cyg_uint32
-isr(cyg_vector vector, CYG_ADDRWORD data)
+static Cyg_Interrupt wdint
+(
+ CYGNUM_HAL_INTERRUPT_WATCHDOG,
+ INT_PRIO,
+ 0,
+ watchdog_isr,
+ NULL
+ );
+
+//==========================================================================
+
+cyg_uint32 watchdog_isr(cyg_vector vector, CYG_ADDRWORD data)
 {
   CYG_REPORT_FUNCTION();
   CYG_REPORT_FUNCARG2XV(vector, data);
 
   wd->trigger();
-  Cyg_Interrupt::acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
+  wdint.acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
   CYG_REPORT_RETVAL(Cyg_Interrupt::HANDLED);
   return Cyg_Interrupt::HANDLED;
 }
 
-//==========================================================================
-
-static Cyg_Interrupt wdint(
-    CYGNUM_HAL_INTERRUPT_WATCHDOG,
-    INT_PRIO,
-    0,
-    isr,
-    NULL
-  );
+#endif	/* defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) */
 
 //==========================================================================
-
+/*
+ * Init hardware watchdog timer.
+ */
 void
 Cyg_Watchdog::init_hw(void)
 {
@@ -180,15 +177,9 @@
 
   wd = this;
   resolution = RESOLUTION;
-  wdint.configure_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG, false, true);
-  wdint.attach();
-  wdint.acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
-  wdint.unmask_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
+
   CYG_REPORT_RETURN();
 }
-
-#endif	/* defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT) */
-
 //==========================================================================
 /*
  * Reset watchdog timer. This needs to be called regularly to prevent
@@ -200,9 +191,14 @@
 {
   CYG_REPORT_FUNCTION();
   CYG_REPORT_FUNCARGVOID();
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+  /* Re-arm watchdog timer */
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_CR, AT91_ST_CR_WDRST);
 
+#else
   /* Write magic code to reset the watchdog. */
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
+#endif
   CYG_REPORT_RETURN();
 }
 
@@ -218,6 +214,18 @@
   CYG_REPORT_FUNCTION();
   CYG_REPORT_FUNCARGVOID();
   
+#if !defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT)  
+  wdint.configure_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG, false, true);
+  wdint.attach();
+  wdint.acknowledge_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
+  wdint.unmask_interrupt(CYGNUM_HAL_INTERRUPT_WATCHDOG);
+#endif
+
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_WDMR, TICKS | WDMRFLG );
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_IER, IERFLG );
+  HAL_WRITE_UINT32(AT91_ST + AT91_ST_CR, AT91_ST_CR_WDRST  );
+#else
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY);
   HAL_WRITE_UINT32(
     AT91_WD + AT91_WD_CMR,
@@ -225,6 +233,7 @@
   );
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
   HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, OMRVAL);
+#endif
   CYG_REPORT_RETURN();
 }