* Trans.: Re: at91 watchdog on eb42
@ 2004-08-12 9:25 davarn
0 siblings, 0 replies; only message in thread
From: davarn @ 2004-08-12 9:25 UTC (permalink / raw)
To: ecos-patches, ecos-maintainers
[-- Attachment #1: Type: text/plain, Size: 1364 bytes --]
I redo var_io and watchdog patches concidering all your remarks.
var_io was big because i did not used the latest version to make my code.
Selon Nick Garnett <nickg@ecoscentric.com>:
> davarn@free.fr writes:
>
> > Hello,
> >
> > The change is really the minimum, even if it is quite important.
> > Tis is due to the fact that on eb42 board, if Interrupt is used in init_hw,
> the
> > object is not already intialized so the attach function assert.
> > Moving it in the start function make the thing work, and does not change
> the
> > behavior at all.
> > To be closer to the original code, it is necessary to investigate object
> > intialization on eb42 board.
>
> I was also concerned about changes to var_io.h. Your patch seems to be
> deleting large numbers of definitions. I'm also not sure what the
> change to AT91_US_BAUD() is going to do.
>
>
> The problem with the interrupt object can be fixed by adding
> CYGBLD_ATTRIB_INIT_PRI() to the interrupt object definition:
>
> static Cyg_Interrupt wdint(
> CYGNUM_HAL_INTERRUPT_WATCHDOG,
> INT_PRIO,
> 0,
> isr,
> NULL
> ) CYGBLD_ATTRIB_INIT_PRI( CYG_INIT_DRIVERS );
>
>
> This only seems to affect some targets, we haven't worked out why
> this is yet.
>
> --
> Nick Garnett eCos Kernel Architect
> http://www.ecoscentric.com/ The eCos and RedBoot experts
>
>
[-- Attachment #2: watchdog_at91.cxx.patch --]
[-- Type: application/octet-stream, Size: 4100 bytes --]
--- watchdog_at91.cxx 2004-08-05 11:33:26.000000000 +0200
+++ /opt/ecos/ecos/packages/devs/watchdog/arm/at91/current/src/watchdog_at91.cxx 2004-08-04 20:22:20.000000000 +0200
@@ -73,13 +73,15 @@
//==========================================================================
-#define MCLK_FREQUENCY_KHZ (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
-#define MAX_TICKS 0x0000ffff
-#define BASE_TICKS (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
+
#if defined(CYGHWR_HAL_ARM_AT91_R40008) || \
defined(CYGHWR_HAL_ARM_AT91_R40807)
+#define MCLK_FREQUENCY_KHZ (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
+#define MAX_TICKS 0x0000ffff
+#define BASE_TICKS (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
+
#if BASE_TICKS / 8 <= MAX_TICKS
#define DIVIDER 0
#define DIV_FACTOR 8
@@ -96,8 +98,15 @@
#error Desired resolution beyond hardware capabilities
#endif
+#define TICKS ((BASE_TICKS / DIV_FACTOR) | 0xfff)
+#define RESOLUTION ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
+
#elif defined(CYGHWR_HAL_ARM_AT91_M55800A)
+#define MCLK_FREQUENCY_KHZ (CYGNUM_HAL_ARM_AT91_CLOCK_SPEED/1000)
+#define MAX_TICKS 0x0000ffff
+#define BASE_TICKS (MCLK_FREQUENCY_KHZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS)
+
#if BASE_TICKS / 32 <= MAX_TICKS
#define DIVIDER 0
#define DIV_FACTOR 32
@@ -114,17 +123,32 @@
#error Desired resolution beyond hardware capabilities
#endif
+#define TICKS ((BASE_TICKS / DIV_FACTOR) | 0xfff)
+#define RESOLUTION ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
+#elif defined(CYGHWR_HAL_ARM_AT91_M42800A)
+
+#define SCLK_FREQUENCY_HZ 32800 // Slow clock in hertz
+#define MAX_TICKS 0x0000ffff
+#define BASE_TICKS (SCLK_FREQUENCY_HZ * CYGNUM_DEVS_WATCHDOG_ARM_AT91_DESIRED_TIMEOUT_MS/1000)
+
+#if BASE_TICKS/128 > MAX_TICKS
+#error Desired resolution beyond hardware capabilities
+#endif
+
+#define TICKS ((BASE_TICKS / 128) & 0xffff)
+#define RESOLUTION ((cyg_uint64) (TICKS * 128) * 1000000000 / SCLK_FREQUENCY_HZ)
#endif
-#define TICKS ((BASE_TICKS / DIV_FACTOR) | 0xfff)
-#define RESOLUTION ((cyg_uint64) (TICKS * DIV_FACTOR ) * 1000000 / MCLK_FREQUENCY_KHZ)
+
//==========================================================================
#if defined(CYGSEM_WATCHDOG_RESETS_ON_TIMEOUT)
#define OMRVAL (AT91_WD_OMR_OKEY | AT91_WD_OMR_RSTEN | AT91_WD_OMR_WDEN)
+#define WDMRFLG (AT91_ST_WDMR_RSTEN | AT91_ST_WDMR_EXTEN)
+#define IERFLG 0
void
Cyg_Watchdog::init_hw(void)
@@ -140,6 +164,8 @@
//==========================================================================
#define OMRVAL (AT91_WD_OMR_OKEY | AT91_WD_OMR_IRQEN | AT91_WD_OMR_WDEN)
+#define WDMRFLG 0
+#define IERFLG (AT91_ST_WDOVF)
#define INT_PRIO 7
//==========================================================================
@@ -168,7 +194,7 @@
0,
isr,
NULL
- );
+ ) CYGBLD_ATTRIB_INIT_PRI( CYG_INIT_DRIVERS );
//==========================================================================
@@ -200,9 +226,14 @@
{
CYG_REPORT_FUNCTION();
CYG_REPORT_FUNCARGVOID();
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+ /* Re-arm watchdog timer */
+ HAL_WRITE_UINT32(AT91_ST + AT91_ST_CR, AT91_ST_CR_WDRST);
+#else
/* Write magic code to reset the watchdog. */
HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
+#endif
CYG_REPORT_RETURN();
}
@@ -218,6 +249,11 @@
CYG_REPORT_FUNCTION();
CYG_REPORT_FUNCARGVOID();
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+ HAL_WRITE_UINT32(AT91_ST + AT91_ST_WDMR, TICKS | WDMRFLG );
+ HAL_WRITE_UINT32(AT91_ST + AT91_ST_IER, IERFLG );
+ HAL_WRITE_UINT32(AT91_ST + AT91_ST_CR, AT91_ST_CR_WDRST );
+#else
HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, AT91_WD_OMR_OKEY);
HAL_WRITE_UINT32(
AT91_WD + AT91_WD_CMR,
@@ -225,6 +261,7 @@
);
HAL_WRITE_UINT32(AT91_WD + AT91_WD_CR, AT91_WD_CR_RSTKEY);
HAL_WRITE_UINT32(AT91_WD + AT91_WD_OMR, OMRVAL);
+#endif
CYG_REPORT_RETURN();
}
[-- Attachment #3: var_io.h.patch --]
[-- Type: application/octet-stream, Size: 1606 bytes --]
--- var_io.h 2004-08-05 11:28:34.000000000 +0200
+++ /opt/ecos/ecos/packages/hal/arm/at91/var/current/include/var_io.h 2004-08-06 18:35:47.000000000 +0200
@@ -620,6 +620,44 @@
//=============================================================================
// Watchdog
+
+#if defined(CYGHWR_HAL_ARM_AT91_M42800A)
+#ifndef AT91_ST
+#define AT91_ST 0xFFFF8000
+#endif
+
+#define AT91_ST_CR 0x00000000
+#define AT91_ST_CR_WDRST 0x00000001
+
+#define AT91_ST_PIMR 0x00000004
+#define AT91_ST_PIMR_PIV_MSK 0x0000ffff
+
+#define AT91_ST_WDMR 0x00000008
+#define AT91_ST_WDMR_EXTEN 0x00020000
+#define AT91_ST_WDMR_RSTEN 0x00010000
+#define AT91_ST_WDMR_WDV_MSK 0x0000ffff
+
+#define AT91_ST_RTMR 0x0000000C
+#define AT91_ST_RTMR_RTP_MSK 0x0000ffff
+
+#define AT91_ST_SR 0x00000010
+#define AT91_ST_IER 0x00000014
+#define AT91_ST_IDR 0x00000018
+#define AT91_ST_IMR 0x0000001C
+
+#define AT91_ST_PITS 0x00000001
+#define AT91_ST_WDOVF 0x00000002
+#define AT91_ST_RTTINC 0x00000004
+#define AT91_ST_ALMS 0x00000008
+
+#define AT91_ST_RTAR 0x00000020
+#define AT91_ST_RTAR_ALMV_MSK 0x00ffffff
+
+#define AT91_ST_CRTR 0x00000024
+#define AT91_ST_CRTR_ALMV_MSK 0x00ffffff
+
+#else
+
#ifndef AT91_WD
#define AT91_WD 0xFFFF8000
#endif
@@ -638,6 +676,7 @@
#define AT91_WD_CR_RSTKEY 0x0000C071
#define AT91_WD_SR 0x0C
#define AT91_WD_SR_WDOVF 0x00000001
+#endif
//-----------------------------------------------------------------------------
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2004-08-12 9:25 Trans.: Re: at91 watchdog on eb42 davarn
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