* [Bug 1001124] Cortex M - stack corruption
[not found] <bug-1001124-104@http.bugs.ecos.sourceware.org/>
@ 2011-01-20 18:08 ` bugzilla-daemon
2011-01-20 18:09 ` bugzilla-daemon
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Christophe Coutand <ecos@hotmail.co.uk> changed:
What |Removed |Added
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CC| |ecos-patches@ecos.sourcewar
| |e.org
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[not found] <bug-1001124-104@http.bugs.ecos.sourceware.org/>
2011-01-20 18:08 ` [Bug 1001124] Cortex M - stack corruption bugzilla-daemon
@ 2011-01-20 18:09 ` bugzilla-daemon
2011-01-21 10:49 ` bugzilla-daemon
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--- Comment #1 from Christophe Coutand <ecos@hotmail.co.uk> 2011-01-20 18:09:15 GMT ---
Created an attachment (id=1091)
--> (http://bugs.ecos.sourceware.org/attachment.cgi?id=1091)
Fix stack corruption
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[not found] <bug-1001124-104@http.bugs.ecos.sourceware.org/>
2011-01-20 18:08 ` [Bug 1001124] Cortex M - stack corruption bugzilla-daemon
2011-01-20 18:09 ` bugzilla-daemon
@ 2011-01-21 10:49 ` bugzilla-daemon
2011-01-21 11:09 ` bugzilla-daemon
2011-01-23 8:59 ` bugzilla-daemon
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From: bugzilla-daemon @ 2011-01-21 10:49 UTC (permalink / raw)
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Nick Garnett <nickg@ecoscentric.com> changed:
What |Removed |Added
----------------------------------------------------------------------------
CC| |nickg@ecoscentric.com
--- Comment #2 from Nick Garnett <nickg@ecoscentric.com> 2011-01-21 10:48:48 GMT ---
Christophe,
This is not right. It would leave the interrupt stack pointing to halfway
through the stack area. Since the interrupt stack is usually placed in on-chip
SRAM, this wastes some precious memory.
I am also not sure how you get any interrupts before the first context switch
moves to a real thread stack. The context switch code changes stack before
setting BASEPRI, which is when the first interrupt may occur. You should not be
getting any interrupts or exceptions before this point, if you are then I
suspect you have accidentally enabled interrupts in some piece of
initialization code.
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[not found] <bug-1001124-104@http.bugs.ecos.sourceware.org/>
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From: bugzilla-daemon @ 2011-01-21 11:09 UTC (permalink / raw)
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--- Comment #3 from Christophe Coutand <ecos@hotmail.co.uk> 2011-01-21 11:08:43 GMT ---
Hi Nick,
I have misunderstood hal_switch_state_vsr and the interrupt masking principle.
I thought hal_switch_state_vsr was moving PSP not MSP...
My initial undertanding was that masking interrupts with the BASEPRI register
was not stopping the system interrupt like the RTC interrupt from SysTick to
happen. I have to find out why I get the RTC interrupt.
Thanks,
Christophe
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From: bugzilla-daemon @ 2011-01-23 8:59 UTC (permalink / raw)
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Christophe Coutand <ecos@hotmail.co.uk> changed:
What |Removed |Added
----------------------------------------------------------------------------
Status|UNCONFIRMED |RESOLVED
Resolution| |NOTABUG
--- Comment #4 from Christophe Coutand <ecos@hotmail.co.uk> 2011-01-23 08:58:43 GMT ---
Wrong setting of CYGNUM_HAL_CORTEXM_PRIORITY_MAX was causing interrupt to
happen..
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