[SCM] master: Fixing PPC32on64 bank registers.

[SCM] master: Fixing PPC32on64 bank registers.

[jflavio]

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      from  d493569a34db466c257c88071d35432e20859f66 (commit)

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- Log -----------------------------------------------------------------
commit adc15992c27aee3dc62efd09149a9c930f41a4a2
Author: Jose Flavio Aguilar Paulino <jflavio@br.ibm.com>
Date:   Thu Nov 22 09:47:40 2007 -0200

    Fixing PPC32on64 bank registers.

-----------------------------------------------------------------------

Summary of changes:
 frysk-core/frysk/proc/ChangeLog             |    4 +++
 frysk-core/frysk/proc/PPCBankRegisters.java |   37 +++++++++++---------------
 2 files changed, 20 insertions(+), 21 deletions(-)

First 500 lines of diff:
diff --git a/frysk-core/frysk/proc/ChangeLog b/frysk-core/frysk/proc/ChangeLog
index ba69afb..f467745 100644
--- a/frysk-core/frysk/proc/ChangeLog
+++ b/frysk-core/frysk/proc/ChangeLog
@@ -1,3 +1,7 @@
+2007-11-22  Jose Flavio Aguilar Paulino <jflavio@br.ibm.com>
+	
+	* PPCBankRegisters.java: Correcting the bank registers PPC32on64.
+
 2007-11-21  Andrew Cagney  <cagney@redhat.com>
 
 	* IsaX8664.java: Use X8664Registers.DR6 instead of "d6".
diff --git a/frysk-core/frysk/proc/PPCBankRegisters.java b/frysk-core/frysk/proc/PPCBankRegisters.java
index 1eecc0f..d6a9565 100644
--- a/frysk-core/frysk/proc/PPCBankRegisters.java
+++ b/frysk-core/frysk/proc/PPCBankRegisters.java
@@ -81,7 +81,7 @@ public class PPCBankRegisters {
 	.add(new BankRegister(0, 124, 4, PPC32Registers.GPR31))
 	.add(new BankRegister(0, 128, 4, "result"))
 	.add(new BankRegister(0, 132, 4, "msr"))
-	.add(new BankRegister(0, 136, 4, "orig_r3"))
+	.add(new BankRegister(0, 136, 4, PPC32Registers.ARG)) //orig_r3
 	.add(new BankRegister(0, 140, 4, PPC32Registers.CTR))
 	.add(new BankRegister(0, 144, 4, PPC32Registers.LR))
 	.add(new BankRegister(0, 148, 4, PPC32Registers.XER))
@@ -160,11 +160,11 @@ public class PPCBankRegisters {
 	.add(new BankRegister(0, 248, 8, PPC64Registers.GPR31))
 	.add(new BankRegister(0, 256, 8, PPC64Registers.NIP))
 	.add(new BankRegister(0, 264, 8, "msr"))
-	.add(new BankRegister(0, 272, 8, "orig_r3"))
-	.add(new BankRegister(0, 280, 8, "ctr"))
-	.add(new BankRegister(0, 288, 8, "lnk"))
-	.add(new BankRegister(0, 296, 8, "xer"))
-	.add(new BankRegister(0, 304, 8, "ccr"))
+	.add(new BankRegister(0, 272, 8, PPC64Registers.ARG)) //old orig_r3
+	.add(new BankRegister(0, 280, 8, PPC64Registers.CTR))
+	.add(new BankRegister(0, 288, 8, PPC64Registers.LR))
+	.add(new BankRegister(0, 296, 8, PPC64Registers.XER))
+	.add(new BankRegister(0, 304, 8, PPC64Registers.CCR))
 	.add(new BankRegister(0, 312, 8, "softe"))
 	.add(new BankRegister(0, 320, 8, "trap"))
 	.add(new BankRegister(0, 328, 8, "dar"))
@@ -239,21 +239,16 @@ public class PPCBankRegisters {
 	.add("gpr29")
 	.add("gpr30")
 	.add("gpr31")
-    // XXX: No such register on PPC32
-    //.add("nip")
-	.add("msr")
-	.add("orig_r3")
-    // XXX: No such register on PPC32
-    //.add("ctr")
-    //.add("lnk")
-    //.add("xer")
-    //.add("ccr")
-    // No such register on ppc64.
-    // .add("mq"))
-	.add("trap")
-	.add("dar")
-	.add("dsisr")
-	.add("result")
+        .add("result")
+        .add("msr")
+        .add("arg")
+        .add("ctr")
+        .add("lr")
+        .add("xer")
+        .add("ccr")
+        .add("trap")
+        .add("dar")
+        .add("dsisr")
 	.add("fpr0")
 	.add("fpr1")
 	.add("fpr2")


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