[Bug target/100056] [9/10/11 Regression] orr + lsl vs. [us]bfiz

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https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100056

--- Comment #9 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:39d23b7960e4efb11bbe1eff056ae9da0884c539

commit r11-8188-g39d23b7960e4efb11bbe1eff056ae9da0884c539
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Thu Apr 15 10:45:09 2021 +0200

    aarch64: Fix several *<LOGICAL:optab>_ashl<mode>3 related regressions
[PR100056]

    Before combiner added 2 to 2 combinations, the following testcase functions
    have been all compiled into 2 instructions, zero/sign extensions or and
    followed by orr with lsl, e.g. for the first function
    Trying 7 -> 8:
        7: r96:SI=r94:SI<<0xb
        8: r95:SI=r96:SI|r94:SI
          REG_DEAD r96:SI
          REG_DEAD r94:SI
    Successfully matched this instruction:
    (set (reg:SI 95)
        (ior:SI (ashift:SI (reg/v:SI 94 [ i ])
                (const_int 11 [0xb]))
            (reg/v:SI 94 [ i ])))
    is the important successful try_combine and so we end up with
            and     w0, w0, 255
            orr     w0, w0, w0, lsl 11
    in the body.
    With 2 to 2 combination, before that can trigger, another successful
    combination:
    Trying 2 -> 7:
        2: r94:SI=zero_extend(x0:QI)
          REG_DEAD x0:QI
        7: r96:SI=r94:SI<<0xb
    is replaced with:
    (set (reg/v:SI 94 [ i ])
        (zero_extend:SI (reg:QI 0 x0 [ i ])))
    and
    (set (reg:SI 96)
        (and:SI (ashift:SI (reg:SI 0 x0 [ i ])
                (const_int 11 [0xb]))
            (const_int 522240 [0x7f800])))
    and in the end results in 3 instructions in the body:
            and     w1, w0, 255
            ubfiz   w0, w0, 11, 8
            orr     w0, w0, w1
    The following combine splitters help undo that when combiner tries to
    combine 3 instructions - the zero/sign extend or and, the other insn
    from the 2 to 2 combination ([us]bfiz) and the logical op, the CPUs
    don't have an insn to do everything in one op, but we can split it
    back into the zero/sign extend or and followed by logical with lsl.

    2021-04-15  Jakub Jelinek  <jakub@redhat.com>

            PR target/100056
            * config/aarch64/aarch64.md
(*<LOGICAL:optab>_<SHIFT:optab><mode>3):
            Add combine splitters for *<LOGICAL:optab>_ashl<mode>3 with
            ZERO_EXTEND, SIGN_EXTEND or AND.

            * gcc.target/aarch64/pr100056.c: New test.