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* [Bug target/100093] New: different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
@ 2021-04-15 9:09 crazylht at gmail dot com
2021-04-15 9:35 ` [Bug target/100093] " crazylht at gmail dot com
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-04-15 9:09 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093
Bug ID: 100093
Summary: different behavior between -mtune=cpu_type and
target_attribute (“arch=cputype”)
Product: gcc
Version: 11.0
Status: UNCONFIRMED
Severity: normal
Priority: P3
Component: target
Assignee: unassigned at gcc dot gnu.org
Reporter: crazylht at gmail dot com
CC: hjl.tools at gmail dot com
Target Milestone: ---
Host: x86_64-pc-linux-gnu
Target: x86_64-*-* i?86-*-*
Refer to https://godbolt.org/z/31nv3T8Tf
__attribute__((target("tune=skylake-avx512")))
void fill_avx2(double *__restrict__ data, int n, double value)
{
for (int i = 0; i < n * 16; i++) {
data[i] = value;
}
}
Shouldn't command line gcc -O3 -march=znver1 generate same codes gcc -O3
-march=znver1 -mtune=skylake-avx512?
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
2021-04-15 9:09 [Bug target/100093] New: different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”) crazylht at gmail dot com
@ 2021-04-15 9:35 ` crazylht at gmail dot com
2021-04-16 6:14 ` crazylht at gmail dot com
` (2 subsequent siblings)
3 siblings, 0 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-04-15 9:35 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093
--- Comment #1 from Hongtao.liu <crazylht at gmail dot com> ---
When ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL] is false,
GCC goes to set up the bit MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE, but when
ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL
features[X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL] is true, it doesn't to
clear the bit which causes the issue.
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD;
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
2021-04-15 9:09 [Bug target/100093] New: different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”) crazylht at gmail dot com
2021-04-15 9:35 ` [Bug target/100093] " crazylht at gmail dot com
@ 2021-04-16 6:14 ` crazylht at gmail dot com
2021-04-23 1:19 ` cvs-commit at gcc dot gnu.org
2021-04-23 1:19 ` crazylht at gmail dot com
3 siblings, 0 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-04-16 6:14 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093
--- Comment #2 from Hongtao.liu <crazylht at gmail dot com> ---
Created attachment 50611
--> https://gcc.gnu.org/bugzilla/attachment.cgi?id=50611&action=edit
tested patch waiting for GCC12.
[i386] MASK_AVX256_SPLIT_UNALIGNED_STORE/LOAD should be cleared in
opts->x_target_flags when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL
is enabled by target attribute.
gcc/ChangeLog:
PR target/10093
* config/i386/i386-options.c (ix86_option_override_internal):
Clear MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE in x_target_flags
when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is enabled
by target attribute.
gcc/testsuite/ChangeLog:
PR target/10093
* gcc.target/i386/pr10093.c: New test.
2 files changed, 19 insertions(+)
gcc/config/i386/i386-options.c | 7 +++++++
gcc/testsuite/gcc.target/i386/pr10093.c | 12 ++++++++++++
modified gcc/config/i386/i386-options.c
@@ -2853,9 +2853,16 @@ ix86_option_override_internal (bool main_args_p,
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_LOAD))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_LOAD;
+ else if (!main_args_p
+ && ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_LOAD_OPTIMAL])
+ opts->x_target_flags &= ~MASK_AVX256_SPLIT_UNALIGNED_LOAD;
+
if (!ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL]
&& !(opts_set->x_target_flags & MASK_AVX256_SPLIT_UNALIGNED_STORE))
opts->x_target_flags |= MASK_AVX256_SPLIT_UNALIGNED_STORE;
+ else if (!main_args_p
+ && ix86_tune_features[X86_TUNE_AVX256_UNALIGNED_STORE_OPTIMAL])
+ opts->x_target_flags &= ~MASK_AVX256_SPLIT_UNALIGNED_STORE;
/* Enable 128-bit AVX instruction generation
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
2021-04-15 9:09 [Bug target/100093] New: different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”) crazylht at gmail dot com
2021-04-15 9:35 ` [Bug target/100093] " crazylht at gmail dot com
2021-04-16 6:14 ` crazylht at gmail dot com
@ 2021-04-23 1:19 ` cvs-commit at gcc dot gnu.org
2021-04-23 1:19 ` crazylht at gmail dot com
3 siblings, 0 replies; 5+ messages in thread
From: cvs-commit at gcc dot gnu.org @ 2021-04-23 1:19 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093
--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:
https://gcc.gnu.org/g:342de04d993beaa644d0b0087c20bef5dad5bf5f
commit r12-78-g342de04d993beaa644d0b0087c20bef5dad5bf5f
Author: liuhongt <hongtao.liu@intel.com>
Date: Fri Apr 16 11:29:10 2021 +0800
MASK_AVX256_SPLIT_UNALIGNED_STORE/LOAD should be cleared in
opts->x_target_flags when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is
enabled by target attribute.
gcc/ChangeLog:
PR target/100093
* config/i386/i386-options.c (ix86_option_override_internal):
Clear MASK_AVX256_SPLIT_UNALIGNED_LOAD/STORE in x_target_flags
when X86_TUNE_AVX256_UNALIGNED_LOAD/STORE_OPTIMAL is enabled
by target attribute.
gcc/testsuite/ChangeLog:
PR target/100093
* gcc.target/i386/pr100093.c: New test.
^ permalink raw reply [flat|nested] 5+ messages in thread
* [Bug target/100093] different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”)
2021-04-15 9:09 [Bug target/100093] New: different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”) crazylht at gmail dot com
` (2 preceding siblings ...)
2021-04-23 1:19 ` cvs-commit at gcc dot gnu.org
@ 2021-04-23 1:19 ` crazylht at gmail dot com
3 siblings, 0 replies; 5+ messages in thread
From: crazylht at gmail dot com @ 2021-04-23 1:19 UTC (permalink / raw)
To: gcc-bugs
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100093
Hongtao.liu <crazylht at gmail dot com> changed:
What |Removed |Added
----------------------------------------------------------------------------
Resolution|--- |FIXED
Status|UNCONFIRMED |RESOLVED
--- Comment #4 from Hongtao.liu <crazylht at gmail dot com> ---
Fixed in GCC12.
^ permalink raw reply [flat|nested] 5+ messages in thread
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2021-04-15 9:09 [Bug target/100093] New: different behavior between -mtune=cpu_type and target_attribute (“arch=cputype”) crazylht at gmail dot com
2021-04-15 9:35 ` [Bug target/100093] " crazylht at gmail dot com
2021-04-16 6:14 ` crazylht at gmail dot com
2021-04-23 1:19 ` cvs-commit at gcc dot gnu.org
2021-04-23 1:19 ` crazylht at gmail dot com
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