[Bug target/100265] New: [RISCV] Use proper fences for atomic load/store

[Bug target/100265] New: [RISCV] Use proper fences for atomic load/store

[christophm30 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100265

            Bug ID: 100265
           Summary: [RISCV] Use proper fences for atomic load/store
           Product: gcc
           Version: unknown
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: christophm30 at gmail dot com
  Target Milestone: ---

On RISC-V we don't have load/store instructions with memory ordering bits.
To enforce memory ordering we need to use FENCE instructions.
The good thing is, we can have support for sub-word load/store.

The particular FENCE arguments (i.e. how to map the C ordering to RISC-V
ordering is documented in the RISC-V unpriv spec in section "Code Porting and
Mapping Guidelines").

Currenlty, GCC generates the following:

load_u32_n:
  lw a0,0(a0)
  sext.w a0,a0
  ret

load_u32_aq_n:
  lw a0,0(a0)
  fence iorw,iorw
  sext.w a0,a0
  ret

store_u32_n:
  amoswap.w zero,a1,0(a0)
  ret

store_u32_rl_n:
  fence iorw,ow
  amoswap.w zero,a1,0(a0)
  ret

The goal would be to generate this as follows:

load_u32_n:
  lw a0,0(a0)
  ret

load_u32_aq_n:
  lw a0,0(a0)
  fence r,rw
  ret

store_au32_n:
  sw a1,0(a0)
  ret

store_au32_rl_n:
  fence rw,w
  sw a1,0(a0)
  ret

[Bug target/100265] [RISCV] Use proper fences for atomic load/store

[christophm30 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100265

--- Comment #1 from Christoph M. <christophm30 at gmail dot com> ---
A patchset to resolve this can be found here:
  https://gcc.gnu.org/pipermail/gcc-patches/2021-April/568684.html

[Bug target/100265] [RISCV] Use proper fences for atomic load/store

[patrick at rivosinc dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100265

Patrick O'Neill <patrick at rivosinc dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |patrick at rivosinc dot com

--- Comment #2 from Patrick O'Neill <patrick at rivosinc dot com> ---
I believe this issue should be resolved now that the atomics fixes from a few
months ago have landed/the atomics mappings are defined in the RISC-V PSABI
doc.
https://inbox.sourceware.org/gcc-patches/20230427162301.1151333-1-patrick@rivosinc.com/

Also backported for GCC 13.3
https://inbox.sourceware.org/gcc-patches/20230725180206.284777-1-patrick@rivosinc.com/

Thanks!

[Bug target/100265] [RISCV] Use proper fences for atomic load/store

[christophm30 at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100265

Christoph Müllner <christophm30 at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED

--- Comment #3 from Christoph Müllner <christophm30 at gmail dot com> ---
Yes, this got fixed.