[Bug target/100757] New: arm: ICE (unrecognizable insn) with MVE VPSELQ_S

[Bug target/100757] New: arm: ICE (unrecognizable insn) with MVE VPSELQ_S

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

            Bug ID: 100757
           Summary: arm: ICE (unrecognizable insn) with MVE VPSELQ_S
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: acoplan at gcc dot gnu.org
  Target Milestone: ---

This appears to be a recent regression on the trunk:

$ gcc/xgcc -v
Using built-in specs.
COLLECT_GCC=gcc/xgcc
Target: arm-eabi
Configured with: /home/alecop01/toolchain/src/gcc/configure
--prefix=/data_sdb/toolchain/cc1s/arm --enable-languages=c,c++
--disable-bootstrap --target=arm-eabi
Thread model: single
Supported LTO compression algorithms: zlib
gcc version 12.0.0 20210525 (experimental) (GCC)
$ cat test.c
extern int a[];
int n;
void foo(int x, _Bool b) {
  for (int i = 0; i < n; i++)
    a[i] = x || b;
}
$ gcc/xgcc -B gcc -c test.c -march=armv8.1-m.main+mve -mfloat-abi=hard -O
-ftree-vectorize -mtune=cortex-a55
test.c: In function ‘foo’:
test.c:6:1: error: unrecognizable insn:
    6 | }
      | ^
(insn 44 43 45 6 (set (reg:V4SI 131 [ vect_patt_4.10 ])
        (unspec:V4SI [
                (reg:V4SI 149)
                (reg:V4SI 150)
                (reg:V4SI 148 [ mask__2.9 ])
            ] VPSELQ_S)) -1
     (nil))
during RTL pass: vregs
test.c:6:1: internal compiler error: in extract_insn, at recog.c:2770
0x5e9fc6 _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.c:108
0x5e9fe5 _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.c:116
0xc770c7 extract_insn(rtx_insn*)
        /home/alecop01/toolchain/src/gcc/gcc/recog.c:2770
0x9aa78a instantiate_virtual_regs_in_insn
        /home/alecop01/toolchain/src/gcc/gcc/function.c:1609
0x9aa78a instantiate_virtual_regs
        /home/alecop01/toolchain/src/gcc/gcc/function.c:1983
0x9aa78a execute
        /home/alecop01/toolchain/src/gcc/gcc/function.c:2032
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

Christophe Lyon <clyon at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |clyon at gcc dot gnu.org

--- Comment #1 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Maybe that's related to my recent MVE patches?

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #2 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Could be, I'm bisecting it now...

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |12.0

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2021-05-26
            Summary|[12 Regression] arm: ICE    |[12 Regression] arm: ICE
                   |(unrecognizable insn) with  |(unrecognizable insn) with
                   |MVE VPSELQ_S                |MVE VPSELQ_S since
                   |                            |r12-834-ga6eacbf10
     Ever confirmed|0                           |1

--- Comment #3 from Alex Coplan <acoplan at gcc dot gnu.org> ---
(In reply to Christophe Lyon from comment #1)
> Maybe that's related to my recent MVE patches?

Yeah, started with r12-834-ga6eacbf1055520e968d1a25f6d30d6ff4b66272d

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

Christophe Lyon <clyon at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |clyon at gcc dot gnu.org
             Status|NEW                         |ASSIGNED

--- Comment #4 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Sigh, I did write & run several tests though :-(

I had to add -mfpu=auto because I configured my toolchain --with-fpu=neon, and
I need to keep -mtune=cortex-a55.

BTW, was it a typo on your side: cortex-a55 instead of cortex-m55?
With cortex-m55 the test doesn't crash.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #5 from Alex Coplan <acoplan at gcc dot gnu.org> ---
(In reply to Christophe Lyon from comment #4)
> Sigh, I did write & run several tests though :-(
> 
> I had to add -mfpu=auto because I configured my toolchain --with-fpu=neon,
> and I need to keep -mtune=cortex-a55.
> 
> BTW, was it a typo on your side: cortex-a55 instead of cortex-m55?
> With cortex-m55 the test doesn't crash.

Not a typo. I run some GCC testing with random options including with random
-mtune options. Although -mtune=cortex-a55 isn't a sensible choice given that
we're targeting MVE, it shouldn't ICE.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #6 from Christophe Lyon <clyon at gcc dot gnu.org> ---
That's related to the tune_params::LOG_OP_NON_SHORT_CIRCUIT tuning param for
Thumb mode. Setting it to FALSE in the a53 tuning params (used by a55) avoids
the ICE.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #7 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Note that it also ICEs with e.g. -mtune=arm920t.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #8 from Christophe Lyon <clyon at gcc dot gnu.org> ---
At expand time, we have:

(insn 33 32 34 6 (set (reg:V4SI 144)
        (const_vector:V4SI [
                (const_int 0 [0]) repeated x4
            ])) "bz-100757.c":5:12 -1
     (nil))
(insn 34 33 35 6 (set (reg:HI 143)
        (ne:HI (reg:V4SI 126 [ vect_cst__32 ])
            (reg:V4SI 144))) "bz-100757.c":5:12 -1
     (nil))
(insn 35 34 36 6 (set (reg:V4SI 145)
        (const_vector:V4SI [
                (const_int 0 [0]) repeated x4
            ])) "bz-100757.c":5:12 -1
     (nil))
(insn 36 35 37 6 (set (reg:V4SI 146)
        (const_vector:V4SI [
                (const_int 1 [0x1]) repeated x4
            ])) "bz-100757.c":5:12 -1
     (nil))
(insn 37 36 38 6 (set (reg:V4SI 142 [ mask__1.8 ])
        (unspec:V4SI [
                (reg:V4SI 146)
                (reg:V4SI 145)
                (reg:HI 143)
            ] VPSELQ_S)) "bz-100757.c":5:12 -1
     (nil))
(insn 38 37 39 6 (set (reg:V4SI 147 [ mask__2.9 ])
        (ior:V4SI (reg:V4SI 142 [ mask__1.8 ])
            (reg:V4SI 130 [ vect_cst__36 ]))) "bz-100757.c":5:14 -1
     (nil))
(insn 39 38 40 6 (set (reg:V4SI 148)
        (const_vector:V4SI [
                (const_int 1 [0x1]) repeated x4
            ])) -1
     (nil))
(insn 40 39 41 6 (set (reg:V4SI 149)
        (const_vector:V4SI [
                (const_int 0 [0]) repeated x4
            ])) -1
     (nil))
(insn 41 40 42 6 (set (reg:V4SI 132 [ vect_patt_4.10 ])
        (unspec:V4SI [
                (reg:V4SI 148)
                (reg:V4SI 149)
                (reg:V4SI 147 [ mask__2.9 ])
            ] VPSELQ_S)) -1
     (nil))


The problem is with the second VPSELQ_S, where operand 3 is not of HI type.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #9 from Alex Coplan <acoplan at gcc dot gnu.org> ---
Hi Christophe,

FYI, I just did a testsuite run on a toolchain configured with
--with-arch=armv8.1-m.main+mve.fp+fp.dp and --with-float=hard. I'm seeing
several ICEs at -O3, e.g.:

$ ../../build-arm-eabi-armv8.1-m.main+mve.fp+fp.dp/install/bin/arm-eabi-gcc
gcc/testsuite/gcc.c-torture/compile/20160205-1.c -O3
gcc/testsuite/gcc.c-torture/compile/20160205-1.c: In function 'fn1':
gcc/testsuite/gcc.c-torture/compile/20160205-1.c:8:1: error: unrecognizable
insn:
    8 | }
      | ^
(insn 71 70 72 2 (set (reg:V4SI 121 [ vect_c_2.8 ])
        (unspec:V4SI [
                (reg:V4SI 208)
                (reg:V4SI 209)
                (reg:V4SI 207)
            ] VPSELQ_S)) -1
     (nil))
during RTL pass: vregs
gcc/testsuite/gcc.c-torture/compile/20160205-1.c:8:1: internal compiler error:
in extract_insn, at recog.c:2770
0xccc6ef _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.c:108
0xccc70e _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /home/alecop01/toolchain/src/gcc/gcc/rtl-error.c:116
0xc9b2b3 extract_insn(rtx_insn*)
        /home/alecop01/toolchain/src/gcc/gcc/recog.c:2770
0x9bd383 instantiate_virtual_regs_in_insn
        /home/alecop01/toolchain/src/gcc/gcc/function.c:1611
0x9bd383 instantiate_virtual_regs
        /home/alecop01/toolchain/src/gcc/gcc/function.c:1985
0x9bd383 execute
        /home/alecop01/toolchain/src/gcc/gcc/function.c:2034
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

Note that these don't need any special scheduling to show up.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #10 from Christophe Lyon <clyon at gcc dot gnu.org> ---
The problem is in vec-common.md:
(define_expand "vcond_mask_<mode><v_cmp_result>"
  [(set (match_operand:VDQWH 0 "s_register_operand")
        (if_then_else:VDQWH
          (match_operand:<V_cmp_result> 3 "s_register_operand")
          (match_operand:VDQWH 1 "s_register_operand")
          (match_operand:VDQWH 2 "s_register_operand")))]
  "ARM_HAVE_<MODE>_ARITH
   && !TARGET_REALLY_IWMMXT
   && (!<Is_float_mode> || flag_unsafe_math_optimizations)"
{
  if (TARGET_NEON)
    {
      emit_insn (gen_neon_vbsl (<MODE>mode, operands[0], operands[3],
                                operands[1], operands[2]));
    }
  else if (TARGET_HAVE_MVE)
    {
      emit_insn (gen_mve_vpselq (VPSELQ_S, <MODE>mode, operands[0],
                                 operands[1], operands[2], operands[3]));
    }
  else
    gcc_unreachable ();
  DONE;
})

For MVE, we pass operands[3] to mve_vpselq, but it has the same vector mode as
the other operands while vpselq expects a 16-bit mask (HI mode) suitable for
VPR.P0

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #11 from Alex Coplan <acoplan at gcc dot gnu.org> ---
@Christophe: do you still plan to look at this? I'm happy to pick it up if not

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #12 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Yes, I've been working on it for a while, it's proving to be a bit tricky when
switching to HImode as suggested by Richard. I have something working, now
checking I haven't broken Neon.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #13 from Christophe Lyon <clyon at gcc dot gnu.org> ---
This is also related to https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101325

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[vvinayag at arm dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

vvinayag at arm dot com changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |vvinayag at arm dot com

--- Comment #14 from vvinayag at arm dot com ---
(In reply to Christophe Lyon from comment #12)
> Yes, I've been working on it for a while, it's proving to be a bit tricky
> when switching to HImode as suggested by Richard. I have something working,
> now checking I haven't broken Neon.

Hi Christophe, if you are working on this, just wondering whether we are close
to getting a patch for this, thank you.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #15 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Hi, yes this is close to completion.
The patch series was approved last week by Richard Sandiford:
https://gcc.gnu.org/pipermail/gcc-patches/2021-October/581778.html

but I have found a bug with more validations, I'm discussing the fix with him,
should be ready shortly.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P1

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #16 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:884f77b4222289510e1df9db2889b60c5df6fcda

commit r12-7338-g884f77b4222289510e1df9db2889b60c5df6fcda
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Oct 13 09:16:22 2021 +0000

    arm: Implement MVE predicates as vectors of booleans

    This patch implements support for vectors of booleans to support MVE
    predicates, instead of HImode.  Since the ABI mandates pred16_t (aka
    uint16_t) to represent predicates in intrinsics prototypes, we
    introduce a new "predicate" type qualifier so that we can map relevant
    builtins HImode arguments and return value to the appropriate vector
    of booleans (VxBI).

    We have to update test_vector_ops_duplicate, because it iterates using
    an offset in bytes, where we would need to iterate in bits: we stop
    iterating when we reach the end of the vector of booleans.

    In addition, we have to fix the underlying definition of vectors of
    booleans because ARM/MVE needs a different representation than
    AArch64/SVE. With ARM/MVE the 'true' bit is duplicated over the
    element size, so that a true element of V4BI is represented by
    '0b1111'.  This patch updates the aarch64 definition of VNx*BI as
    needed.

    Most of the work of this patch series was carried out while I was
    working at STMicroelectronics as a Linaro assignee.

    2022-02-22  Christophe Lyon  <christophe.lyon@arm.com>
                Richard Sandiford  <richard.sandiford@arm.com>

            gcc/
            PR target/100757
            PR target/101325
            * config/aarch64/aarch64-modes.def (VNx16BI, VNx8BI, VNx4BI,
            VNx2BI): Update definition.
            * config/arm/arm-builtins.cc (arm_init_simd_builtin_types): Add new
            simd types.
            (arm_init_builtin): Map predicate vectors arguments to HImode.
            (arm_expand_builtin_args): Move HImode predicate arguments to VxBI
            rtx. Move return value to HImode rtx.
            * config/arm/arm-builtins.h (arm_type_qualifiers): Add
qualifier_predicate.
            * config/arm/arm-modes.def (B2I, B4I, V16BI, V8BI, V4BI): New
modes.
            * config/arm/arm-simd-builtin-types.def (Pred1x16_t,
            Pred2x8_t,Pred4x4_t): New.
            * emit-rtl.cc (init_emit_once): Handle all boolean modes.
            * genmodes.cc (mode_data): Add boolean field.
            (blank_mode): Initialize it.
            (make_complex_modes): Fix handling of boolean modes.
            (make_vector_modes): Likewise.
            (VECTOR_BOOL_MODE): Use new COMPONENT parameter.
            (make_vector_bool_mode): Likewise.
            (BOOL_MODE): New.
            (make_bool_mode): New.
            (emit_insn_modes_h): Fix generation of boolean modes.
            (emit_class_narrowest_mode): Likewise.
            * machmode.def: (VECTOR_BOOL_MODE): Document new COMPONENT
            parameter.  Use new BOOL_MODE instead of FRACTIONAL_INT_MODE to
            define BImode.
            * rtx-vector-builder.cc (rtx_vector_builder::find_cached_value):
            Fix handling of constm1_rtx for VECTOR_BOOL.
            * simplify-rtx.cc (native_encode_rtx): Fix support for VECTOR_BOOL.
            (native_decode_vector_rtx): Likewise.
            (test_vector_ops_duplicate): Skip vec_merge test
            with vectors of booleans.
            * varasm.cc (output_constant_pool_2): Likewise.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #17 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:91224cf625dc90304bb515a0cc602beed48fe3da

commit r12-7339-g91224cf625dc90304bb515a0cc602beed48fe3da
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Oct 13 09:16:27 2021 +0000

    arm: Implement auto-vectorized MVE comparisons with vectors of boolean
predicates

    We make use of qualifier_predicate to describe MVE builtins
    prototypes, restricting to auto-vectorizable vcmp* and vpsel builtins,
    as they are exercised by the tests added earlier in the series.

    Special handling is needed for mve_vpselq because it has a v2di
    variant, which has no natural VPR.P0 representation: we keep HImode
    for it.

    The vector_compare expansion code is updated to use the right VxBI
    mode instead of HI for the result.

    We extend the existing thumb2_movhi_vfp and thumb2_movhi_fp16 patterns
    to use the new MVE_7_HI iterator which covers HI and the new VxBI
    modes, in conjunction with the new DB constraint for a constant vector
    of booleans.

    This patch also adds tests derived from the one provided in PR
    target/101325: there is a compile-only test because I did not have
    access to anything that could execute MVE code until recently.  I have
    been able to add an executable test since QEMU supports MVE.

    Instead of adding arm_v8_1m_mve_hw, I update arm_mve_hw so that it
    uses add_options_for_arm_v8_1m_mve_fp, like arm_neon_hw does.  This
    ensures arm_mve_hw passes even if the toolchain does not generate MVE
    code by default.

    Most of the work of this patch series was carried out while I was
    working at STMicroelectronics as a Linaro assignee.

    2022-02-22  Christophe Lyon <christophe.lyon@arm.com>
                Richard Sandiford  <richard.sandiford@arm.com>

            gcc/
            PR target/100757
            PR target/101325
            * config/arm/arm-builtins.cc (BINOP_PRED_UNONE_UNONE_QUALIFIERS)
            (BINOP_PRED_NONE_NONE_QUALIFIERS)
            (TERNOP_NONE_NONE_NONE_PRED_QUALIFIERS)
            (TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS): New.
            * config/arm/arm-protos.h (mve_bool_vec_to_const): New.
            * config/arm/arm.cc (arm_hard_regno_mode_ok): Handle new VxBI
            modes.
            (arm_mode_to_pred_mode): New.
            (arm_expand_vector_compare): Use the right VxBI mode instead of
            HI.
            (arm_expand_vcond): Likewise.
            (simd_valid_immediate): Handle MODE_VECTOR_BOOL.
            (mve_bool_vec_to_const): New.
            (neon_make_constant): Call mve_bool_vec_to_const when needed.
            * config/arm/arm_mve_builtins.def (vcmpneq_, vcmphiq_, vcmpcsq_)
            (vcmpltq_, vcmpleq_, vcmpgtq_, vcmpgeq_, vcmpeqq_, vcmpneq_f)
            (vcmpltq_f, vcmpleq_f, vcmpgtq_f, vcmpgeq_f, vcmpeqq_f, vpselq_u)
            (vpselq_s, vpselq_f): Use new predicated qualifiers.
            * config/arm/constraints.md (DB): New.
            * config/arm/iterators.md (MVE_7, MVE_7_HI): New mode iterators.
            (MVE_VPRED, MVE_vpred): New attribute iterators.
            * config/arm/mve.md (@mve_vcmp<mve_cmp_op>q_<mode>)
            (@mve_vcmp<mve_cmp_op>q_f<mode>, @mve_vpselq_<supf><mode>)
            (@mve_vpselq_f<mode>): Use MVE_VPRED instead of HI.
            (@mve_vpselq_<supf>v2di): Define separately.
            (mov<mode>): New expander for VxBI modes.
            * config/arm/vfp.md (thumb2_movhi_vfp, thumb2_movhi_fp16): Use
            MVE_7_HI iterator and add support for DB constraint.

            gcc/testsuite/
            PR target/100757
            PR target/101325
            * gcc.dg/rtl/arm/mve-vxbi.c: New test.
            * gcc.target/arm/simd/pr101325.c: New.
            * gcc.target/arm/simd/pr101325-2.c: New.
            * lib/target-supports.exp (check_effective_target_arm_mve_hw): Use
            add_options_for_arm_v8_1m_mve_fp.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #18 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:df0e57c2c032cea0f77f2e68231c035f282b26d6

commit r12-7340-gdf0e57c2c032cea0f77f2e68231c035f282b26d6
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Oct 20 15:30:16 2021 +0000

    arm: Fix vcond_mask expander for MVE (PR target/100757)

    The problem in this PR is that we call VPSEL with a mask of vector
    type instead of HImode. This happens because operand 3 in vcond_mask
    is the pre-computed vector comparison and has vector type.

    This patch fixes it by implementing TARGET_VECTORIZE_GET_MASK_MODE,
    returning the appropriate VxBI mode when targeting MVE.  In turn, this
    implies implementing vec_cmp<mode><MVE_vpred>,
    vec_cmpu<mode><MVE_vpred> and vcond_mask_<mode><MVE_vpred>, and we can
    move vec_cmp<mode><v_cmp_result>, vec_cmpu<mode><mode> and
    vcond_mask_<mode><v_cmp_result> back to neon.md since they are not
    used by MVE anymore.  The new *<MVE_vpred> patterns listed above are
    implemented in mve.md since they are only valid for MVE. However this
    may make maintenance/comparison more painful than having all of them
    in vec-common.md.

    In the process, we can get rid of the recently added vcond_mve
    parameter of arm_expand_vector_compare.

    Compared to neon.md's vcond_mask_<mode><v_cmp_result> before my "arm:
    Auto-vectorization for MVE: vcmp" patch (r12-834), it keeps the VDQWH
    iterator added in r12-835 (to have V4HF/V8HF support), as well as the
    (!<Is_float_mode> || flag_unsafe_math_optimizations) condition which
    was not present before r12-834 although SF modes were enabled by VDQW
    (I think this was a bug).

    Using TARGET_VECTORIZE_GET_MASK_MODE has the advantage that we no
    longer need to generate vpsel with vectors of 0 and 1: the masks are
    now merged via scalar 'ands' instructions operating on 16-bit masks
    after converting the boolean vectors.

    In addition, this patch fixes a problem in arm_expand_vcond() where
    the result would be a vector of 0 or 1 instead of operand 1 or 2.

    Since we want to skip gcc.dg/signbit-2.c for MVE, we also add a new
    arm_mve effective target.

    Reducing the number of iterations in pr100757-3.c from 32 to 8, we
    generate the code below:

    float a[32];
    float fn1(int d) {
      float c = 4.0f;
      for (int b = 0; b < 8; b++)
        if (a[b] != 2.0f)
          c = 5.0f;
      return c;
    }

    fn1:
            ldr     r3, .L3+48
            vldr.64 d4, .L3              // q2=(2.0,2.0,2.0,2.0)
            vldr.64 d5, .L3+8
            vldrw.32        q0, [r3]     // q0=a(0..3)
            adds    r3, r3, #16
            vcmp.f32        eq, q0, q2   // cmp a(0..3) == (2.0,2.0,2.0,2.0)
            vldrw.32        q1, [r3]     // q1=a(4..7)
            vmrs     r3, P0
            vcmp.f32        eq, q1, q2   // cmp a(4..7) == (2.0,2.0,2.0,2.0)
            vmrs    r2, P0  @ movhi
            ands    r3, r3, r2           // r3=select(a(0..3]) &
select(a(4..7))
            vldr.64 d4, .L3+16           // q2=(5.0,5.0,5.0,5.0)
            vldr.64 d5, .L3+24
            vmsr     P0, r3
            vldr.64 d6, .L3+32           // q3=(4.0,4.0,4.0,4.0)
            vldr.64 d7, .L3+40
            vpsel q3, q3, q2             // q3=vcond_mask(4.0,5.0)
            vmov.32 r2, q3[1]            // keep the scalar max
            vmov.32 r0, q3[3]
            vmov.32 r3, q3[2]
            vmov.f32        s11, s12
            vmov    s15, r2
            vmov    s14, r3
            vmaxnm.f32      s15, s11, s15
            vmaxnm.f32      s15, s15, s14
            vmov    s14, r0
            vmaxnm.f32      s15, s15, s14
            vmov    r0, s15
            bx      lr
            .L4:
            .align  3
            .L3:
            .word   1073741824      // 2.0f
            .word   1073741824
            .word   1073741824
            .word   1073741824
            .word   1084227584      // 5.0f
            .word   1084227584
            .word   1084227584
            .word   1084227584
            .word   1082130432      // 4.0f
            .word   1082130432
            .word   1082130432
            .word   1082130432

    This patch adds tests that trigger an ICE without this fix.

    The pr100757*.c testcases are derived from
    gcc.c-torture/compile/20160205-1.c, forcing the use of MVE, and using
    various types and return values different from 0 and 1 to avoid
    commonalization with boolean masks.  In addition, since we should not
    need these masks, the tests make sure they are not present.

    Most of the work of this patch series was carried out while I was
    working at STMicroelectronics as a Linaro assignee.

    2022-02-22  Christophe Lyon  <christophe.lyon@arm.com>

            PR target/100757
            gcc/
            * config/arm/arm-protos.h (arm_get_mask_mode): New prototype.
            (arm_expand_vector_compare): Update prototype.
            * config/arm/arm.cc (TARGET_VECTORIZE_GET_MASK_MODE): New.
            (arm_vector_mode_supported_p): Add support for VxBI modes.
            (arm_expand_vector_compare): Remove useless generation of vpsel.
            (arm_expand_vcond): Fix select operands.
            (arm_get_mask_mode): New.
            * config/arm/mve.md (vec_cmp<mode><MVE_vpred>): New.
            (vec_cmpu<mode><MVE_vpred>): New.
            (vcond_mask_<mode><MVE_vpred>): New.
            * config/arm/vec-common.md (vec_cmp<mode><v_cmp_result>)
            (vec_cmpu<mode><mode, vcond_mask_<mode><v_cmp_result>): Move to ...
            * config/arm/neon.md (vec_cmp<mode><v_cmp_result>)
            (vec_cmpu<mode><mode, vcond_mask_<mode><v_cmp_result>): ... here
            and disable for MVE.
            * doc/sourcebuild.texi (arm_mve): Document new effective-target.

            gcc/testsuite/
            PR target/100757
            * gcc.target/arm/simd/pr100757-2.c: New.
            * gcc.target/arm/simd/pr100757-3.c: New.
            * gcc.target/arm/simd/pr100757-4.c: New.
            * gcc.target/arm/simd/pr100757.c: New.
            * gcc.dg/signbit-2.c: Skip when targeting ARM/MVE.
            * lib/target-supports.exp (check_effective_target_arm_mve): New.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #19 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:e6a4aefce8e47a7d3ba781066a1410ebfa963e59

commit r12-7341-ge6a4aefce8e47a7d3ba781066a1410ebfa963e59
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Oct 13 09:16:35 2021 +0000

    arm: Convert remaining MVE vcmp builtins to predicate qualifiers

    This is mostly a mechanical change, only tested by the intrinsics
    expansion tests.

    Most of the work of this patch series was carried out while I was
    working at STMicroelectronics as a Linaro assignee.

    2022-02-22  Christophe Lyon  <christophe.lyon@arm.com>

            gcc/
            PR target/100757
            PR target/101325
            * config/arm/arm-builtins.cc (BINOP_UNONE_NONE_NONE_QUALIFIERS):
            Delete.
            (TERNOP_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ...
            (TERNOP_PRED_NONE_NONE_PRED_QUALIFIERS): ... this.
            (TERNOP_PRED_UNONE_UNONE_PRED_QUALIFIERS): New.
            * config/arm/arm_mve_builtins.def (vcmp*q_n_, vcmp*q_m_f): Use new
            predicated qualifiers.
            * config/arm/mve.md (mve_vcmp<mve_cmp_op>q_n_<mode>)
            (mve_vcmp*q_m_f<mode>): Use MVE_VPRED instead of HI.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #20 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:724d6566cd11c676f3bc082a9771784c825affb1

commit r12-7342-g724d6566cd11c676f3bc082a9771784c825affb1
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Oct 13 09:16:40 2021 +0000

    arm: Convert more MVE builtins to predicate qualifiers

    This patch covers all builtins that have an HI operand and use the
    <mode> iterator, thus we can replace HI whe <MVE_vpred>.

    Most of the work of this patch series was carried out while I was
    working at STMicroelectronics as a Linaro assignee.

    2022-02-22  Christophe Lyon  <christophe.lyon@arm.com>

            gcc/
            PR target/100757
            PR target/101325
            * config/arm/arm-builtins.cc
(TERNOP_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ...
            (TERNOP_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this.
            (TERNOP_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ...
            (TERNOP_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this.
            (TERNOP_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ...
            (TERNOP_NONE_NONE_IMM_PRED_QUALIFIERS): ... this.
            (TERNOP_NONE_NONE_UNONE_UNONE_QUALIFIERS): Change to ...
            (TERNOP_NONE_NONE_UNONE_PRED_QUALIFIERS): ... this.
            (QUADOP_UNONE_UNONE_NONE_NONE_UNONE_QUALIFIERS): Change to ...
            (QUADOP_UNONE_UNONE_NONE_NONE_PRED_QUALIFIERS): ... this.
            (QUADOP_NONE_NONE_NONE_NONE_PRED_QUALIFIERS): New.
            (QUADOP_NONE_NONE_NONE_IMM_UNONE_QUALIFIERS): Change to ...
            (QUADOP_NONE_NONE_NONE_IMM_PRED_QUALIFIERS): ... this.
            (QUADOP_UNONE_UNONE_UNONE_UNONE_PRED_QUALIFIERS): New.
            (QUADOP_UNONE_UNONE_NONE_IMM_UNONE_QUALIFIERS): Change to ...
            (QUADOP_UNONE_UNONE_NONE_IMM_PRED_QUALIFIERS): ... this.
            (QUADOP_NONE_NONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ...
            (QUADOP_NONE_NONE_UNONE_IMM_PRED_QUALIFIERS): ... this.
            (QUADOP_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to ...
            (QUADOP_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this.
            (QUADOP_UNONE_UNONE_UNONE_NONE_UNONE_QUALIFIERS): Change to ...
            (QUADOP_UNONE_UNONE_UNONE_NONE_PRED_QUALIFIERS): ... this.
            (STRS_P_QUALIFIERS): Use predicate qualifier.
            (STRU_P_QUALIFIERS): Likewise.
            (STRSU_P_QUALIFIERS): Likewise.
            (STRSS_P_QUALIFIERS): Likewise.
            (LDRGS_Z_QUALIFIERS): Likewise.
            (LDRGU_Z_QUALIFIERS): Likewise.
            (LDRS_Z_QUALIFIERS): Likewise.
            (LDRU_Z_QUALIFIERS): Likewise.
            (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_UNONE_QUALIFIERS): Change to
...
            (QUINOP_UNONE_UNONE_UNONE_UNONE_IMM_PRED_QUALIFIERS): ... this.
            (BINOP_NONE_NONE_PRED_QUALIFIERS): New.
            (BINOP_UNONE_UNONE_PRED_QUALIFIERS): New.
            * config/arm/arm_mve_builtins.def: Use new predicated qualifiers.
            * config/arm/mve.md: Use MVE_VPRED instead of HI.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #21 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:6a7c13a0cf2290b60ab36f9ce1027b92838586bd

commit r12-7343-g6a7c13a0cf2290b60ab36f9ce1027b92838586bd
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Oct 20 15:39:17 2021 +0000

    arm: Convert more load/store MVE builtins to predicate qualifiers

    This patch covers a few builtins where we do not use the <mode>
    iterator and thus we cannot use <MVE_vpred>.

    For v2di instructions, we keep the HI mode for predicates.

    Most of the work of this patch series was carried out while I was
    working at STMicroelectronics as a Linaro assignee.

    2022-02-22  Christophe Lyon  <christophe.lyon@arm.com>

            gcc/
            PR target/100757
            PR target/101325
            * config/arm/arm-builtins.cc (STRSBS_P_QUALIFIERS): Use predicate
            qualifier.
            (STRSBU_P_QUALIFIERS): Likewise.
            (LDRGBS_Z_QUALIFIERS): Likewise.
            (LDRGBU_Z_QUALIFIERS): Likewise.
            (LDRGBWBXU_Z_QUALIFIERS): Likewise.
            (LDRGBWBS_Z_QUALIFIERS): Likewise.
            (LDRGBWBU_Z_QUALIFIERS): Likewise.
            (STRSBWBS_P_QUALIFIERS): Likewise.
            (STRSBWBU_P_QUALIFIERS): Likewise.
            * config/arm/mve.md: Use VxBI instead of HI.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #22 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:c6b4ea7ab1aa6c5c07798fa6c6ad15dd1761b5ed

commit r12-7344-gc6b4ea7ab1aa6c5c07798fa6c6ad15dd1761b5ed
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Oct 13 09:16:49 2021 +0000

    arm: Convert more MVE/CDE builtins to predicate qualifiers

    This patch covers a few non-load/store builtins where we do not use
    the <mode> iterator and thus we cannot use <MVE_vpred>.

    Most of the work of this patch series was carried out while I was
    working at STMicroelectronics as a Linaro assignee.

    2022-02-22  Christophe Lyon  <christophe.lyon@arm.com>

            gcc/
            PR target/100757
            PR target/101325
            * config/arm/arm-builtins.cc (CX_UNARY_UNONE_QUALIFIERS): Use
            predicate.
            (CX_BINARY_UNONE_QUALIFIERS): Likewise.
            (CX_TERNARY_UNONE_QUALIFIERS): Likewise.
            (TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete.
            (QUADOP_NONE_NONE_NONE_NONE_UNONE_QUALIFIERS): Delete.
            (QUADOP_UNONE_UNONE_UNONE_UNONE_UNONE_QUALIFIERS): Delete.
            * config/arm/arm_mve_builtins.def: Use predicated qualifiers.
            * config/arm/mve.md: Use VxBI instead of HI.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[clyon at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

Christophe Lyon <clyon at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #23 from Christophe Lyon <clyon at gcc dot gnu.org> ---
Should be fixed, at last.

[Bug target/100757] [12 Regression] arm: ICE (unrecognizable insn) with MVE VPSELQ_S since r12-834-ga6eacbf10

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100757

--- Comment #24 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Christophe Lyon <clyon@gcc.gnu.org>:

https://gcc.gnu.org/g:fd0ab7c734b04b91653467b94afd48ceca122083

commit r12-7356-gfd0ab7c734b04b91653467b94afd48ceca122083
Author: Christophe Lyon <christophe.lyon@arm.com>
Date:   Wed Feb 23 06:44:12 2022 +0000

    arm: Fix typo in auto-vectorized MVE comparisons

    I made a last minute renaming of mve_const_bool_vec_to_hi () into
    mve_bool_vec_to_const () and forgot to update the call sites in vfp.md
    accordingly.

    Committed as obvious.

    2022-02-23  Christophe Lyon <christophe.lyon@arm.com>

            gcc/
            PR target/100757
            PR target/101325
            * config/arm/vfp.md (thumb2_movhi_vfp, thumb2_movhi_fp16): Fix
            typo.