[Bug target/100762] New: [mips+msa] ICE when comparing 64 bit vectors

[Bug target/100762] New: [mips+msa] ICE when comparing 64 bit vectors

[evan@coeus-group.com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762

            Bug ID: 100762
           Summary: [mips+msa] ICE when comparing 64 bit vectors
           Product: gcc
           Version: 10.2.1
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: evan@coeus-group.com
  Target Milestone: ---

In MIPS with MSA enabled on GCC 10.2.1, any comparison operation on 64-bit
vectors results in an ICE.

Test case:


typedef int i32x2 __attribute__((__vector_size__(8)));

i32x2 cmp(i32x2 a, i32x2 b) {
  return a >= b;
}


$ mips64el-linux-gnuabi64-gcc-10 -march=loongson3a -mmsa -c -o test.o test.c
mips64el-linux-gnuabi64-gcc-10 -march=loongson3a -mmsa -c -o test.o test2.c
during RTL pass: expand
test.c: In function 'cmp':
test.c:4:12: internal compiler error: in mips_expand_vector_init, at
config/mips/mips.c:22076
    4 |   return a >= b;
      |          ~~^~~~
0x7f420202dd09 __libc_start_main
        ../csu/libc-start.c:308
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <file:///usr/share/doc/gcc-10/README.Bugs> for instructions.


This is with GCC 10.2.1-6 from Debian:


$ mips64el-linux-gnuabi64-gcc-10 --version
mips64el-linux-gnuabi64-gcc-10 (Debian 10.2.1-6) 10.2.1 20210110
Copyright (C) 2020 Free Software Foundation, Inc.
This is free software; see the source for copying conditions.  There is NO
warranty; not even for MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.

[Bug target/100762] [mips+msa] ICE when comparing 64 bit vectors

[evan@coeus-group.com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762

--- Comment #1 from Evan Nemerson <evan@coeus-group.com> ---
It's not just comparisons.  <<, >>, /, * also don't work.  AFAICT only bitwise
operations and +/- work, as well as everything with a 64-bit element type
(i.e., a vector of one element)… 8/16/32-bit elements all fail.

[Bug target/100762] [mips+msa] ICE when comparing 64 bit vectors

[xry111 at mengyan1223 dot wang]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762

Xi Ruoyao <xry111 at mengyan1223 dot wang> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |xry111 at mengyan1223 dot wang

--- Comment #2 from Xi Ruoyao <xry111 at mengyan1223 dot wang> ---
11.1.0 also ICE with this case.

[Bug target/100762] [mips+msa] ICE when comparing 64 bit vectors

[xry111 at mengyan1223 dot wang]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762

--- Comment #3 from Xi Ruoyao <xry111 at mengyan1223 dot wang> ---
There is some strange interaction between -mmsa and -mloongson-mmi causing
this.  It can be reproduced by building pixman (which enables -mloongson-mmi by
default) with -mmsa.

[Bug target/100762] [mips+msa] ICE when comparing 64 bit vectors

[xry111 at mengyan1223 dot wang]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762

--- Comment #4 from Xi Ruoyao <xry111 at mengyan1223 dot wang> ---
Patch proposed: https://gcc.gnu.org/pipermail/gcc-patches/2021-June/573213.html

[Bug target/100762] [mips+msa] ICE when comparing 64 bit vectors

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100762

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Xi Ruoyao <xry111@gcc.gnu.org>:

https://gcc.gnu.org/g:82625a42e652d52fc6bbe6070f8d0589d5e0c8ad

commit r12-2183-g82625a42e652d52fc6bbe6070f8d0589d5e0c8ad
Author: Xi Ruoyao <xry111@mengyan1223.wang>
Date:   Fri Jun 18 20:11:42 2021 +0800

    mips: check MSA support for vector modes [PR100760,PR100761,PR100762]

    Check if the vector mode is really supported by MSA in certain cases,
    instead of testing ISA_HAS_MSA.  Simply testing ISA_HAS_MSA can cause
    ICE when MSA is enabled besides other MIPS SIMD extensions (notably,
    Loongson MMI).

    gcc/

            PR target/100760
            PR target/100761
            PR target/100762
            * config/mips/mips.c (mips_const_insns): Use MSA_SUPPORTED_MODE_P
            instead of ISA_HAS_MSA.
            (mips_expand_vec_unpack): Likewise.
            (mips_expand_vector_init): Likewise.

    gcc/testsuite/

            PR target/100760
            PR target/100761
            PR target/100762
            * gcc.target/mips/pr100760.c: New test.
            * gcc.target/mips/pr100761.c: New test.
            * gcc.target/mips/pr100762.c: New test.