[Bug target/101248] New: [AVX512] The upper bits of FIXUPIMMS{S,D} should come from src1 not dest.

["crazylht at gmail dot com" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101248

            Bug ID: 101248
           Summary: [AVX512]  The upper bits of FIXUPIMMS{S,D} should come
                    from src1 not dest.
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Keywords: wrong-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: crazylht at gmail dot com
  Target Milestone: ---
            Target: x86_64-*-* i?86-*-*

currently the pattern is defined as

(define_insn "avx512f_sfixupimm<mode>_mask<round_saeonly_name>"
  [(set (match_operand:VF_128 0 "register_operand" "=v")
        (vec_merge:VF_128
          (vec_merge:VF_128
            (unspec:VF_128
               [(match_operand:VF_128 1 "register_operand" "0")
                (match_operand:VF_128 2 "register_operand" "v")
                (match_operand:<sseintvecmode> 3
"<round_saeonly_nimm_scalar_predicate>" "<round_saeonly_constraint>")
                (match_operand:SI 4 "const_0_to_255_operand")]
               UNSPEC_FIXUPIMM)
            (match_dup 2)
            (const_int 1))
          (match_dup 1)
          (match_operand:<avx512fmaskmode> 5 "register_operand" "Yk")))]
  "TARGET_AVX512F"
  "vfixupimm<ssescalarmodesuffix>\t{%4, <round_saeonly_op6>%3, %2,
%0%{%5%}|%0%{%5%}, %2, %<iptr>3<round_saeonly_op6>, %4}";
  [(set_attr "prefix" "evex")
   (set_attr "mode" "<ssescalarmode>")])

when mask is 1, current GCC will optimize

        movl    $-1, %eax
        kmovw   %eax, %k2
        vfixupimmpd     $0, %xmm2, %xmm1, %xmm0{%k2}
to
        vfixupimmsd     $0, %xmm3, %xmm1, %xmm0

But the upper 32 bits of vfixupimmsd should come from src1 not dest which means
the upper optimization is wrong.