[Bug tree-optimization/102393] New: Failure to optimize 2 8-bit stores into a single 16-bit store

[Bug tree-optimization/102393] New: Failure to optimize 2 8-bit stores into a single 16-bit store

[gabravier at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102393

            Bug ID: 102393
           Summary: Failure to optimize 2 8-bit stores into a single
                    16-bit store
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: gabravier at gmail dot com
  Target Milestone: ---

#include <stdint.h>

void HeaderWriteU16LE(int offset, uint16_t value, uint8_t *RomHeader)
{
    RomHeader[offset] = value;
    RomHeader[offset + 1] = value >> 8;
}

Non-withstanding aliasing, this can be optimized to `*(uint16_t *)(RomHeader +
offset) = value`. This transformation is done by LLVM, but not by GCC.

Sample AMD64 output for this from GCC:

HeaderWriteU16LE:
  movsx rdi, edi
  mov eax, esi
  mov BYTE PTR [rdx+rdi], sil
  mov BYTE PTR [rdx+1+rdi], ah
  ret

And from LLVM:

HeaderWriteU16LE:
  movsxd rax, edi
  mov word ptr [rdx + rax], si
  ret

PS: The equivalent pattern for 4 8-bit stores gets optimized into a single
32-bit store.

[Bug tree-optimization/102393] Failure to optimize 2 8-bit stores into a single 16-bit store

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102393

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2021-09-18
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
           See Also|                            |https://gcc.gnu.org/bugzill
                   |                            |a/show_bug.cgi?id=102391
           Severity|normal                      |enhancement

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Really the same issue as PR 102391 bug on the store side rather than the load
side.

[Bug tree-optimization/102393] Failure to optimize 2 8-bit stores into a single 16-bit store

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102393

--- Comment #2 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
that is offset = 0; works.

[Bug tree-optimization/102393] Failure to optimize 2 8-bit stores into a single 16-bit store

[gabravier at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102393

--- Comment #3 from Gabriel Ravier <gabravier at gmail dot com> ---
It seems odd that the equivalent 32-bit pattern, i.e. this:

void HeaderWriteU32LE(int offset, uint32_t value, uint8_t *RomHeader)
{
    RomHeader[offset] = value;
    RomHeader[offset + 1] = value >> 8;
    RomHeader[offset + 2] = value >> 16;
    RomHeader[offset + 3] = value >> 24;
}

is optimized to a single store, though, even though the 32-bit pattern for PR
102391 doesn't. It's why I made this a separate bug report, as I thought it
indicated a likely difference in the cause of the bug.

[Bug tree-optimization/102393] Failure to optimize 2 8-bit stores into a single 16-bit store

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=102393

--- Comment #4 from Richard Biener <rguenth at gcc dot gnu.org> ---
SLSR might come to the rescue eventually but same as the other PR,
store-merging doesn't perform any advanced DR analysis.