[Bug target/103775] New: [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[Bug target/103775] New: [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

            Bug ID: 103775
           Summary: [12 Regression] Assembler messages: Warning:
                    unpredictable transfer with writeback -- `ldrb
                    w0,[x0,16]!'
           Product: gcc
           Version: 12.0
            Status: UNCONFIRMED
          Keywords: wrong-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: aarch64-unknown-linux-gnu

Created attachment 52035
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52035&action=edit
reduced testcase

According to what I could find:

ARM DDI 0487G.b (ID072021)
K1.2.16
CONSTRAINED UNPREDICTABLE behavior for A64 instructions

the behavior of the generated instruction is not guaranteed to be what the
compiler might expected.

Compiler output:
$ aarch64-unknown-linux-gnu-gcc -Og -fno-forward-propagate -free testcase.c -c
/tmp/ccOyWfMV.s: Assembler messages:
/tmp/ccOyWfMV.s:11: Warning: unpredictable transfer with writeback -- `ldrb
w0,[x0,16]!'

$ aarch64-unknown-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-aarch64/bin/aarch64-unknown-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r12-6072-20211220084313-g8d1e342b4af-checking-yes-rtl-df-extra-aarch64/bin/../libexec/gcc/aarch64-unknown-linux-gnu/12.0.0/lto-wrapper
Target: aarch64-unknown-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--with-cloog --with-ppl --with-isl
--with-sysroot=/usr/aarch64-unknown-linux-gnu --build=x86_64-pc-linux-gnu
--host=x86_64-pc-linux-gnu --target=aarch64-unknown-linux-gnu
--with-ld=/usr/bin/aarch64-unknown-linux-gnu-ld
--with-as=/usr/bin/aarch64-unknown-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r12-6072-20211220084313-g8d1e342b4af-checking-yes-rtl-df-extra-aarch64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 12.0.0 20211220 (experimental) (GCC)

[Bug target/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |12.0
           Keywords|                            |assemble-failure

[Bug target/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Zdenek Sojka <zsojka at seznam dot cz> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Keywords|                            |ice-on-valid-code

--- Comment #1 from Zdenek Sojka <zsojka at seznam dot cz> ---
With slightly different flags, this ICEs instead:
$ aarch64-unknown-linux-gnu-gcc -Og -fno-forward-propagate -free -g testcase.c
during RTL pass: vartrack
testcase.c: In function 'foo':
testcase.c:9:1: internal compiler error: in cselib_record_set, at cselib.c:2617
    9 | }
      | ^
0x6d97bc cselib_record_set
        /repo/gcc-trunk/gcc/cselib.c:2617
0xc7c676 cselib_record_set
        /repo/gcc-trunk/gcc/cselib.c:2941
0xc7c676 cselib_record_sets
        /repo/gcc-trunk/gcc/cselib.c:2946
0xc7d7aa cselib_process_insn(rtx_insn*)
        /repo/gcc-trunk/gcc/cselib.c:3069
0x1458719 vt_initialize
        /repo/gcc-trunk/gcc/var-tracking.c:10284
0x145edb2 variable_tracking_main_1
        /repo/gcc-trunk/gcc/var-tracking.c:10512
0x145ef5b variable_tracking_main()
        /repo/gcc-trunk/gcc/var-tracking.c:10565
0x145ef5b execute
        /repo/gcc-trunk/gcc/var-tracking.c:10602
Please submit a full bug report,
with preprocessed source if appropriate.
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

[Bug target/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

--- Comment #2 from Zdenek Sojka <zsojka at seznam dot cz> ---
(In reply to Zdenek Sojka from comment #1)
> With slightly different flags, this ICEs instead:

Actually, just add -g

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
          Component|target                      |rtl-optimization
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW
   Last reconfirmed|                            |2021-12-20
           Keywords|ice-on-valid-code           |
                 CC|                            |pinskia at gcc dot gnu.org

--- Comment #3 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
(insn 12 9 13 2 (set (reg:SI 93 [ _2 ])
        (zero_extend:SI (mem/c:QI (plus:DI (reg/f:DI 65 ap)
                    (const_int 16 [0x10])) [1 u128_1+0 S1 A128])))
"/app/example.cpp":5:35 117 {*zero_extendqisi2_aarch64}
     (nil))


Auto-increment then turns it into:

(insn 39 9 12 2 (set (reg/f:DI 114)
        (reg/f:DI 65 ap)) "/app/example.cpp":5:35 -1
     (nil))
(insn 12 39 13 2 (set (reg:SI 93 [ _2 ])
        (zero_extend:SI (mem/c:QI (pre_modify:DI (reg/f:DI 114)
                    (plus:DI (reg/f:DI 114)
                        (const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"/app/example.cpp":5:35 117 {*zero_extendqisi2_aarch64}
     (expr_list:REG_INC (reg/f:DI 114)
        (nil)))


But this does not make sense as the result of the modify is not used
afterwards.
found pre add(17) r[115]=r[65]+20
   16: r114:DI=ap:DI+0x10
      REG_UNUSED r114:DI
   15: r95:SI=r113:DI#0
      REG_DEAD r113:DI
   14: r113:DI=clrsb(r112:DI)
      REG_DEAD r112:DI
   13: r112:DI=zero_extend(r93:SI)
   12: r93:SI=zero_extend([ap:DI+0x10])
   12: r93:SI=zero_extend([ap:DI+0x10])
found mem(12) *(r[65]+16)
   16: r114:DI=ap:DI+0x10
      REG_UNUSED r114:DI
found post add(16) r[114]=r[65]+16



hmm before auto-increment:
(insn 16 15 17 2 (set (reg/f:DI 114)
        (plus:DI (reg/f:DI 65 ap)
            (const_int 16 [0x10]))) "/app/example.cpp":6:3 124
{*adddi3_aarch64}
     (nil))
(insn 17 16 18 2 (set (reg/f:DI 115)
        (plus:DI (reg/f:DI 65 ap)
            (const_int 20 [0x14]))) "/app/example.cpp":6:3 124
{*adddi3_aarch64}
     (expr_list:REG_DEAD (reg/f:DI 114)
        (nil)))

114 is dead even before this.

Oh this is because at -Og we are not running DCE. I think there is some DF not
being updated before auto-increment too.

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[acoplan at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Alex Coplan <acoplan at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |acoplan at gcc dot gnu.org

--- Comment #4 from Alex Coplan <acoplan at gcc dot gnu.org> ---
FWIW both the ICE and assembly failure started with
r12-3252-gcad36f38576a6a781e3c62ab061c68f5b8dab13a:

commit cad36f38576a6a781e3c62ab061c68f5b8dab13a
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Tue Aug 31 11:45:07 2021

    Preserve SUBREG_PROMOTED_VAR_P on (extend:HI (subreg/s:QI (reg:SI))).

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

--- Comment #5 from Richard Biener <rguenth at gcc dot gnu.org> ---
That change probably just made the latent issue trigger.

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Priority|P3                          |P1

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |jakub at gcc dot gnu.org

--- Comment #6 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
I think this is a REE bug.
However inefficient (but we get that because of -Og and
-fno-forward-propagate),
(insn 12 39 13 2 (set (reg:SI 1 x1 [orig:93 _2 ] [93])
        (zero_extend:SI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
                    (plus:DI (reg/f:DI 0 x0 [114])
                        (const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 117 {*zero_extendqisi2_aarch64}
     (expr_list:REG_INC (reg/f:DI 0 x0 [114])
        (nil)))
(insn 13 12 14 2 (set (reg:DI 0 x0 [orig:112 _2 ] [112])
        (zero_extend:DI (reg:SI 1 x1 [orig:93 _2 ] [93]))) "pr103775.c":5:16
111 {*zero_extendsidi2_aarch64}
     (nil))
is valid, but turning that into:
(insn 12 39 44 2 (set (reg:DI 0 x0)
        (zero_extend:DI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
                    (plus:DI (reg/f:DI 0 x0 [114])
                        (const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 119 {*zero_extendqidi2_aarch64}
     (expr_list:REG_INC (reg/f:DI 0 x0 [114])
        (nil)))
(insn 44 12 14 2 (set (reg:DI 1 x1)
        (reg:DI 0 x0)) "pr103775.c":5:35 -1
     (nil))
is invalid, as one instruction can't set the same register multiple times.

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |ebotcazou at gcc dot gnu.org,
                   |                            |rguenth at gcc dot gnu.org

--- Comment #7 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Though, maybe it shouldn't be the duty of every pass to check this and instead
something like insn_invalid_p should reject those?

If so, shall we worry about that just when reload_completed?

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

--- Comment #8 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Created attachment 52682
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52682&action=edit
gcc12-pr103775.patch

This untested patch seems to work.

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[ebotcazou at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

--- Comment #9 from Eric Botcazou <ebotcazou at gcc dot gnu.org> ---
> This untested patch seems to work.

This looks sensible to me, maybe move the new code up to before the constraint
check since it is always run.

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

--- Comment #10 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Jakub Jelinek <jakub@gcc.gnu.org>:

https://gcc.gnu.org/g:6459e6537632bc06e04e6011ca7fb6488f0e8e7d

commit r12-7832-g6459e6537632bc06e04e6011ca7fb6488f0e8e7d
Author: Jakub Jelinek <jakub@redhat.com>
Date:   Sat Mar 26 16:21:36 2022 +0100

    ecog: Return 1 from insn_invalid_p if REG_INC reg overlaps some stored reg
[PR103775]

    The following testcase ICEs on aarch64-linux with -g and
    assembles with a warning otherwise, because it emits
    ldrb w0,[x0,16]!
    instruction which sets the x0 register multiple times.
    Due to disabled DCE (from -Og) we end up before REE with:
    (insn 12 39 13 2 (set (reg:SI 1 x1 [orig:93 _2 ] [93])
            (zero_extend:SI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
                        (plus:DI (reg/f:DI 0 x0 [114])
                            (const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 117 {*zero_extendqisi2_aarch64}
         (expr_list:REG_INC (reg/f:DI 0 x0 [114])
            (nil)))
    (insn 13 12 14 2 (set (reg:DI 0 x0 [orig:112 _2 ] [112])
            (zero_extend:DI (reg:SI 1 x1 [orig:93 _2 ] [93])))
"pr103775.c":5:16 111 {*zero_extendsidi2_aarch64}
         (nil))
    which is valid but not exactly efficient as x0 is dead after the
    insn that auto-increments it.  REE turns it into:
    (insn 12 39 44 2 (set (reg:DI 0 x0)
            (zero_extend:DI (mem/c:QI (pre_modify:DI (reg/f:DI 0 x0 [114])
                        (plus:DI (reg/f:DI 0 x0 [114])
                            (const_int 16 [0x10]))) [1 u128_1+0 S1 A128])))
"pr103775.c":5:35 119 {*zero_extendqidi2_aarch64}
         (expr_list:REG_INC (reg/f:DI 0 x0 [114])
            (nil)))
    (insn 44 12 14 2 (set (reg:DI 1 x1)
            (reg:DI 0 x0)) "pr103775.c":5:35 -1
         (nil))
    which is invalid because it sets x0 multiple times, one
    in SET_DEST of the PATTERN and once in PRE_MODIFY.
    As perhaps other passes than REE might suffer from it, IMHO it is better
    to reject this during change validation.

    2022-03-26  Jakub Jelinek  <jakub@redhat.com>

            PR rtl-optimization/103775
            * recog.cc (check_invalid_inc_dec): New function.
            (insn_invalid_p): Return 1 if REG_INC operand overlaps
            any stored REGs.

            * gcc.dg/pr103775.c: New test.

[Bug rtl-optimization/103775] [12 Regression] Assembler messages: Warning: unpredictable transfer with writeback -- `ldrb w0,[x0,16]!'

[jakub at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=103775

Jakub Jelinek <jakub at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|NEW                         |RESOLVED
         Resolution|---                         |FIXED

--- Comment #11 from Jakub Jelinek <jakub at gcc dot gnu.org> ---
Fixed.