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From: "lili.cui at intel dot com" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/104271] [12 Regression] 538.imagick_r run-time at -Ofast -march=native regressed by 26% on Intel Cascade Lake server CPU Date: Fri, 15 Apr 2022 11:04:42 +0000 [thread overview] Message-ID: <bug-104271-4-KcJ1jOguE2@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-104271-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104271 --- Comment #9 from cuilili <lili.cui at intel dot com> --- Really appreciate for your reply, I debugged SRA pass with the small testcase and found that SRA dose not handle this situation. SRA cannot split callee's first parameter for "Do not decompose non-BLKmode parameters in a way that would create a BLKmode parameter. Especially for pass-by-reference (hence, pointer type parameters), it's not worth it." Before inline: For caller store-1 : 128 bits store of struct "a" (it is an implicit store during IPA pass, the store can only be found after a certain pass.) For callee load-1 : 128 bits load of struct "a" for operation "c->a=(*a)" store-2: 128 bits store of struct "c->a" for operation "c->a=(*a)" load-2 : 4 * 32 bits load for c->a.f1, c->a.f2, c->a.f3 and c->a.f4. (because the store-2 using vector register to store, we cannot use the register directly here.) After inline: For caller None. For callee store-2 : 128 bits store of struct c->a for operation "c->a=(*a)" -------------------------------------------------------- int callee (struct A *a, struct C *c) { c->a=(*a); if ((c->b + 7) & 17) { c->a.f1 = c->a.f2 + c->a.f3; c->a.f2 = c->a.f2 - c->a.f3; c->a.f3 = c->a.f2 + c->a.f3; c->a.f4 = c->a.f2 - c->a.f3; c->b = c->a.f2 + c->a.f4; return 0; } return 1; } int caller (int d, struct C *c) { struct A a; a.f1 = 1 + d; a.f2 = 2; a.f3 = 12 + d; a.f4 = 68 + d; if (d > 0) return callee (&a, c); else return 1; } ------------------------------------------------- In 538.imagic_r(c_ray also has the similar code), if we inline the hot function, the redundant store and load structure's size is 256 bits (4 elements of size 64 bits), which can eliminates one 256-bit store, one 256-bit load, and four 64-bit loads. can I do it like this? Computes the total size of all callee arguments that can eliminate redundant loads and stores. Thanks!
next prev parent reply other threads:[~2022-04-15 11:04 UTC|newest] Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-01-28 17:12 [Bug target/104271] New: " jamborm at gcc dot gnu.org 2022-01-31 8:11 ` [Bug target/104271] [12 Regression] " rguenth at gcc dot gnu.org 2022-01-31 9:08 ` marxin at gcc dot gnu.org 2022-02-07 1:31 ` crazylht at gmail dot com 2022-02-07 18:10 ` jamborm at gcc dot gnu.org 2022-02-08 2:49 ` crazylht at gmail dot com 2022-03-23 12:37 ` rguenth at gcc dot gnu.org 2022-03-23 16:17 ` jamborm at gcc dot gnu.org 2022-03-24 8:34 ` lili.cui at intel dot com 2022-03-29 6:48 ` lili.cui at intel dot com 2022-03-29 10:39 ` rguenth at gcc dot gnu.org 2022-04-15 11:04 ` lili.cui at intel dot com [this message] 2022-05-06 8:32 ` [Bug target/104271] [12/13 " jakub at gcc dot gnu.org 2022-11-28 3:24 ` lili.cui at intel dot com 2023-05-08 12:23 ` [Bug target/104271] [12 " rguenth at gcc dot gnu.org 2023-06-07 2:07 ` lili.cui at intel dot com 2023-06-07 7:02 ` sjames at gcc dot gnu.org 2023-06-07 7:14 ` rguenth at gcc dot gnu.org
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