[Bug tree-optimization/105090] New: BFI instructions are not generated on arm-none-eabi-g++

[Bug tree-optimization/105090] New: BFI instructions are not generated on arm-none-eabi-g++

[andrew.jeddeloh at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

            Bug ID: 105090
           Summary: BFI instructions are not generated on
                    arm-none-eabi-g++
           Product: gcc
           Version: 11.2.1
            Status: UNCONFIRMED
          Keywords: missed-optimization
          Severity: normal
          Priority: P3
         Component: tree-optimization
          Assignee: unassigned at gcc dot gnu.org
          Reporter: andrew.jeddeloh at gmail dot com
  Target Milestone: ---

Created attachment 52704
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=52704&action=edit
.ii file for test case

The following code could generate a BFI instruction but does not. Clang will
generate one.

#include <stdint.h>
uint32_t emplace(uint32_t into, uint32_t what) {
        constexpr uint32_t shift = 5;
        constexpr uint32_t width = 4;
        constexpr uint32_t mask = ((1 << width) - 1) << shift;
        return (into & ~mask) | ((what << shift) & mask);
}

you can write equivalent C code and get the same problem.

gcc 8.5 and clang generate:
        bfi     r0, r1, #5, #4
        bx      lr

Whereas 9.3+ generates:
        lsls    r1, r1, #5
        and     r1, r1, #480
        bic     r0, r0, #480
        orrs    r0, r0, r1
        bx      lr

These are compiled with arm-none-eabi-gcc -Wall -Wextra -mcpu=cortex-m4 -O3 -c
Compile output is silent. Attached is .ii
I also tried O2, O1 and Os.

See problem with godbolt: https://godbolt.org/z/57h5Yd9ov

A lot of embedded development involves setting certain chunks of memory mapped
registers like this and would greatly benefit from this being fixed. 

GCC version info from my computer:
Using built-in specs.
COLLECT_GCC=arm-none-eabi-gcc
COLLECT_LTO_WRAPPER=/usr/lib/gcc/arm-none-eabi/11.2.0/lto-wrapper
Target: arm-none-eabi
Configured with: /build/arm-none-eabi-gcc/src/gcc-11.2.0/configure
--target=arm-none-eabi --prefix=/usr --with-sysroot=/usr/arm-none-eabi
--with-native-system-header-dir=/include --libexecdir=/usr/lib
--enable-languages=c,c++ --enable-plugins --disable-decimal-float
--disable-libffi --disable-libgomp --disable-libmudflap --disable-libquadmath
--disable-libssp --disable-libstdcxx-pch --disable-nls --disable-shared
--disable-threads --disable-tls --with-gnu-as --with-gnu-ld --with-system-zlib
--with-newlib --with-headers=/usr/arm-none-eabi/include
--with-python-dir=share/gcc-arm-none-eabi --with-gmp --with-mpfr --with-mpc
--with-isl --with-libelf --enable-gnu-indirect-function
--with-host-libstdcxx='-static-libgcc -Wl,-Bstatic,-lstdc++,-Bdynamic -lm'
--with-pkgversion='Arch Repository' --with-bugurl=https://bugs.archlinux.org/
--with-multilib-list=rmprofile
Thread model: single
Supported LTO compression algorithms: zlib zstd
gcc version 11.2.0 (Arch Repository)



Possibly related but I'm not sure:
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85628

[Bug tree-optimization/105090] BFI instructions are not generated on arm-none-eabi-g++

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

--- Comment #1 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
This was fallout from some changes made internally in the compiler in around
the gcc-10 timeframe, but it really just exposed a more general problem with
the failure to detect opportunities to use bitfield expressions.

TLDR;

We need to recognize that the pattern:

(set (reg:SI 119)
    (ior:SI (and:SI (reg:SI 123)
            (const_int -481 [0xfffffffffffffe1f]))
        (and:SI (ashift:SI (reg:SI 124)
                (const_int 5 [0x5]))
            (const_int 480 [0x1e0]))))

Is in fact a direct match for a bitfield insert instruction and handle it
accordingly.

[Bug tree-optimization/105090] BFI instructions are not generated on arm-none-eabi-g++

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2022-03-29
     Ever confirmed|0                           |1
             Status|UNCONFIRMED                 |NEW

--- Comment #2 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
The PR you cite is for aarch64, so while very similar is for a separate target.

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |rearnsha at gcc dot gnu.org
             Status|NEW                         |ASSIGNED

--- Comment #3 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
I have patches for this, but they'll have to wait for GCC-13 development to
start.

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

[andrew.jeddeloh at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

--- Comment #4 from Andrew Jeddeloh <andrew.jeddeloh at gmail dot com> ---
Hi, I wanted to follow up now that GCC 13 development has opened up. Any news
on including it?

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Richard Earnshaw <rearnsha@gcc.gnu.org>:

https://gcc.gnu.org/g:2005b9b888eeac078f2524b1521885f4b5453894

commit r13-1006-g2005b9b888eeac078f2524b1521885f4b5453894
Author: Richard Earnshaw <rearnsha@arm.com>
Date:   Tue Jun 7 12:09:47 2022 +0100

    arm: Improve code generation for BFI and BFC [PR105090]

    This patch, in response to PR105090, makes some general improvements
    to the code generation when BFI and BFC instructions are available.
    Firstly we handle more cases where the RTL does not generate an INSV
    operation due to a lack of a tie between the input and output, but we
    nevertheless need to emit BFI later on; we handle this by requiring
    the register allocator to tie the operands.  Secondly we handle some
    cases where we were previously emitting BFC, but AND with an immediate
    would be better; we do this by converting all BFC patterns into AND
    using a split pattern.  And finally, we handle some cases where
    previously we would emit multiple BIC operations to clear a value, but
    could instead use a single BFC instruction.

    BFC and BFI express the mask as a pair of values, one for the number
    of bits to clear and another for the location of the least significant
    bit.  We handle these with a single new output modifier letter that
    causes both values to be printed; we use an 'inverted' value so that
    it can be used directly with the constant used in an AND rtl
    construct.  We've run out of 'new' letters, so to do this we re-use
    one of the long-obsoleted Maverick output modifiers.

    gcc/ChangeLog:

            PR target/105090
            * config/arm/arm.cc (arm_bfi_1_p): New function.
            (arm_bfi_p): New function.
            (arm_rtx_costs_internal): Add costs for BFI idioms.
            (arm_print_operand [case 'V']): Format output for BFI/BFC masks.
            * config/arm/constraints.md (Dj): New constraint.
            * config/arm/arm.md (arm_andsi3_insn): Add alternative to use BFC.
            (insv_zero): Convert to an insn with a split.
            (*bfi, *bfi_alt1, *bfi_alt2, *bfi_alt3): New patterns.

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
         Resolution|---                         |FIXED
             Status|ASSIGNED                    |RESOLVED

--- Comment #6 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
Fixed on master

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |andij.cr at gmail dot com

--- Comment #7 from Richard Earnshaw <rearnsha at gcc dot gnu.org> ---
*** Bug 91674 has been marked as a duplicate of this bug. ***

[Bug target/105090] BFI instructions are not generated on arm-none-eabi-g++

[rearnsha at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105090

Richard Earnshaw <rearnsha at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Target Milestone|---                         |13.0