[Bug target/105854] New: ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[Bug target/105854] New: ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[zsojka at seznam dot cz]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

            Bug ID: 105854
           Summary: ICE: in extract_constrain_insn, at recog.cc:2692 (insn
                    does not satisfy its constraints: sse2_lshrv1ti3)
           Product: gcc
           Version: 13.0
            Status: UNCONFIRMED
          Keywords: ice-on-valid-code
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: zsojka at seznam dot cz
  Target Milestone: ---
              Host: x86_64-pc-linux-gnu
            Target: x86_64-pc-linux-gnu

Created attachment 53087
  --> https://gcc.gnu.org/bugzilla/attachment.cgi?id=53087&action=edit
reduced testcase

Compiler output:
$ x86_64-pc-linux-gnu-gcc -O -fcaller-saves -mavx512vl testcase.c 
testcase.c: In function 'foo':
testcase.c:29:1: error: insn does not satisfy its constraints:
   29 | }
      | ^
(insn 326 325 321 2 (set (reg:V1TI 52 xmm16 [128])
        (lshiftrt:V1TI (reg:V1TI 52 xmm16 [128])
            (const_int 0 [0]))) "testcase.c":18:14 6365 {sse2_lshrv1ti3}
     (nil))
during RTL pass: cprop_hardreg
testcase.c:29:1: internal compiler error: in extract_constrain_insn, at
recog.cc:2692
0x775bee _fatal_insn(char const*, rtx_def const*, char const*, int, char
const*)
        /repo/gcc-trunk/gcc/rtl-error.cc:108
0x775c7b _fatal_insn_not_found(rtx_def const*, char const*, int, char const*)
        /repo/gcc-trunk/gcc/rtl-error.cc:118
0x7647b9 extract_constrain_insn(rtx_insn*)
        /repo/gcc-trunk/gcc/recog.cc:2692
0x130f4d4 copyprop_hardreg_forward_1
        /repo/gcc-trunk/gcc/regcprop.cc:826
0x13108b3 execute
        /repo/gcc-trunk/gcc/regcprop.cc:1406
Please submit a full bug report, with preprocessed source (by using
-freport-bug).
Please include the complete backtrace with any bug report.
See <https://gcc.gnu.org/bugs/> for instructions.

$ x86_64-pc-linux-gnu-gcc -v
Using built-in specs.
COLLECT_GCC=/repo/gcc-trunk/binary-latest-amd64/bin/x86_64-pc-linux-gnu-gcc
COLLECT_LTO_WRAPPER=/repo/gcc-trunk/binary-trunk-r13-992-20220605001627-gad6919374be-checking-yes-rtl-df-extra-nobootstrap-amd64/bin/../libexec/gcc/x86_64-pc-linux-gnu/13.0.0/lto-wrapper
Target: x86_64-pc-linux-gnu
Configured with: /repo/gcc-trunk//configure --enable-languages=c,c++
--enable-valgrind-annotations --disable-nls --enable-checking=yes,rtl,df,extra
--disable-bootstrap --with-cloog --with-ppl --with-isl
--build=x86_64-pc-linux-gnu --host=x86_64-pc-linux-gnu
--target=x86_64-pc-linux-gnu --with-ld=/usr/bin/x86_64-pc-linux-gnu-ld
--with-as=/usr/bin/x86_64-pc-linux-gnu-as --disable-libstdcxx-pch
--prefix=/repo/gcc-trunk//binary-trunk-r13-992-20220605001627-gad6919374be-checking-yes-rtl-df-extra-nobootstrap-amd64
Thread model: posix
Supported LTO compression algorithms: zlib zstd
gcc version 13.0.0 20220605 (experimental) (GCC)

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

Hongtao.liu <crazylht at gmail dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |crazylht at gmail dot com

--- Comment #1 from Hongtao.liu <crazylht at gmail dot com> ---
21114(define_insn_and_split "ssse3_palignrdi"
21115  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
21116        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
21117                    (match_operand:DI 2 "register_mmxmem_operand"
"ym,x,Yv")
21118                    (match_operand:SI 3 "const_0_to_255_mul_8_operand")]
21119                   UNSPEC_PALIGNR))]
21120  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq which
requires AVX512VL & AVX512BW for evex version.

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

--- Comment #2 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:cd22395457f063824c839fd1c0077d15d3dccd6d

commit r13-1005-gcd22395457f063824c839fd1c0077d15d3dccd6d
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Jun 6 13:39:19 2022 +0800

    Fix insn does not satisfy its constraints: sse2_lshrv1ti3

    21114(define_insn_and_split "ssse3_palignrdi"
    21115  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
    21116        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
    21117                    (match_operand:DI 2 "register_mmxmem_operand"
"ym,x,Yv")
    21118                    (match_operand:SI 3
"const_0_to_255_mul_8_operand")]
    21119                   UNSPEC_PALIGNR))]
    21120  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

    Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
    which requires AVX512VL & AVX512BW for evex version.

    gcc/ChangeLog:

            PR target/105854
            * config/i386/sse.md (ssse3_palignrdi): Change alternative 2
            from Yv to Yw.

    gcc/testsuite/ChangeLog:

            * gcc.target/i386/pr105854.c: New test.

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

--- Comment #3 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by hongtao Liu <liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:e4bdeaba6ef8a83877417f7ec172fd8743370284

commit r13-1008-ge4bdeaba6ef8a83877417f7ec172fd8743370284
Author: liuhongt <hongtao.liu@intel.com>
Date:   Wed Jun 8 10:55:32 2022 +0800

    Adjust testcase to avoid compile failure under -m32.

    gcc/testsuite/ChangeLog:

            PR target/105854
            * gcc.target/i386/pr105854.c: Add target int128 and dfp.

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-11 branch has been updated by hongtao Liu
<liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:66b1b04bb59fbafb809bfad945c95888b758e719

commit r11-10053-g66b1b04bb59fbafb809bfad945c95888b758e719
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Jun 6 13:39:19 2022 +0800

    Fix insn does not satisfy its constraints: sse2_lshrv1ti3

    21114(define_insn_and_split "ssse3_palignrdi"
    21115  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
    21116        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
    21117                    (match_operand:DI 2 "register_mmxmem_operand"
"ym,x,Yv")
    21118                    (match_operand:SI 3
"const_0_to_255_mul_8_operand")]
    21119                   UNSPEC_PALIGNR))]
    21120  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

    Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
    which requires AVX512VL & AVX512BW for evex version.

    gcc/ChangeLog:

            PR target/105854
            * config/i386/sse.md (ssse3_palignrdi): Change alternative 2
            from Yv to Yw.

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

--- Comment #5 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The releases/gcc-12 branch has been updated by hongtao Liu
<liuhongt@gcc.gnu.org>:

https://gcc.gnu.org/g:c45a9752f15bbc37d8efda0e29af5a2bfd53729d

commit r12-8462-gc45a9752f15bbc37d8efda0e29af5a2bfd53729d
Author: liuhongt <hongtao.liu@intel.com>
Date:   Mon Jun 6 13:39:19 2022 +0800

    Fix insn does not satisfy its constraints: sse2_lshrv1ti3

    21114(define_insn_and_split "ssse3_palignrdi"
    21115  [(set (match_operand:DI 0 "register_operand" "=y,x,Yv")
    21116        (unspec:DI [(match_operand:DI 1 "register_operand" "0,0,Yv")
    21117                    (match_operand:DI 2 "register_mmxmem_operand"
"ym,x,Yv")
    21118                    (match_operand:SI 3
"const_0_to_255_mul_8_operand")]
    21119                   UNSPEC_PALIGNR))]
    21120  "(TARGET_MMX || TARGET_MMX_WITH_SSE) && TARGET_SSSE3"

    Alternative 2 requires Yw instead of Yv since it's splitted to vpsrldq
    which requires AVX512VL & AVX512BW for evex version.

    gcc/ChangeLog:

            PR target/105854
            * config/i386/sse.md (ssse3_palignrdi): Change alternative 2
            from Yv to Yw.

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[crazylht at gmail dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

--- Comment #6 from Hongtao.liu <crazylht at gmail dot com> ---
Fixed in trunk, GCC12.2 and GCC11.3

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

--- Comment #7 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Roger Sayle <sayle@gcc.gnu.org>:

https://gcc.gnu.org/g:02e2e15ec4b610c0f5c73e1db424b1bbc65dd39a

commit r13-1508-g02e2e15ec4b610c0f5c73e1db424b1bbc65dd39a
Author: Roger Sayle <roger@nextmovesoftware.com>
Date:   Tue Jul 5 18:00:00 2022 +0100

    UNSPEC_PALIGNR optimizations and clean-ups on x86.

    This patch is a follow-up to Hongtao's fix for PR target/105854.  That
    fix is perfectly correct, but the thing that caught my eye was why is
    the compiler generating a shift by zero at all.  Digging deeper it
    turns out that we can easily optimize __builtin_ia32_palignr for
    alignments of 0 and 64 respectively, which may be simplified to moves
    of the highpart and lowpart respectively.

    After adding optimizations to simplify the 64-bit DImode palignr, I
    started to add the corresponding optimizations for vpalignr (i.e.
    128-bit).  The first oddity is that sse.md uses TImode and a special
    SSESCALARMODE iterator, rather than V1TImode, and indeed the comment
    above SSESCALARMODE hints that this should be "dropped in favor of
    VIMAX_AVX2_AVX512BW".  Hence this patch includes the migration of
    <ssse3_avx2>_palignr<mode> to use VIMAX_AVX2_AVX512BW, basically
    using V1TImode instead of TImode for 128-bit palignr.

    This patch has been tested on x86_64-pc-linux-gnu with make bootstrap
    and make -k check, both with and without --target_board=unix{-,32},
    with no new failures.  Ok for mainline?

    2022-07-05  Roger Sayle  <roger@nextmovesoftware.com>
                Hongtao Liu  <hongtao.liu@intel.com>

    gcc/ChangeLog
            * config/i386/i386-builtin.def (__builtin_ia32_palignr128): Change
            CODE_FOR_ssse3_palignrti to CODE_FOR_ssse3_palignrv1ti.
            * config/i386/i386-expand.cc (expand_vec_perm_palignr): Use
V1TImode
            and gen_ssse3_palignv1ti instead of TImode.
            * config/i386/sse.md (SSESCALARMODE): Delete.
            (define_mode_attr ssse3_avx2): Handle V1TImode instead of TImode.
            (<ssse3_avx2>_palignr<mode>): Use VIMAX_AVX2_AVX512BW as a mode
            iterator instead of SSESCALARMODE.
            (ssse3_palignrdi): Optimize cases where operands[3] is 0 or 64,
            using a single move instruction (if required).

    gcc/testsuite/ChangeLog
            * gcc.target/i386/ssse3-palignr-2.c: New test case.

[Bug target/105854] ICE: in extract_constrain_insn, at recog.cc:2692 (insn does not satisfy its constraints: sse2_lshrv1ti3)

[roger at nextmovesoftware dot com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=105854

Roger Sayle <roger at nextmovesoftware dot com> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|UNCONFIRMED                 |RESOLVED
         Resolution|---                         |FIXED
   Target Milestone|---                         |11.4
                 CC|                            |roger at nextmovesoftware dot com

--- Comment #8 from Roger Sayle <roger at nextmovesoftware dot com> ---
As explained by Hongtao in comment #6, this is now fixed.