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From: "cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org> To: gcc-bugs@gcc.gnu.org Subject: [Bug target/106101] [12/13 Regression] ICE in reg_bitfield_target_p since r12-4428-g147ed0184f403b Date: Thu, 25 Aug 2022 12:40:19 +0000 [thread overview] Message-ID: <bug-106101-4-nr7EV8Jz9G@http.gcc.gnu.org/bugzilla/> (raw) In-Reply-To: <bug-106101-4@http.gcc.gnu.org/bugzilla/> https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106101 --- Comment #20 from CVS Commits <cvs-commit at gcc dot gnu.org> --- The master branch has been updated by Andreas Krebbel <krebbel@gcc.gnu.org>: https://gcc.gnu.org/g:585a21bab3ec688c2039bff2922cc372d8558283 commit r13-2201-g585a21bab3ec688c2039bff2922cc372d8558283 Author: Andreas Krebbel <krebbel@linux.ibm.com> Date: Fri Jul 29 09:55:54 2022 +0200 PR 106101: IBM zSystems: Fix strict_low_part problem This avoids generating illegal (strict_low_part (reg ...)) RTXs. This required two changes: 1. Do not use gen_lowpart to generate the inner expression of a STRICT_LOW_PART. gen_lowpart might fold the SUBREG either because there is already a paradoxical subreg or because it can directly be applied to the register. A new wrapper function makes sure that we always end up having an actual SUBREG. 2. Change the movstrict patterns to enforce a SUBREG as inner operand of the STRICT_LOW_PARTs. The new predicate introduced for the destination operand requires a SUBREG expression with a register_operand as inner operand. However, since reload strips away the majority of the SUBREGs we have to accept single registers as well once we reach reload. Bootstrapped and regression tested on IBM zSystems 64 bit. gcc/ChangeLog: PR target/106101 * config/s390/predicates.md (subreg_register_operand): New predicate. * config/s390/s390-protos.h (s390_gen_lowpart_subreg): New function prototype. * config/s390/s390.cc (s390_gen_lowpart_subreg): New function. (s390_expand_insv): Use s390_gen_lowpart_subreg instead of gen_lowpart. * config/s390/s390.md ("*get_tp_64", "*zero_extendhisi2_31") ("*zero_extendqisi2_31", "*zero_extendqihi2_31"): Likewise. ("movstrictqi", "movstricthi", "movstrictsi"): Use the subreg_register_operand predicate instead of register_operand. gcc/testsuite/ChangeLog: PR target/106101 * gcc.c-torture/compile/pr106101.c: New test.
next prev parent reply other threads:[~2022-08-25 12:40 UTC|newest] Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-06-27 9:22 [Bug rtl-optimization/106101] New: [12/13 Regression] ICE in reg_bitfield_target_p rguenth at gcc dot gnu.org 2022-06-27 9:22 ` [Bug rtl-optimization/106101] " rguenth at gcc dot gnu.org 2022-06-27 9:22 ` rguenth at gcc dot gnu.org 2022-06-27 9:26 ` rguenth at gcc dot gnu.org 2022-06-27 15:10 ` segher at gcc dot gnu.org 2022-06-28 6:57 ` [Bug target/106101] " rguenth at gcc dot gnu.org 2022-06-28 15:03 ` segher at gcc dot gnu.org 2022-06-28 16:58 ` segher at gcc dot gnu.org 2022-06-29 9:11 ` rguenth at gcc dot gnu.org 2022-06-29 15:48 ` segher at gcc dot gnu.org 2022-07-08 13:56 ` [Bug target/106101] [12/13 Regression] ICE in reg_bitfield_target_p since r12-4428-g147ed0184f403b marxin at gcc dot gnu.org 2022-07-14 10:02 ` krebbel at gcc dot gnu.org 2022-07-19 11:53 ` krebbel at gcc dot gnu.org 2022-08-24 6:46 ` krebbel at gcc dot gnu.org 2022-08-24 11:57 ` segher at gcc dot gnu.org 2022-08-25 12:40 ` cvs-commit at gcc dot gnu.org [this message] 2022-08-25 13:02 ` krebbel at gcc dot gnu.org 2022-08-25 13:55 ` krebbel at gcc dot gnu.org 2022-08-25 15:03 ` segher at gcc dot gnu.org 2023-01-17 15:25 ` [Bug target/106101] [12 " rguenth at gcc dot gnu.org 2023-01-17 15:26 ` rguenth at gcc dot gnu.org 2023-01-23 7:58 ` cvs-commit at gcc dot gnu.org 2023-03-01 13:28 ` rguenth at gcc dot gnu.org 2023-10-10 14:29 ` fw at gcc dot gnu.org 2023-10-10 17:36 ` pinskia at gcc dot gnu.org 2023-10-10 17:39 ` pinskia at gcc dot gnu.org 2023-10-11 6:46 ` fw at gcc dot gnu.org
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