[Bug c/106195] New: RFE: Split -msse into -msse and -fenable-intrinsics

[Bug c/106195] New: RFE: Split -msse into -msse and -fenable-intrinsics

[jengelh at inai dot de]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106195

            Bug ID: 106195
           Summary: RFE: Split -msse into -msse and -fenable-intrinsics
           Product: gcc
           Version: 12.1.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: c
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jengelh at inai dot de
  Target Milestone: ---

Some libraries may use cpuid to runtime-test for SSE availability, yet their
authors may, intentionally or not, cause a profound lack of #ifdef __SSE__
guards around sections that do use _mm_* functions. The problem is not tied to
SSE specifically; any CPU extension may be affected. Consider this source code:


#include <string>
#include <cpuid.h>
#include <xmmintrin.h>
struct ADLConfig {
        int cc=6,eid=0,bank=14,vol=0,pcm=0,pan=1,ban2k=false;
        std::string cbank;
};
ADLConfig adlConfig; // generates MOVAPS under -O2 -msse
int main()
{
        long x=0,a=0,b=0,c=0,d=0;
        __cpuid(x,a,b,c,d);
        if (x) {
                __m128 a,b;
                _mm_add_ss(a,b);
        } else {
                // <non-SIMD variant>
        }
}


Without -msse, compilation of the snippet fails.
With -msse, the program builds but then won't run on SSE-less CPUs, because SSE
is emitted in a place where it's undesired - basically the only places where it
*is* desired is the _mm calls. There should be a better option than to find and
edit all _mm callsites and add #ifdef __SSE__.
If only I could tell the compiler "-mno-sse -fenable-sse-intrinsics" or so..

[Bug target/106195] RFE: Split -msse into -msse and -fenable-intrinsics

[pinskia at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106195

Andrew Pinski <pinskia at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Severity|normal                      |enhancement
          Component|c                           |target

--- Comment #1 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
I doubt we want to do this because it is hard to do with the current gcc
infrastructure. Plus there are other options like using the attribute target or
optimize instead to turn off that.


Oh there might be a dup of this already.

[Bug target/106195] RFE: Split -msse into -msse and -fenable-intrinsics

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106195

Richard Biener <rguenth at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Target|                            |x86_64-*-*

--- Comment #2 from Richard Biener <rguenth at gcc dot gnu.org> ---
The CPU-id switched code needs to be in different functions where you can
then use the target attribute to enable/disable ISAs.

As Andrew says, controlling this per statement is not going to work with the
way GCC handles instruction selection and register allocation (just to name
very few but maybe obvious places).

I'd say WONTFIX (or find the duplicate enhancement request).

[Bug target/106195] RFE: Split -msse into -msse and -fenable-intrinsics

[rguenth at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106195

--- Comment #3 from Richard Biener <rguenth at gcc dot gnu.org> ---
Implementation-wise the simples way would be "sub-functions" that are assembled
"inline".  A frame like we have for nested functions would appear (ideally we'd
be able to optimize those).