[Bug target/106532] riscv fails to build enabling ZBA/ZBB/ZBC/ZBS by default for 32bit

["pinskia at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106532

--- Comment #6 from Andrew Pinski <pinskia at gcc dot gnu.org> ---
Oh why oh why:
  /* Check whether the constant can be loaded in a single
     instruction with zbs extensions.  */
  if (TARGET_64BIT && TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (INTVAL (op)))
    return false;


But:
  if (TARGET_ZBS && SINGLE_BIT_MASK_OPERAND (value))
    {
      /* Simply BSETI.  */
      codes[0].code = UNKNOWN;
      codes[0].value = value;

      /* RISC-V sign-extends all 32bit values that live in a 32bit
         register.  To avoid paradoxes, we thus need to use the
         sign-extended (negative) representation (-1 << 31) for the
         value, if we want to build (1 << 31) in SImode.  This will
         then expand to an LUI instruction.  */
      if (mode == SImode && value == (HOST_WIDE_INT_1U << 31))
        codes[0].value = (HOST_WIDE_INT_M1U << 31);

      return 1;
    }