[Bug target/106769] New: PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[Bug target/106769] New: PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[jens.seifert at de dot ibm.com]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

            Bug ID: 106769
           Summary: PPCLE: vec_extract(vector unsigned int) unnecessary
                    rldicl after mfvsrwz
           Product: gcc
           Version: 11.2.0
            Status: UNCONFIRMED
          Severity: normal
          Priority: P3
         Component: target
          Assignee: unassigned at gcc dot gnu.org
          Reporter: jens.seifert at de dot ibm.com
  Target Milestone: ---

#include <altivec.h>

unsigned int extr(vector unsigned int v)
{
   return vec_extract(v, 2);
}

Generates:

_Z4extrDv4_j:
.LFB1:
        .cfi_startproc
        mfvsrwz 3,34
        rldicl 3,3,0,32
        blr
        .long 0
        .byte 0,9,0,0,0,0,0,0
        .cfi_endproc


The rldicl is not necessary as mfvsrwz already wiped out the upper 32 bits of
the register.

[Bug target/106769] PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[guihaoc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

HaoChen Gui <guihaoc at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
           Assignee|unassigned at gcc dot gnu.org      |guihaoc at gcc dot gnu.org
                 CC|                            |guihaoc at gcc dot gnu.org

--- Comment #1 from HaoChen Gui <guihaoc at gcc dot gnu.org> ---
The problem only occurs below P9. It can be reproduced with -mcpu=power8

[Bug target/106769] PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[guihaoc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

HaoChen Gui <guihaoc at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
   Last reconfirmed|                            |2023-05-31
             Status|UNCONFIRMED                 |ASSIGNED
     Ever confirmed|0                           |1

[Bug target/106769] PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[bergner at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

Peter Bergner <bergner at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
                 CC|                            |aagarwa at gcc dot gnu.org,
                   |                            |bergner at gcc dot gnu.org

--- Comment #2 from Peter Bergner <bergner at gcc dot gnu.org> ---
I wonder if Ajit's REE changes catch this unneeded zero extension?

[Bug target/106769] PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[guihaoc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

--- Comment #3 from HaoChen Gui <guihaoc at gcc dot gnu.org> ---
(In reply to Peter Bergner from comment #2)
> I wonder if Ajit's REE changes catch this unneeded zero extension?

mfvsrwz can be defined as a zero-extend on a vector select other than a SI mode
move from "wa" to "r". Then the combine pass can help us eliminate the
redundent zero-extend. I will submit a patch for it.

[Bug target/106769] PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

--- Comment #4 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by HaoChen Gui <guihaoc@gcc.gnu.org>:

https://gcc.gnu.org/g:a79cf858b39e01c80537bc5d47a5e9004418c267

commit r14-3236-ga79cf858b39e01c80537bc5d47a5e9004418c267
Author: Haochen Gui <guihaoc@gcc.gnu.org>
Date:   Wed Aug 16 14:21:09 2023 +0800

    rs6000: Generate mfvsrwz for all platforms and remove redundant zero extend

    mfvsrwz has lower latency than xxextractuw or vextuw[lr]x.  So it should be
    generated even with p9 vector enabled.  Also the instruction is already
    zero extended.  A combine pattern is needed to eliminate redundant zero
    extend instructions.

    gcc/
            PR target/106769
            * config/rs6000/vsx.md (expand vsx_extract_<mode>): Set it only
            for V8HI and V16QI.
            (vsx_extract_v4si): New expand for V4SI extraction.
            (vsx_extract_v4si_w1): New insn pattern for V4SI extraction on
            word 1 from BE order.
            (*mfvsrwz): New insn pattern for mfvsrwz.
            (*vsx_extract_<mode>_di_p9): Assert that it won't be generated on
            word 1 from BE order.
            (*vsx_extract_si): Remove.
            (*vsx_extract_v4si_w023): New insn and split pattern on word 0, 2,
            3 from BE order.

    gcc/testsuite/
            PR target/106769
            * gcc.target/powerpc/pr106769.h: New.
            * gcc.target/powerpc/pr106769-p8.c: New.
            * gcc.target/powerpc/pr106769-p9.c: New.

[Bug target/106769] PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[guihaoc at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

HaoChen Gui <guihaoc at gcc dot gnu.org> changed:

           What    |Removed                     |Added
----------------------------------------------------------------------------
             Status|ASSIGNED                    |RESOLVED
         Resolution|---                         |FIXED

--- Comment #5 from HaoChen Gui <guihaoc at gcc dot gnu.org> ---
fixed

[Bug target/106769] PPCLE: vec_extract(vector unsigned int) unnecessary rldicl after mfvsrwz

[cvs-commit at gcc dot gnu.org]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106769

--- Comment #6 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by HaoChen Gui <guihaoc@gcc.gnu.org>:

https://gcc.gnu.org/g:c1e474785859c9630fcae19c8d2d606f5642c636

commit r14-4485-gc1e474785859c9630fcae19c8d2d606f5642c636
Author: Haochen Gui <guihaoc@gcc.gnu.org>
Date:   Mon Oct 9 14:34:46 2023 +0800

    rs6000: support 32bit inline lrint

    gcc/
            PR target/88558
            * config/rs6000/rs6000.md (lrint<mode>di2): Remove TARGET_FPRND
            from insn condition.
            (lrint<mode>si2): New insn pattern for 32bit lrint.

    gcc/testsuite/
            PR target/106769
            * gcc.target/powerpc/pr88558.h: New.
            * gcc.target/powerpc/pr88558-p7.c: New.
            * gcc.target/powerpc/pr88558-p8.c: New.