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From: "vineetg at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>
To: gcc-bugs@gcc.gnu.org
Subject: [Bug tree-optimization/106888] [RISCV] Negative optimization that excess andi instructions are generated in gcc.dg/pr90838.c
Date: Fri, 21 Apr 2023 21:18:12 +0000 [thread overview]
Message-ID: <bug-106888-4-jneL5Hrqss@http.gcc.gnu.org/bugzilla/> (raw)
In-Reply-To: <bug-106888-4@http.gcc.gnu.org/bugzilla/>
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=106888
--- Comment #7 from Vineet Gupta <vineetg at gcc dot gnu.org> ---
(In reply to Roger Sayle from comment #5)
> Created attachment 54905 [details]
> proposed patch
>
> This patch should fix this problem, by adding another pattern the machine
> description to also recognize zero_extend of clz/ctz/pcnt, matching the
> current pattern that only matches sign_extend. Clearly for SI operands, the
> result must always be 0..32, so sign extension and zero extension are
> equivalent, and the zero extension is perhaps (now) the preferred canonical
> form.
Thx for the patch Roger, but as Jeff noted, it alone is not enough and
generates same extra ANDI. Would you have expected combine to recog() the new
pattern ?
next prev parent reply other threads:[~2023-04-21 21:18 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-08 9:36 [Bug regression/106888] New: [RISCV] Excess " shihua at iscas dot ac.cn
2022-09-08 9:46 ` [Bug tree-optimization/106888] [RISCV] Negative optimization that excess " shihua at iscas dot ac.cn
2023-04-20 19:00 ` pinskia at gcc dot gnu.org
2023-04-20 23:06 ` vineetg at gcc dot gnu.org
2023-04-20 23:44 ` law at gcc dot gnu.org
2023-04-21 17:27 ` roger at nextmovesoftware dot com
2023-04-21 17:38 ` law at gcc dot gnu.org
2023-04-21 21:18 ` vineetg at gcc dot gnu.org [this message]
2023-04-21 22:07 ` law at gcc dot gnu.org
2023-04-22 0:08 ` vineetg at gcc dot gnu.org
2023-04-22 0:16 ` law at gcc dot gnu.org
2023-05-20 2:55 ` cvs-commit at gcc dot gnu.org
2023-05-20 3:03 ` law at gcc dot gnu.org
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