[Bug target/108654] Incorrect codegen of RVV GCC

["cvs-commit at gcc dot gnu.org" <gcc-bugzilla@gcc.gnu.org>]

https://gcc.gnu.org/bugzilla/show_bug.cgi?id=108654

--- Comment #1 from CVS Commits <cvs-commit at gcc dot gnu.org> ---
The master branch has been updated by Kito Cheng <kito@gcc.gnu.org>:

https://gcc.gnu.org/g:247cacc9e381d666a492dfa4ed61b7b19e2d008f

commit r13-6524-g247cacc9e381d666a492dfa4ed61b7b19e2d008f
Author: Pan Li <pan2.li@intel.com>
Date:   Tue Mar 7 20:05:15 2023 +0800

    RISC-V: Bugfix for rvv bool mode precision adjustment

    Fix the bug of the rvv bool mode precision with the adjustment.
    The bits size of vbool*_t will be adjusted to
    [1, 2, 4, 8, 16, 32, 64] according to the rvv spec 1.0 isa. The
    adjusted mode precison of vbool*_t will help underlying pass to
    make the right decision for both the correctness and optimization.

    Given below sample code:

    void test_1(int8_t * restrict in, int8_t * restrict out)
    {
      vbool8_t v2 = *(vbool8_t*)in;
      vbool16_t v5 = *(vbool16_t*)in;
      *(vbool16_t*)(out + 200) = v5;
      *(vbool8_t*)(out + 100) = v2;
    }

    Before the precision adjustment:

    addi    a4,a1,100
    vsetvli a5,zero,e8,m1,ta,ma
    addi    a1,a1,200
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a4)
    // Need one vsetvli and vlm.v for correctness here.
    vsm.v   v24,0(a1)

    After the precision adjustment:

    csrr    t0,vlenb
    slli    t1,t0,1
    csrr    a3,vlenb
    sub     sp,sp,t1
    slli    a4,a3,1
    add     a4,a4,sp
    sub     a3,a4,a3
    vsetvli a5,zero,e8,m1,ta,ma
    addi    a2,a1,200
    vlm.v   v24,0(a0)
    vsm.v   v24,0(a3)
    addi    a1,a1,100
    vsetvli a4,zero,e8,mf2,ta,ma
    csrr    t0,vlenb
    vlm.v   v25,0(a3)
    vsm.v   v25,0(a2)
    slli    t1,t0,1
    vsetvli a5,zero,e8,m1,ta,ma
    vsm.v   v24,0(a1)
    add     sp,sp,t1
    jr      ra

    However, there may be some optimization opportunates after
    the mode precision adjustment. It can be token care of in
    the RISC-V backend in the underlying separted PR(s).

    gcc/ChangeLog:

            PR target/108185
            PR target/108654
            * config/riscv/riscv-modes.def (ADJUST_PRECISION): Adjust VNx*BI
            modes.
            * config/riscv/riscv.cc (riscv_v_adjust_precision): New.
            * config/riscv/riscv.h (riscv_v_adjust_precision): New.
            * genmodes.cc (adj_precision): New.
            (ADJUST_PRECISION): New.
            (emit_mode_adjustments): Handle ADJUST_PRECISION.

    gcc/testsuite/ChangeLog:

            PR target/108185
            PR target/108654
            * gcc.target/riscv/rvv/base/pr108185-1.c: New test.
            * gcc.target/riscv/rvv/base/pr108185-2.c: New test.
            * gcc.target/riscv/rvv/base/pr108185-3.c: New test.
            * gcc.target/riscv/rvv/base/pr108185-4.c: New test.
            * gcc.target/riscv/rvv/base/pr108185-5.c: New test.
            * gcc.target/riscv/rvv/base/pr108185-6.c: New test.
            * gcc.target/riscv/rvv/base/pr108185-7.c: New test.
            * gcc.target/riscv/rvv/base/pr108185-8.c: New test.

    Signed-off-by: Pan Li <pan2.li@intel.com>
    Co-authored-by: Ju-Zhe Zhong <juzhe.zhong@rivai.ai>